TSEK06 8-Bit Successive Approximation ADC Project

TSEK06 VLSI Chip Design Project 8 bit SAR-‐ADC [email protected]

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Successive Approximation ADC

Version 0.2


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Successive Approximation ADC Project Group: 05

Linkoping University, ISY, Electronics Devices

Participants of the group Name Responsibility Phone Email

Hiwa Mobaraz Team leader 0735812570 [email protected]

Ming-Jie, Yang Customer Relation 0700056658 [email protected]

Ching, Hsu Implementation 0704996070 [email protected]

Naga Thejus Sambasivan Mruthyunjaya

Simulation & Evaluation

0707288425 [email protected]

Karthikeyan Krishnamourthy

Documentation 0707348672 [email protected]

All Responsible for design

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Customer and Supervisor: Martin Nielsen-Lönn Office: B building 2D: 555, Phone: 013-288946, Fax: 013-139282 Email:

mailto:[email protected]

Course Responsible: Atila Alvandpour ([email protected])


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Documentation history

Version Date Changes Done by Reviewed 0.1 23.05.2014 Initial Draft Thejus and

Karthikeyan Martin

0.2 11.06.2014 2nd Draft Thejus and Karthikeyan


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INDEX

1. INTRODUCTION: .............................................................................................................................. 5 1.1 BACKGROUND ..................................................................................................................................... 5 1.2 OBJECTIVE .......................................................................................................................................... 5 1.3 ORGANISATION ................................................................................................................................... 5

2 IMPLEMENTATION OF SAR ADC ................................................................................................... 6 2.1 INTRODUCTION ................................................................................................................................... 6 2.2 COMPARATOR ..................................................................................................................................... 7 2.3 SAR LOGIC ....................................................................................................................................... 10 2.4 CAPACITIVE DAC ............................................................................................................................. 12 2.5 INTEGRATION OF THE CHIP……………………………………………………………………… ... 14

3. PAD LIST .............................................................................................................................................. 15

4. PCB CONNECTION SPECIFICATION ........................................................................................... 18

5. PERFORMANCE EVALUATION ..................................................................................................... 21 5.1 SCHEMETIC LEVEL ............................................................................................................................. 21 5.2 LAYOUT LEVEL .................................................................................................................................. 22

6. EVALUATION PLAN ......................................................................................................................... 24

7. TIME PLAN .......................................................................................................................................... 26

8. PROJECT EXPERIENCE & EVALUATION .................................................................................. 28

9. REFERENCES ...................................................................................................................................... 29


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CHAPTER 1: INTRODUCTION 1.1 Background Successive approximation A/D converter is very popular and widely used architecture for realising ADC mainly because of the moderate circuit complexity. Most of the current day systems are digital and all the real world signals are analog, A/D converters play a very important role important role as the interface between real world analog signals and digital processing system. Due to its medium resolution, moderate speed and power trade off, SAR-ADC is widely preferred in medical instruments, auxiliary analog-to-digital interfaces of micro-processors, sensor systems and so on. 1.2 Objective In this document, a full custom transistor / layout level implementation of a 3.3 V, 8-bit successive approximation (SAR) ADC at a sampling rate of 1 MS/s is reported. This reported SAR-ADC is designed using AMS 0.35 um CMOS technology. 1.3 Organisation Chapter 2 presents the implementation of the proposed SAR-ADC in transistor/layout level. Chapter 3 would give an idea about the pad list that is being used in this design. Chapter 4 presents the PCB connection specification Chapter 5 presents the performance evaluation of the designed SAR-ADC with respect to SNR, SNDR, SFDR, ENOB and power consumption. Chapter 6 talks about the evaluation Chapter 7 presents the Time plan Chapter 8 is all about the Project experience and evaluation Chapter 9 is References.


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CHAPTER 2: IMPLEMENTATION OF SAR-ADC 2.1 Introduction An analog-to-digital converter can be imagined as a black box, which converts a continuous physical quantity to a digital number that represents the amplitude. The conversion involves sampling and holding of the continuous time quantity at Nyquist rate and binary coding of the samples to get the result. The result is a sequence of digital values that have converted a continuous-time and continuous-amplitude analog signal to a discrete-time and discrete-amplitude digital signal [5]. There are many architectures and algorithms to perform A to D conversion. One such architecture is successive approximation ADC that follows the binary search algorithm for mapping the samples into coding.

Figure 1: Block level view of SAR-ADC

The figure above clearly depicts the block level structure of the SAR-ADC. It contains the following components.

• Sample and hold • An analog comparator • Capacitive DAC • SAR logic register

Both Sample/hold and DAC could be realized through the same component, thus achieving area and power optimization. All the other blocks are described in the upcoming texts.


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2.2 Comparator The comparator is one of the most important components in this design as this provides the link between analog and digital domain. The comparator will be used to detect how close the hold value VH is to the reference voltage VREF, by reading the output of the DAC. Speed and accuracy are the primary concern as far as comparators are concerned. Offset and noise are major problems encountered while designing comparators. Such a dynamic comparator could be designed by cascading a latch-only comparator with a tracking SR latch stage as shown below [2]. The whole operation is divided into two phases – tracking & latching. Latch comparator is preferred also because of its low power configuration.

Figure 2: System level view of the Comparator used in this design

In the above displayed block level description of the comparator, the component COMP_PRESTAGE plays a vital role, which amplifies the received differential signal and outputs the compared value. COMP_REG is a SR Latch, which keeps the comparison result constant for a whole period of clock cycle. Transistor level realization is displayed and explained clearly in the following text.

2.2.1 Latch Comparator (COMP_PRESTAGE)

When clk_bar is low, the reset switches are ON and thus the output node is charged to VDD. At this moment the biasing transistor is turned OFF and hence there is no path for the current to flow from VDD to ground. During this tracking phase, the comparator consumes power only at when the power supply charges output capacitance.

When clk_bar goes high, the reset switches are cut off but now the biasing transistors are ON, the current starts to flow in the differential pairs with the load of cross-coupled inverters. When


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this voltage is lower than VThN, the corresponding gate-connected NMOS is turned off and allows VDD to fully charge its output capacitance. When latching is done, one output is at VDD and the other becomes ground. At this moment, there is no supply current. Therefore, the comparator consumes power only during the regeneration. The SR latch remains in the previous state in the tracking mode.

Figure 3: Comparator pre-stage [2]

Sizing of these transistors are very critical that it could affect the performance and speed of the comparator [2]. By the result and analysis of various simulations, the transistors that are used to amplify the signals are sized to have a width of 2 um and hence the biasing transistor is sized to have a width of 4 um. The transistors that are there in the latch part are designed to have a width of 2.5 um and 1.5 um.

2.2.2 SR-Latch (COMP_REG)

A SR latch is designed by using a Cross-coupled NOR gates at the final stage as pictured below. As mentioned above, The SR latch stores the COMP-PRESTAGE output for a whole period of clock cycle without any changes. Otherwise the comparator output is always precharged to VDD

at the reset mode. Unnecessary signal level change will consume extra power [2].


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Figure 4: SR-Latch (COMP_REG)

2.2.3 Comparator Layout

The following figure is the manually drawn layout for the comparator. Common-centroid technique has been used here for the whole COMP_PRESTAGE so that mismatch errors due to fabrication could be reduced and distributed. It is also made sure that the gates of the differential pair transistors experience the same resistance so that they get the signal at the same time.

Figure 5: Comparator Layout


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2.3 SAR Logic

This is essentially a sequential FSM, which is based on the binary search algorithm [6]. During each successive step, the comparator compares the input voltages. Comparator output, which would be either 0 or 1, will be stored in the SAR register. SAR supports three main operations: First, it shifts the initial guess “one” to the right by one bit; secondly, it loads the result from the comparator by the triggering of next nearest bit; thirdly, it holds the determined bits.

As per the binary search algorithm, first the register is set to midscale (that is, 10000000, where the MSB is set to '1'). MSB of this register is either kept at logical '1' or changed to a logical '0' based on the comparator output. Then the control part moves to the next MSB and makes it logical '1' and does the comparator operation again. This happens all the way down to the LSB. Once this is done, the conversion is complete, and the 8-bit digital word is available in the register.

2.3.1 Hardware realisation

The following is the hardware realization of the SAR logic. It is a logical arrangement of flip-flop based registers such that it acts like a shift register that can remember the previous values of the comparator. The upper register setup is the shift register while the register setup below is the “memory part” remembering the values of the comparator. SAR output is directly fed to the DAC thus they are placed together. A differential DAC is used in this implementation and the SAR is placed in between them as shown below in figure 7. SAR accepts the comparator output (COMP) and clock (clk) as the main inputs. It generated Ena, Ena_bar, Enb, Enb_bar and reset-dac signals, which are used to control the DAC.

Figure6: SAR setup


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Figure 7: SAR sandwiched between the differential DACs


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2.4 Capacitive DAC

2.4.1 Basics of DAC

Figure 8: System level view of DAC [1]

A typical capacitive DAC consisting of an array of N capacitors with binary weighted values plus one "dummy LSB" capacitor is shown above. During the acquisition phase, the array's common terminal is connected to ground and all free terminals are connected to the input signal (Vin). After acquisition, the common terminal is disconnected from ground and the free terminals are disconnected from Vin, in turn trapping charge proportional to the input voltage on the capacitor array. The free terminals of all the capacitors are then connected to ground, driving the common terminal negative to a voltage equal to -Vin. In the binary search algorithm, first step is the free terminal of the MSB capacitor is disconnected from ground and connected to VREF, driving the common terminal in the positive direction by an amount equal to 1/2VREF. When this voltage is compared to ground, the comparator output yields logic '1', implying that the MSB is greater than 1/2VREF. Conversely, if Vin is equal to 1/4VREF, the common terminal voltage is (- 1/4VREF + 1/2VREF) = + 1/4VREF, and the comparator output is logic '0'. Following this, the next-largest capacitor is disconnected from ground and connected to VREF, and the comparator determines the next bit. This continues until all bits have been determined. Binary weighted capacitors are used for the DAC. The S&H function is realized by the DAC itself.

In order to improve the capability of DAC this implementation uses transmission gate instead of a pass transistor at the input of DAC so that the swing range can be full. To have the functionality required above, we need a switch that can “choose” to connect between either the input voltage or the pins of the SAR output. So we need 4 transistors in each switch and therefore 4 signals telling the switch weather it should be connected to input voltage or to the output of SAR. The signals ENa, ENa_bar, ENb, and ENb_bar are therefore needed for each bottom plate switch.


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2.4.2 Layout

Once again common centroid technique has been used here to layout the capacitive array so that the mismatches could be minimized and the errors could be distributed. The unit capacitance was chosen to 8 fF and it was connected in parallel in order to obtain large capacitances as per the common centroid design rules. As stated in the previous report, a differential DAC is being used here, so this part of the design takes most of the space in our design. To make it a bit more compact the switch array is directly connected to the DAC to avoid routing. Also minimal routing has been used inside of the DAC to reduce resistance and parasitic capacitances. Since it is a sensitive part of our design dummy capacitances are used to enclose the whole DAC that is the outer layer is made of dummy unit capacitances to prevent any interference from the external signals.

Figure 9: Layout of DAC with switch array


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2.5 Integration of the chip:

Figure 10: Sketch of the integrated chip

As shown above, SAR is divided into eight similar segments. Thus laying it out was easy due to design reuse. Also a switch array has been designed so that it could be connected with the CAP array. COMP (comparator) is placed on the SAR so as to reduce the routing distance from CAP array back to the COMP.


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3. PAD LIST:

The entire pad frames [4] we use for this project is selected from pre-defined libraries. The pads used in this project are as follows:

1) VDDGNDCORNER:

This pad frame is used for the corner, and this can be instantiated from the library TSEK06_PADLIB. This allows us to get two more pads in the same area. It is used to connect VDD and GND in our design. Since instantiating of different pads is based on the placement of this cell, we place this cell at zero origin (X=0, Y=0) and proceed with others. The layout of VDDGNDCORNER is shown below.

Figure 11: VDDGNDCORNER

2) APRIOP: This pad is used for interfacing analog signals. This can be instantiated from the library IOLIB_ANA_4M. This particular pad frame is suitable for AC signals. In our design we use this pad frame to interface CLK, VinN, VinP and VCM signals.

Figure 12: APRIOP


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3) BUXP: This particular pad is a digital output pad (based on driving strength of the output buffer) with included buffers and ESD protection. There are different versions of this pad based on. In this project BU8P is used to interface VOUT. This pad is found in the library IOLIB_4M.

Figure 13: BUXP

4) ICP:

This particular pad is a digital input pad and is used for CMOS logic levels. It includes ESD protection and a small buffer. It can be instantiated from the library IOLIB_4M. In our design we use it to interface reset signal. The layout of ICP is shown below.

Figure 14: ICP

5) APRIOWP: This pad frame is found in IOLIB_ANA_4M library. It has wider M2 wires and has more capacitance to ground, so it suitable for DC signals. Also, if there is a requirement to create two separate VDD connections we use this pad frame. In our design we use it for Vref signal

Figure 15: APRIOWP


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6) ICCK16P: This pad is used for interfacing digital signals. This can be instantiated from the library IOLIB_4M. In our design we use this pad frame to interface Clk signal because it has in built clock buffers which is more efficient. The layout of ICCK16P is shown below

Figure 16: APRIOWP

After placing all the pads and routing them with our design, the layout would look like the following

Figure 17: Total Chip


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4. PCB CONNECTION SPECIFICATION It is mandatory to create a PCB board with proper connections to every pad in the circuit to measure/check the chip, which has been described so far in the above sections. These PCB connections vary based on the type of signal and the device that is used to generate and measure the signal. The following figure shows the sketch of the layout with the pins numbered.

Figure 18: Sketch of the layout with the pins numbered

The table here gives clear information about all the pins that are shown above in the figure. It contains information about the pin name, type of the signal and the connections that would be used in the PCB board.

Table1: PCB pin list

The text below describes the connections in that are mentioned above in the table.

Pin number Name Type Connection

1 EOC Digital output Pin Array 2 VREF Reference voltage Pin Array + Decoupling 3 VinP Analog input SMA 4 VinN Analog input SMA 5 RESET Digital input Push button (active high) 6 VSS Ground Ground 7 VDD VDD Power supply 8 VCM Reference voltage Pin Array + Decoupling 9 CLK Clock input SMA 10 OUT Digital output Pin Array


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1. Pin Array - This type of connection connects the chip pin to a pin on the PCB. This connection is used for digital inputs/outputs with low frequency. This connection could be easily connected to an oscilloscope or pattern generator.

Figure 19: Pin Array [3] 2. Pin Array + Decoupling – This connection is same as that of the Pin array with an added

advantage to solder on 1206 and 0805 capacitors for decoupling. This connection is widely used for reference voltages.

Figure 20: Pin Array + Decoupling [3]

3. SMA – SMA is used for high-frequency signals like clock or the input analog signals. It consists of a 50 Ohm SMA connector that easily connects to signal generators, spectrum analyzers and oscilloscopes. It also has an option to add 0805 resistor for termination.

Figure 21: SMA [3]

4. Push button – Push button is a standard connection for the RESET button. It acts like a relay switch between the buttons to two different pin lists. When pressed, the button connects to one of the pins, and the other when it is not pressed.


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Figure 22: Push button [3]

5. Ground – This connection is used to connect the chip pin to the global VSS.

Figure 23: Ground [3]

6. Power supply – This connection is being used to connect the chip pin with the global VDD via a jumper. Decoupling capacitors of sizes 1206 and 0805 should also be soldered on for stabilizing the voltage supply and to avoid damage to the chip.

Figure 24: Power supply [3]


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5. PERFORMANCE EVALUATION: 5.1 Schematic Level

To test the performance of the chip after tape out we simulate our design under various ambient conditions and process mismatches, using Spectre tool of Cadence.

1. Ambient temperature T = 0° C 2. Ambient temperature T = 110° C 3. Ambient temperature T = 27° C & cmosws (worst speed process corner) 4. Ambient temperature T = 27° C & cmoswp (worst power process corner) 5. Ambient temperature T = 27° C & cmostm (Typical mean parameters) 6. Ambient temperature T = 110° C & cmosws (worst speed process corner)

Corner SFDR SNDR Power ENOB

Cmostm 60.7 50.9 53.15 uW 8.08

Cmosws 60.5 49.5 54.4 uW 7.93

Cmoswp 56.2 49.8 53.43 uW 7.97

Cmostm(110° C) 56.9 48.9 55.86 uW 7.83

Cmostm (0° C) 59.2 49.9 52.39 uW 8

Cmosws(110° C) 52.4 47 56.6 uW 7.5

Table 2: Process corner (Schematic level)

The above results are for the schematic level. From the above table we can observe that the ENOB and other parameters are good for “cmostm” at 27° C. We get an ENOB more than 8 bits because of the amount of samples we consider (more number of samples, the more realistic ENOB we get). The power consumption of different parts in our SAR ADC is given below

Table 3: Power consumption (Schematic level)

Component Power SAR 38.6 uW DAC 109.9 nW * 2

Comparator 10.81 uW TOTAL 50.62 uW


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Figure 25: Power consumption in schematic level

Since there are two sections of DAC in our design, the power consumed by DAC is multiplied by a factor of 2. Also there is a difference in the total power consumed by 3 uW because of switches which is included in the DAC and SAR logic. 5.2 Layout Level In the same test bench setup our design was evaluated in layout level to examine its performance parameters, and the same is given in the below table:

Corner Power (mW) ENOB SNR SNDR SFDR

cmostm 1.43 7.3 57.3 45.9 52.4

cmosws 1.412 6.7 55.1 42.6 47.4

cmoswp 2.106 6.8 53.5 43.1 50.9

cmostm(110° C) 1.802 7.5 55.3 46.7 56.8

cmostm(0° C ) 1.464 7.2 55.3 45 53

cmosws(110° C) 1.669 6.5 54.2 41.2 47.6

Table 4: Parameters in various process corners (Layout level)

Power Consumption

SAR DAC COMP Others


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Spectrum Under normal conditions, i.e. for the corner “cmostm” at 27°C we get the following spectrum with the help of Matlab. This corresponds to the ENOB of 7.3

Figure 26: Spectrum of the chip in “cmostm”

Conclusions

• It can be deduced from the above table, that the ENOB and other parameters like SNR, SFDR and SNDR drops when we consider the layout and include parasitic capacitances.

• Particularly when we integrated the layout of DAC along with its switches the ENOB dropped drastically from 8 to 6.3. The routings were optimized to get a better ENOB.

• Also we can see a drastic increase in the power consumption after our design was

integrated with the padding. In fact, the padding consumes more power than our design.


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6. EVALUATION PLAN After the integration our design with different pads, the following setup is used to simulate the whole design in Cadence.

Figure 27: Evaluation setup After tape out, to evaluate the real chip, a similar setup is required and along with the following equipment

1) Evaluation board (details given in the next section) 2) Signal generator with two ports 3) Dual port DC voltage supply 4) Oscilloscope 5) Connecting probes.

Steps to be followed to evaluate the chip: • The test bench should be set up similar to that we use in the Cadence. Firstly the taped

out chip is interfaced on the custom made Evaluation board. • We connect the VinN and VinP of the chip to the signal generator using connecting probes. • The reference voltage (Vcm) is connected to DC voltage supply of 1.65V and the VDD

pin of the chip is connected to the DC voltage supply set at 3.3 V. • The output pins (OUT and EOC) of the chip are connected to the oscilloscope.

The figure that is shown below depicts the setup that should be used to test the chip. It also gives information on the devices that would be required for the measurement.


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Figure 28: Setup that must be used for testing

• The values have to be observed at the negative edge of the clock (when the clock is low). • The “reset” indicates end of one sample, so when it goes low the next sample’s LSB is

ready. • When “reset” goes low, we have to ignore one negative clock edge and start measuring

the values again for the next coming 8 low clock edges (new sample). • By doing so we can observe the waveforms with the help of the spectrum analyzer, which

is similar to the one shown below.

Figure 29: Simulated timing diagram

Green – Output Purple - Reset Red – Clock

After one clock cycle post every reset, we start measuring the output, which should be equal to (01111111) according to our setup. Instead we get 01111110, and because of this kind of errors our ENOB drops below 8, which is equal to 7.3


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7. TIME PLAN As far as time plan is concerned, this total project can be divided into 3 main parts.

1. High level design and design topology 2. Transistor level design and verification 3. Layout level implementation and chip assembly.

An approximate time allocation could be summarized as High-level design and design topology consumed 20%, Transistor level design and verification consumed 40% and Layout level implementation and chip assembly took the remaining 40%. The table below gives a clear picture on the activities and our comments against it.

Activities Description Comments on “What we thought vs. How it went “

Time plan Make time plan and keep it up to date ----

Pre-study Litterateur search, find good potential implementation structures.

Finding good implementable structures was not so difficult as these chips are well established.

High level modeling Create a high level model for a design that functions according to the specification

We thought Verilog design as well the integration would be easy but we went wrong in the algorithm which consumed so much of time

Status report for TG1 Writing the high level modeling report ----

Transistor block design

Create schematics of all blocks and verify that they work according to specification.

We thought transistor level design would be first hard task but on contrary we finished it well before the planned time.

Chip designs on transistor level

Complete schematic of chip and chip verification

Integration in transistor level and improving the ENOB was not hard but it consumed more time than we planned.

Status report for TG2 Writing the transistor level report ----

Block layout and verification

Make block layout and verify through LVS and DRC.

We thought layout would be the hardest in the whole project but we were much faster than planned because of the design reuse from the labs and good planning.

PAD frame Layout and decide which pads to use, DRC and LVS. It was easier than we thought

Chip core layout Global place and route, DRC, LVS, verification.

This consumed more time than we planned as we committed some mistakes


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Generate fill and

additional layers and Tape-Out

Stream out and run the needed scripts

Pad integration was somewhat easier than what we taught

Verification plan Decide what should be measured and how.

Project report Final project report ----

Project presentation Prepare and present your results to your course colleagues.

Done

Table5: Time plan


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8. PROJECT EXPERIENCE AND EVALUATION

As a team we found this project to be successful but extremely time-consuming and challenging. The main problem was our knowledge before starting the project, especially because we thought we had enough knowledge, which was not the case. Therefore neither the time plan nor the work was good enough to cover the needs and we found out that we need to do this in whole another way, sadly a bit too late. This was the main source of stress during the hard times and late nights but since we never gave up we managed to finish the project in time. We could have got a bit more help regarding the practical aspects on our project, because we did not have enough background knowledge. Also the balance of work and hours spent on the project was neither right nor fair. We think this was mostly again because of the background and knowledge for electronic design and product development. Over the longer time, especially during the layout we could help each other a bit more and every one had something to do. We are glad that we are done and a tip for next year students would be to ask a lot before the project starts so the planning is not wrong and also the teachers should give a more detailed info about what should be build and common mistakes should also be warned for. Apart from the points above, we learnt how to route a signal and it was a good learning. The lab manual was good and useful. We would like to extend out thanks to our supervisor Martin and Prof. Atila Avlandpour for their help and time.


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9. REFERENCES 1. 8 bit SA-ADC Project description and requirement spec. Manual from TSEK06 VLSI chip design course, 2014 2. Dai Zhang, “Design and Evaluation of an Ultra-Low Power Successive Approximation ADC”, Student thesis, Linköping University, Department of Electrical Engineering, 2009. 3. “PCB Connection Specification” from TSEK06 VLSI chip design course, 2014 4. Project Guide - TSEK06 VLSI Chip Design Project and TSEK11 Evaluation of an IC 5. http://en.wikipedia.org/wiki/Analog-to-digital_converter referred on 15/03/2014 6. http://en.wikipedia.org/wiki/Successive_Approximation_ADC referred on 15/03/2014

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TSEK06 8-Bit Successive Approximation ADC Project

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