Major Project PresentationDesigning and development of forward error correction logic in VHDL.By
Ishan Upadhyay-R790211019Abhipraiya Bhatnagar-R790211002
2015 UPESMentor Prof. S. Choudhoury 2012 UPES 2012 UPESMar 2012122015 UPESApril 2015IntroductionObjectiveLiterature reviewBlock diagramTimelineDetailed component list/If any hardwareDetail software toolsMethodologyOutcomeFuture planConclusionReferencesContent 2012 UPESMar 20122015 UPESApril 2015Introduction
Data communication basically involves transfers of data from one place to another or from one point of time to another. Error may be introduced by the channel which makes data unreliable for user. In doing so there may be situations that error may be encountered in the channel due to various factors like Electromagnetic Interferences, Cross talk and Bandwidth limitation etc.Hence we need different error detection and error correction schemes.Mar 2012 2012 UPESMar 20123April 20152015 UPESObjectiveErrors introduced by the channel should be detected at the receiver end.Designing of turbo code algorithm . Implementation of code using VHDL and burning it into Spartan-6 kit.Correcting the error using FEC.Mar 2012 2012 UPESMar 201244Literature review2015 UPESApril 2015Turbo codes achieve performance near the Shannon limit. Standard sequential VLSI implementation of turbo decoding requires many iterations and incurs a long latency, which cannot be tolerated in some applications. A novel parallel VLSI architecture for turbo decoding is described, comprising multiple SISO elements, operating jointly on one turbo coded block, and a new parallel interleaver. Latency is reduced ten-fold and more and throughput is increased up to eight-fold relative to sequential decoders, using the same area of silicon, and achieving the same coding gain. The parallel architecture scales favorablylatency and throughput improve with growing block size and chip area.Mar 2012 2012 UPESMar 20125Block diagram
2015 UPESApril 2015Turbo EncoderMar 2012 2012 UPESMar 2012April 20152015 UPESTurbo Decoder
Mar 2012 2012 UPESMar 20127TIMELINEPHASE I-We perform the comparative study between different FECs like Shanon Fanon, Hoffmann, Cyclic, Convolution, Turbo Coding. (2-3 weeks)PHASE II-Selection of best code is done for Forward error correction and learning basic function of Spartan-6 kit.(2-3weeks)PHASE III-Implement the code using VHDL programming and burning code on the Spartan-6 kit.(1-2 weeks)PHASE IV-Removing the problem in the code.(1-2 weeks)PHASE V-Finally the perfect code for Forward error correction is implemented on FPGA Spartan-6 kit.(3-4 weeks)
April 20152015 UPESMar 2012 2012 UPESMar 2012Detail software toolsApril 20152015 UPES Spartan-6 FPGA Board & kit.Software required- Project Navigator, Xilinx Support
Mar 2012 2012 UPESMar 20129UniquenessApril 20152015 UPESMethodology
Turbo codes:- In Turbo encoding scheme standard is a parallel concatenated convolutional code and one interleaver. The function of the interleaver is to take a block of N-bit data and produce a permutation of the input data block.The performance of a Turbo code depends critically on the interleaver structure. The basic Turbo coding rate is 1/3. It encodes an N-bit information data block in to a code word with 3N+12 data bits, where 12 tail bits are used for trellis termination.Mar 2012 2012 UPESMar 2012Methodologycont..
A turbo decoder consists of two decoders separated by an interleaver that permutes the input sequence. The decoding is an iterative process in which the so-called extrinsic information is exchanged between decoders. Each Turbo iteration is divided in to two half iterations. During the first half iteration, decoder 1 is enabled. Likewise, during the second half iteration, decoder 2 is enabled. This iterative process repeats until the decoding has converged or the maximum number of iterations has been reached.April 20152015 UPESMar 2012 2012 UPESMar 2012INPUTX1 X2X3X4X5X6X7X8X9X10X11X12X13X14X15Odd-even interleaver outputEncoder output without interleavingX1X2X3X4X5X6X7X8X9X10X11X12X13X14X15Y1-Y3-Y5-Y7-Y9-Y11-Y13-Y15Encoder output with row-column interleavingX1X2X3X4X5X6X7X8X9X10X11X12X13X14X15-Z6-Z2-Z12-Z8-Z4-Z14-Z10-Final output of the encoderY1Z6Y3Z2Y5Z12Y7Z8Y9Z4Y11Z14Y13Z10Y152015 UPESApril 2015Mar 2012 2012 UPESMar 2012Channel Used for transmissionAdditive White Gaussian Noise Channel (AWGN) The modifiers denote particular characteristics as below, 'Additive' because it gets added to signal noise that might be intrinsic or extrinsic to the information system. 'White' refers to idea that it has even power across the frequency band of the information system. It is an analogy to the color white which has uniform emissions at all frequencies in the visible spectrum. Gaussian because it has a normal distribution over the time domain with an average time domain value of zero.
April 20152015 UPESMar 2012 2012 UPESMar 2012Step wise implementation
First Simulink model for turbo encoder and Turbo decoder is developed The VHDL coding is made and verifiedThe HDL codes are synthesized by Xilinx Support Design ComplierFinally the physical design is implemented on Spartan-6 FPGA Board & kit2015 UPESApril 2015Mar 2012 2012 UPESMar 2012Outcome or ResultVarious forward error correction techniques have been studied and compared. Among all the FECs, Turbo code has been found to be the most suitable code because of the low coding complexity and high coding rate etc.Bit Error Rate: 0.0368951613 @ iteration 0 (no decoding) 0.0027355688 @ iteration 1 0.0001380629 @ iteration 2 0.0000722789 @ iteration 3 0.0000255319 @ iteration 4 0.0000212947 @ iteration 5Signal-to-noise ratio: 5.1 dB2015 UPESFeb 2015April 2015Mar 2012 2012 UPESMar 2012Xilinx implementation imageInterleaver
Mar 2012 2012 UPESMar 2012Interleaver
Mar 2012 2012 UPESMar 2012Encoder
Mar 2012 2012 UPESMar 2012Encoder
Mar 2012 2012 UPESMar 2012encoder
Mar 2012 2012 UPESMar 2012Future planAt this stage our future plan is to design and develop the Forward Error correction logic circuit using VHDL programming on FPGA kit and observe the working of the Turbo code derive system.2015 UPESApril 2015Mar 2012 2012 UPESMar 2012ConclusionTurbo code performance simulation on AWGN Channel1. Number of iterations of the Turbo code performanceWith the increase of the signal to noise ratio, increasing the number of iterations will make the bit error rate is drastically reduced, but when a certain number of iterations is reached, and then increase the number of iterations is also not significantly improve the BER. 2. Encoding rate of Turbo code performance The puncturing process may be useful, Seen by the simulation results in the case of the same SNR, the code rate is 1/3 of the code having a higher bit error rate performance than the code rate is 1/2 code. Because the bit rate of 1/2 Turbo Code .2015 UPESApril 2015Mar 2012 2012 UPESMar 2012References
http://www.google.com University of South Australia, Institute for Telecommunications Research, Turbo coding research group. http://www.itr.unisa.edu.au/~steven/turbo/. S.A. Barbulescu and S.S. Pietrobon. Turbo codes: A tutorial on a new class of powerful error correction coding schemes. Part I: Code structures and interleaver design. J. Elec. and Electron. Eng., Australia, 19:129142, September 1999.
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