A Tutorial for TetraMAX & Its A Tutorial for TetraMAX & Its Fault SimulatorFault Simulator

A Tutorial for TetraMAX & Its A Tutorial for TetraMAX & Its Fault SimulatorFault Simulator

Chih-Yen Lo

Mar.10 2006

Chih-Yen Lo & Cheng-Wen Wu 2

OutlineOutline TetraMAX usage

TetraMAX fault simulator usage

Chih-Yen Lo & Cheng-Wen Wu 3

ConventionsConventions Brackets ([ ]) denote optional choices. Command

is still valid when you omit the choice

A vertical bar ( | ) separates different items from which you can choose single one

An asterisk ( * ) indicates the default setting in a list of choices.

Angle brackets (<>) denote a grouping of related items

Italics indicate a user-defined items

\ denotes the change line sign

Chih-Yen Lo & Cheng-Wen Wu 4

Invoking TetraMAXInvoking TetraMAX Invoking TetraMAX

tmax [ command_file ][ -shell | -gui ]

On-line help Using the TetraMAX user guide

/usr/cad/synopsys/sold/cur/doc/online/test/tmax_ug.pdf

Text-only help Type “help command_name” in TetraMAX shell

mode or in the command line in GUI mode Use pull-down menu Help in GUI mode

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Before Set Up TetraMAXBefore Set Up TetraMAX Require following information in your design

Clock ports Asynchronous set and reset ports Scan chain input and output ports Any ports that place the design in test mode and

their active states Any ports that enable shifting of scan chains and

their active states Any ports that globally control bidirectional drive

and their active states

All the information should include in you STIL file Check “Chap.7 STIL Procedure Files” in

tmax_ug.pdf

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Basic ATPG Design Flow (1/4)Basic ATPG Design Flow (1/4) 1. If necessary, preprocess your netlist to meet

the requirements of TetraMAX.

2. Read in the netlist. build read netlist xxxxx_syn.v

3. Read in the library models. read netlist

home/users/cic/CIC_CBDK018_UMC_ Artisan_V1.1/CIC/Verilog/umc18.v -noabort

4. Build the ATPG design model run build_model top_module_name

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Basic ATPG Design Flow (2/4)Basic ATPG Design Flow (2/4) 5. Read in the STIL test protocol file, generated

by DFT Compiler or another source. Perform test DRC and make any necessary corrections. drc add pi constraints 1 HRESTN set drc -allow_untestable_set_resets run drc file_name.stil report rules -fail > file_name.rpt report violations -all >> file_name.rpt

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Basic ATPG Design Flow (3/4)Basic ATPG Design Flow (3/4) 6. To prepare the design for ATPG, set up the

fault list, analyze buses for contention, and set the ATPG options add faults -all set atpg –merge high -verbose \ -abort_limit number –coverage number \ -capture_cycles number

7. Run automatic test pattern generation run atpg basic_scan_only

8. Review the test coverage and rerun ATPG if necessary

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Basic ATPG Design Flow (4/4)Basic ATPG Design Flow (4/4) 9. Run pattern compression

run pattern_compress number –max number \ -reset_au_faults

10. Save the test patterns and fault list. write patterns file_name_atpg.stil –format stil \ -replace Write faults fault_file_name.all –all -replace

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TetraMAX Fault SimulatorTetraMAX Fault Simulator Invoking TetraMAX as above

All the detail for TetraMAX fault simulation are listed in “Chap.11 Fault Simulation” of tmax_ug.pdf

Next, we will have a simple fault simulation flow for non-scan test patterns

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Fault Simulation Flow (1/3)Fault Simulation Flow (1/3) 1. Prepare the functional test patterns for fault

simulation. Check “Chap.12 Test Pattern Data” of tmax_ug.pdf

2. Prepare the design for fault simulation build read netlist xxxxx_syn.v read netlist home/users/cic/CIC_CBDK018_UMC_

Artisan_V1.1/CIC/Verilog/umc18.v -noabort run build_model top_module_name drc add clock 0 clk or add clock 1 RESETB set drc –nofile (non-scan test pattern) run drc (non-scan test pattern)

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Fault Simulation Flow (2/3)Fault Simulation Flow (2/3) 3. Read in the external functional patterns

test set patterns ext pattern_file_name.v Check “Chap.12 Test Pattern Data” of for detail

4. Perform a good machine simulation add faults –all drc set simulation –measure pat –oscillation 20 2 -verbose test run simulation -sequential

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Fault Simulation Flow (3/3)Fault Simulation Flow (3/3) 5. Perform fault simulation to fault-grade the

functional test patterns drc set simulation –measure pat –oscillation 20 2 \ -verbose test run fault_sim -store –sequential report summaries

6. Write the fault list to perform ATPG later write faults file.dat –all –uncollapsed -rep