Tutorial Icfb

8/10/2019 Tutorial Icfb

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Microelectronica

Full-Custom Design with Cadence

Tutorial

AustriaMicroSystems C35B3 (HIT-Kit 3.70)

Marcelino Santos

rea Cientficade Electrnica


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Table of contends

1. Starting Cadence ............................................................................................................................ 3Starting Cadence for the first time ..................................................... ............................................ 3Starting Cadence again .................................................... ........................................................... .... 4

2. Creating the Schematic................................................................................................................. 4Creating a library and a schematic cell view ........................................................ ........................ 4Drawing the schematic ..................................................... ........................................................... .... 5

Adding the MOS transistors ...................................................... ...................................................... 5Placing VDD and GND supply.................................................. ...................................................... 7

Adding input and output pins .................................................... ...................................................... 7Adding wires and wire names................................................... ...................................................... 7Miscellaneous .......................................................... ............................................................ ............. 7Saving the design .................................................... ............................................................ ............. 8

3. Creating the Symbol ...................................................................................................................... 8

4. Schematic Simulation.................................................................................................................... 9Creating a test bench (schematic for simulation) .......................................................... .............. 9Simulating the schematic ...................................................... ........................................................ 11Waveform Window ............................................................ ........................................................... .. 13Expressions .................................................... ............................................................ ..................... 14Parametric analysis ........................................................... ........................................................... .. 15

5. Creating the Layout...................................................................................................................... 17Starting the layout tool .................................................. ....................................................... .......... 17Layer Selection Window (LSW)...................................................... .............................................. 17Initialize the layout................................................... ............................................................ ........... 17Settings for the Virtuoso Layout XL Editor........................................................ .......................... 19Layout creation - placing the components ........................................................ .......................... 20

Routing between the components .................................................. ............................................. 25Layout creation - miscellaneous..................................................... .............................................. 27

6. Design-Rule-Check (DRC) .......................................................................................................... 28Starting DRC ............................................................ ............................................................ ........... 28Processing DRC errors................................................. ........................................................ ......... 29

7. Extraction....................................................................................................................................... 31Starting extraction ................................................... ............................................................ ........... 31

8. Layout-versus-Schematic Check (LVS Check) ..................................................................... 31Starting LVS checking .................................................. ....................................................... .......... 32

Analyzing LVS results ................................................... ....................................................... .......... 32Parasitics probing .................................................... ............................................................ ........... 33

9. Post-Layout Simulation.............................................................................................................. 34

10. GDSII Export of the Cell Layout.............................................................................................. 34


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Acknowledgements:The author thanks Jos Jesus and Slvia Gomes for their precious helpin the elaboration of this tutorial.

1. Starting Cadence

Starting Cadence for the first time

At first, open a terminal program and source the configuration file cad.init.

> source cad.init

Then create a directory for the project files and change to that directory.

> mkdir cds_tutorial> cd cds_tutorial

Then a script from AustriaMicroSystems is used to initialize the Cadence Custom IC Designtools with the process technology C35B3 (-tech c35b3). Also the Command InterpreterWindow (CIW) is started in mode Front-To-Back Design (-mode fb).

> ams_cds -mode fb -tech c35b3

After Cadence has been started two important windows appear:

Command Interpreter Window (CIW): To start Cadence tools and enter SKILLcommands. The output of the running tools are displayed here and closing thiswindow causes the whole suite to close.

Library Manager: To manage the cells with their various views in the libraries. Herenew cells and libraries are created. This tool can be started from the CIW via themenu bar: Tools - Library Manager.

Close the whats new windows and select the C35B3C0 process.

The library manager window (Fig. 1) can be used for opening existing libraries or cells orcreating new ones. The left column of the library manager window is a list of the current(accessible) libraries. Among these PRIMLIB contains the transistors you will need for theinverter.

Left click at PRIMLIB. The middle column shows the elements of PRIMLIB. Left click atnmos4. This is the basic n-MOS transistor. In the third, rightmost, column you can seeseveral views of nmos4. You will need the symbolview for the schematic and the layoutview

for building the layout.


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Fig. 1 Library Manager window

Starting Cadence again

If you want to start a new Cadence session in a directory where the Cadence tools havealready been initialized only the following commands are necessary:

> source cad.init> cd cds_tutorial> ams_cds -mode fb

2. Creating the Schematic

Creating a library and a schematic cell view

At first, a new library that will contain the data for the implemented cell must be created. Fromthe menu bar of the Library Manager select

File - New - Library

and enter a name for the new library, e.g. STUDENTS. In the next window we choose toattach the library to an existing techfile. After pressing OK the techfile can be selected: SetTechnology Fileto TECH_C35B3and press OK.

Now we can start to create the schematic of our cell. Select the newly made library andchoose

File - New - Cell View

from the menu bar of the Library Manager. Enter a name for the cell in the appearing form(e.g. inverter1) and check whether the correct options are selected: Library Namemust be set

to STUDENTS, View Name must be set to schematic and Tool must be set to Composer-Schematic in order to start the Virtuoso Schematic Composer. After pressing OK the

Schematic Composer should start automatically.


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Drawing the schematic

The following schematic is now entered into the Schematic Composer:

Fig. 2 Schematic of the inverter.

Before adding instances or wires in the inverter schematic, briefly read the Miscellaneous partin this section.

Adding the MOS transistors

First, add the pMOS and nMOS transistors. Select from the Composer menu bar

Add - Instance(or use the shortcut )

Fill out the form by hand or press the Browsebutton to search the libraries for the appropriatecell. The MOS transistors are in the library PRIMLIBand are calledpmos4and nmos4respectively. To place them in a schematic the selected Viewmust be symbol. After choosingthe right cell, parameters of the cell can be set in the form (Fig. 3). Change the default values

of the transistor width (wpmos = 4 m and wnmos = 1 m) and place each symbol in theschematic using the left mouse button.


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Fig.3 Dialogue box for the transistor properties.


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To hide the Add Instance form during placing press the Hidebutton. To rotate or flip the cellpress the Rotate(shortcut ), Sidewaysor Uside Downbuttons.

Placing VDD and GND supply

Add instances of vdd and gnd supply cells which can be found in the library analogLib.

Adding input and output pins

To add input and output pins select

Add - Pin(shortcut

)

from the menu bar and fill out the appearing form. Give a list of Pin Names separated byspaces, e.g. IN OUT, and select the direction of the first pin in the list (INis an input pin). Nowplace the first pin. To hide the Add Pin form, press the Hidebutton. To rotate or flip the pinpress the Rotate (shortcut ), Sideways or Uside Down buttons.

After placing the first pin its name is automatically deleted from the Pin Names list and thenext pin direction can be changed and the pin placed. Place the input pin INand the outputpin OUT.

Adding wires and wire names

To add wires select

Add - Wire (narrow)(shortcut )

from the menu bar and place wires by clicking on the begin and end point of a wire. Connect

the objects via their connection ports. If the mouse pointer is moved near to a connection portand the port is marked with the diamond symbol the wire can be quick-connected to that portby pressing .

Don't forget to connect the bulk-ports of the pMOS transistors with VDD and the bulk-ports of the nMOS transistors with GND!

To name a wire select

Add - Wire Name(shortcut l)

and fill in a list of wire Namesin the appearing form. To hide the Add Wire Name form during

naming press the Hidebutton. Add the wire names in the order as the appear on the Nameslist by clicking the appropriate wire. Note that wires given the same name are connectedimplicitly. The wires connected to the vdd cell are automatically named vdd! and the wiresconnected to the cell gnd are automatically named gnd!.

Miscellaneous

To zoom in on the schematic select Windows - Zoom - Zoom in(shortcut ) and drag abox around the area of interest. Alternatively, right click and draw the rectangle to zoom in.

To fit the schematic window to the current design select Window - Fit(shortcut ).

To move an object:

Very

useful!


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Select the object and move the mouse pointer over it until the pointer changes to amove-object symbol. Press the left mouse button and move the object.

Select Edit - Move(shortcut ) from the menu bar and select the object to move.

To edit cell instance properties select the cell in the composer window and choose Edit -Properties - Objects(shortcut ) from the menu bar.

In the Composer window you can see which command is currently activated and how manyinstances are currently selected. In the lower status bar you can see the current actionsassigned to the mouse buttons according to the currently activated command.

Multiple objects can be selected by:

Holding down the key and selecting the objects.

Draging a box around them with the mouse pointer while pressing the left mousebutton.

Other useful commands:

command menu bar command shortcut

copy object Edit - Copy

detele object Edit - Delete

rotate object Edit - Rotate

undo last action Edit - Undo

save the design Design - Save

move within window, , ,

redraw window terminate any command

Saving the design

Save the design by choosing

Design - Check and Save(shortcut )

from the menu bar. Possible errors are indicated by flashing markers. These markers can bedeleted by selecting Check - Delete All Markersand pressing OK.

3. Creating the Symbol

Creating a symbol of the cell is necessary if the cell should be instantiated in anotherschematic (i.e. the simulation schematic). The symbol defines the shape your cell will assumein another schematic.

To create the symbol, open the cell schematic in the Virtuoso Composer and select

Design - Create Cellview - From Cellview

and check whether the appearing form is filled in correctly: To View Name must be set tosymbol and Tool / Data Type must be set to Composer-Symbol. After hitting OK the form

Very

useful!

Very

important!


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Symbol Generation Options appear where the initial positions of the pins can be chosen.Press OKafter assigning the pins to the desired lists.

The Virtuoso Schematic Composer will open in symbol-editing mode and a default symbol willbe created for the cell. Now the symbol can be designed.

After finishing the design of the symbol check and save it with: Design - Check and Save.

The final symbol could look like this (click on the picture to enlarge it):

Fig.4 Inverter symbol.

After finishing the design of the symbol check and save it with: Design - Check and Save.

4. Schematic SimulationCreating a test bench (schematic for simulation)

The first step to simulate the inverter is to create a schematic with an instance of the newinverter1 (symbol). To create a schematic refer to section 2. Creating the Schematicof thisdocument. The schematic of the test bench must be created in the library STUDENTS andthe cell should be named inv_test.

The inverter gate in the simulation schematic is of course the cell inverter1 from the librarySTUDENTS.


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Add a instance () of a DC voltage source between vddand gnd. Use the cell vdcfrom thelibrary analogLiband set the parameter DC Voltageto vdd_val V. By connecting this voltagesource to the cells vddand gnd,from the library analogLib, you are defining vdd and gnd forall the cells that use these labels.

Fig.5 vdc instance with parametric DC voltage

In order to generate the input signal for the simulation use a voltage source of type vpulse(rectangular signal) from the library analogLib. Define the voltage source with the followingparameters:

V


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vpulse voltage source at

input IN

Voltage 1 3.3 V

Voltage 2 0.0 V

Delay time 0 s

Rise time 5n s

Fall time 5n s

Pulsewidth

45n s

Period 100n s

Note that all parameters in the previous table can be defined as function of parameters (e.g.Pulse with = input_slew; Pulse with = 50n-input_slew). These parameters must be assignedin the simulator environment, with a constant value or in a parametric analysis.

We also have to name the input wire (e.g. IN) and the output wire (e.g. OUT) so that we canselect them during simulation and plot their voltage curves.

Add a capacitor (cap) of 1pF to the output pin from the library analogLib.

You should end up with the test bench of Fig. 6.

Fig. 6 Test bench for the inverter transient simulation.

Simulating the schematic

After creating the simulation schematic you are ready to simulate the inverter gate. Selectfrom the Composer window of the simulation schematic

Tools - Analog Environment

vdc = vdd_value


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The following simulator settings have to be made:

menu bar command details

Setup - Simulator/Directory/Host- Set Simulatorto spectreS- Also the Project Directorycould be changed here

Setup - Model Path

- Check the model library files. In some cases the library/soft/ams/3.7/spectres/cmos53/tm is referred as cmos15/tm.Double click the library to change, edit and select the CHANGEbutton.

Setup - Temperature - Set Degreesto 25

Setup - Environment- Switch View Listshould be set to spectreS cmos_sch schematic- Stop View Listshould be set to spectreS ahdl

Analyses - Choose

- SetAnalysisto trans- Set Stop Timeto 200n-Accuracy Defaultsshould be set to conservative- A description of the analysis will be listed in the fieldAnalysesof

the Virtuoso Analog Environment tool- To edit theAnalyses entries either double-click on an entry orselectAnalyses Chooseagain

Variables - Copy From Cellview

- Variables in the simulation schematic will be identified and will belisted in the field Design Variablesof the Virtuoso Analog

Environment tool- To edit the Design Variablesentries either double-click on an entryor select Variables - Editfrom the menu bar- Set vdd_valto 3.3V

Outputs - To Be Plotted - Select

On Schematic

- Select the signals to be ploted in the simulation schematic: net(must be named!) => voltage; object node => current into the objectthrough this node- Selected signals will be listed in the field Outputsof the Virtuoso

Analog Environment tool- To edit the Outputsentries either double-click on an entry or selectOutputs - Setupfrom the menu bar

After configuring the simulator it should look like Fig. 7.

Fig. 7 Simulation configuration window.


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To build the netlist and run the simulation select

Simulation - Netlist and Run.

First the simulator output log window appears and shows the simulation progress. After thesimulation has finished the waveform window appears and the selected signals are plotted.

Waveform Window

Fig. 8 Simulation waveform window.

In order to perform arithmetic operations you can use the calculator:

Tools calculator

In the IO area of the calculator window (see Fig. 9) you can type the expression to evaluate(see the list of functions presented) and see the result after clicking eval.


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Fig. 9 Calculator window.

Expressions

It is also possible to enter expressions in the field Outputsof the Virtuoso Analog Environmentto calculate parameters of the cell (propagation delay, output slew, ...) from the simulationresults directly or to plot modified signal curves. These expressions can be tested with theCalculator!

Select Outputs - Setup from the menu bar of the Virtuoso Analog Environment and add thefollowing expression:

Name = propagation delay, Expression = delay(v("/IN" ?result "tran") 1.65 1 "rising"v("/OUT" ?result "tran") 1.65 1 "falling")

The expression propagation delay gives the propagation delay of the gate when the input

value changes from IN = 0 to IN = 1.

Fig. 10 Adding an expression to be evaluated or displayed.

IO area


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After plotting the expression with Results - Plot Outputs - Expressions the result of theexpression for the propagation delay is displayed in the field Outputsof the Virtuoso AnalogEnvironment.

The current curve of an object node can be accessed with the command i("/object/node"?result "tran").

Fig. 11 Expression value display in the Virtuoso Analog Environment.

Parametric analysis

It is very important to evaluate the circuit behaviour with different temperatures, supplyvoltages and technological parameters. Parametric analysis is used in this tutorial to sweepthe vdd_val parameter and the temperature. In the Virtuoso Analog Environment select

Tools Parametric Analysis

Fig. 12 Parametric analysis window.


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In the Parametric analysis window select

Setup Pick Name for Variable sweep 1

and select temp. In the Parametric analysis window assign:

Field Value

Step Control Linear Steps

From -10

To 50

Step Size 10

Range Type From/To

and select

Analysis Start

Fig. 13 Parametric analysis display in the waveform window (with a 1-> 0 zoom in).

Fig. 13 shows how results of parametric analysis with expressions are displayed in thewaveform window: a new graph is displayed with the expression result evolution.

In order to change the power supply value, in the Parametric analysis window select

Setup Pick Name for Variable sweep 1

and select vdd_val. In the Parametric analysis window assign:

Field Value

Step Control Linear Steps

From 2

To 4

Step Size 1

Range Type From/To

and, once again, selectAnalysis Start.


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5. Creating the Layout

Starting the layout tool

Open the schematic view of the inverter1 cell and select

Tools - Design Synthesis - Layout XL

from the menu bar. Selecting this option will first open a small dialog box that will let the usercreate a new layout or open an existing one. We opt for Create New. The next dialog gives usthe possibility to change the properties of the new cellview. Check whether the View Nameisset to layoutand the Toolis set to Virtuoso. After pressing OKthe Virtuoso Layout XL Editorwill start.

Layer Selection Window (LSW)

Also the Layer Selection Window (LSW) is started (Fig.14). EachLSW entry is divided in three categories which are color,abbreviated name and purpose. Color shows the appearance of thelayer in the layout. The abbreviation is the official name of the layerfor Virtuoso, it can appear in messages, etc.

The Layer Selection Window is used to select the active layer (leftmouse-button), to set whether a layer is selectable or not (rightmouse-button) and to set whether a layer is visible or not (middlemouse-button). After the visibility status of a layer has beenchanged press the key to refresh the screen.

Each layer appears in the LSW window with purpose drw fordrawing and pin for pin, you will almost always need drw.

Initialize the layout

To initialize the layout according to the schematic (i/o pins, deviceinstances, ...) select

Design - Generate From Source

in the Virtuoso Layout XL Editor menu bar. Fill out the appearingform to set some properties of the components in the layout: set the

boundary width to 3 m and the boundary height to 13 m.Compare the other fields of the form with Fig 15.

Check the Pin Label Shape = Labelbox and enter the Pin LabelOptionsdialogue window. Set the Layer Nameand Layer Purposeto Same as Pin.

Fig.14 LSW


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Fig.15 Layout generation options.

After hitting OK the Virtuoso Layout XL Editor creates the chosen components in the layoutwindow (Fig. 16).


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Fig.16 Layout automatically generated based on the schematic.

Settings for the Virtuoso Layout XL Editor

Select Options - Display and, in the new opened window, assignX Snap Spacingand YSnap Spacingto 0.025, and Display Levels: From = 0, To = 2.

Useful commands are:

command menu bar command shortcut

save the layout Design - Save

zoom in Window - Zoom - In

fit complete layout in the layout window Window - Fit All

redraw layout window Window - Redraw

create ruler Window - Create Ruler delete all rulers Window - Clear All Rulers

undo last action Edit - Undo

move object Edit - Move

stretch object Edit - Stretch

delete object Edit - Delete

edit object properties Edit - Properties

terminate any command

Very

useful!


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Layout creation - placing the components

A first placement iteration can be obtained by selecting

Edit Place as in Schematic

The replaced cells will look like Fig. 17. At this stage, in more complex cells, the commandsConnectivity show incomplete nets / hide incomplete nets may be of interest.

Fig. 17 Layout after Place as in schematiccommand.

When a pin or MOS transistor is selected in the Layout Window, the corresponding device is

also highlighted in the Schematic Window. This works also when a component is selected inthe Schematic Window.

When the Drain or Source contacts of two similar transistors are connected directly, VirtuosoXL will chain these transistors automatically after shifting the according areas over eachother. Furthermore Virtuoso XL determines the necessity for an additional connection to thisarea.

To rotate a transistoreither select the command Edit - Move, select the transistor you wantto rotate and press the right mouse button or bring up the object properties of the appropriatetransistor and change the entry Rotation (Fig.18).

prBoundary =limits of the cell

layout


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Fig. 18 Transistor properties including Rotation = 90.

While a command is activated its detailed behavior can be customized by pressing the key (e.g. set snap mode).

Very useful is Virtuoso XL's status barjust above the menu bar:

X:and Y:indicate the actual mouse pointer's position.

The letter enclosed by parenthesis indicates whether partial selection mode (P) or fullselection mode (F)is activated. Toggle between these two settings by pressing .

The Select:entry shows how many objects are currently selected.

When moving components, dX:, dY:and Dist:show the difference between startingpoint and end point.

In the Cmd:field one can determine the currently active command.

Also very useful is the mouse function indicatorat the bottom of the Layout Window. Therethe currently assigned functions to the mouse buttons according to the active command areindicated.

Gnd and vdd rectangles

Zoom in the bottom of the prBoundary ().

Select the layer metal 1(MET1) of type drawing (drw), clicking in the corresponding layer in

the LSW (see Fig.14).

Draw a ruler () from coordinates (0, 0) to (0, 1.8).

Starting at coordinates (0, 0), draw a rectangle () of metal 1 with the total width of the

prBoundary (that will be the limit of the cell) and 1.8 m of height (see Fig. 19).


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Fig. 19 Gnd rectangle in metal1.

Copy this metal 1 rectangle to the top of the prBoundary box (for vddusage).

Place the gndpin and label over the metal 1 rectangle in the bottom of the cell. For simulationpurpose it can be placed anywhere. If the cell would be used in an automatic placement androuting process, two rectangles of metal 1 of type pin should be overlapped to the metal 1

drw, at each access of the ground rectangle. Each metal 1 pin rectangle points to an accessto the net and therefore its properties must include the directions from where the access isallowed (Fig.20). Place the vddpin and label over the metal 1 rectangle in the top of the cell.

The placement of the global pins gnd! and vdd! needs some additional setting. Theirproperties have to be additionally edited. After selecting them and depressing the EditInstance Propertiesdialog box opens. Here Connectivityhas to be checked. Terminal Nameis displayed(gnd! or vdd!). Net Expression Property and its Default value has to be defined asgndand gnd!as well as vddand vdd!respectively. If this property is missing then everythingwill run correctly with the only exception of the simulation of the extracted netlist. The LVS willnot be influenced, but the simulator will not be able to connect the power supply to the powerrails of the layout and, therefore, the circuit will not function at all.


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Fig. 20 Assigning access directions to a pin.

Substrate and n-well connection

In order to connect the ground metal 1 rectangle to the substrate a contact can beautomatically generated selecting:

Create Contact

and selecting PD_C. Place the bottom-left corner of the contact at coordinates (0, 0). Thiscontact includes the active area (diff), p+select (pplus), metal 1 (met1), and the contact (cont).It performs a good ohmic contact between metal 1 and the substrate.

In order to connect the n-well to vdd, the n-well included in the pmos transistor must beextended to include the vdd line. Select the layer NTUB of type drawing and draw a rectangle

starting from the top of the pmos n-well and ending 0.9 m above the vdd line. (see Fig. 24).

Similarly to the gnd contact to substrate, select the ND_C and place the top-left corner of thecontact at coordinates (0, 13). This contact includes the active area (diff), n+select (nplus),metal 1 (met1), and the contact (cont). It performs a good ohmic contact between metal 1 andn-well (see Fig. 24).

Placing the transistors

Create a ruler (), starting from the top of the gnd rectangle, with 0.45 m of lenght.

Rotate (see item Layout creation placing the components in this section) and move ()the nmos transistor, centring in the prBoundary box and bringing the metal 1 drain and sourceto the distance pointed by the ruler (see Fig. 21).


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Fig. 21 Gnd rectangle with pin assignment, substrate connection and nmos placement.

Create a ruler (), starting from the top of the nplus of the nmos transistor, with 1.2 m oflenght (see Fig. 22).

Rotate and move () the pmos transistor, centring in the prBoundary box and bringing thenwell (ntub see Fig. 22) to the distance pointed by the ruler.


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Fig. 22 pmos placement.

Routing between the components

The next step in layout creation is to connect the components electrically according to theschematic. Connections can be drawn in three different ways:

type of connection menu bar command shortcut

rectangle Create - Rectangle

polygon Create - Polygon

path Create - Path

Before activating a command select the desired layer in the Layer Selection Window (LSW)!

When the path command is activated and the path has been started at an identifiableconnection Virtuoso XL highlights the geometries and terminals of other components whichshould be connected. To change the layer while drawing a path use the path options invokedby pressing . There the Change To Layer option can be modified and Virtuoso XL

automatically generates the contacts from one layer to another.

Inter-layer contacts can be created explicitly through Create - Contact (shortcut ). Toestablish a connection between the metal layer 2 and the poly layer 1, two of these contacts


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have to be placed: MET2 -> MET1 (VIA1_C) and MET1 -> POLY1 (P1_C). They can beplaced right over each other.

With the command Connectivity - Show Incomplete Nets one can highligt signal nets thathaven't been routed correctly and completely. To end the highlighting of incomplete netsselect Connectivity - Hide Incomplete Netsfrom the menu bar.

Fig. 23 Gates and drains interconnection.

Fig. 23 shows the gates and drains interconnections and the OUT pin placement over

the corresponding metal 1 connection. Fig. 23 also shows a poly-metal 1 contact thatallows connectivity in metal 1 to the input of the inverter (Create Contact P1_C).

The sources of the transistors must be connected to vdd!and gnd! (see Fig. 24). The IN pinand label must be moved to the top of the metal 1 connected to the inverter input (overlappingthe P1_C contact, not displayed in Fig. 23 for clarity).


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Fig. 24 Connection of the pmos source, n-well contact and vdd! pin assignment.

Layout creation - miscellaneous

While placing components and routing, periodically start the Design-Rule-Check (DRC) inorder to identify any violations of the design rules of the current process technology (min.spacing between geometries, min. width of geometries, ...). When implementing a standardcell it is also very important to consider the distances of geometries on the various layers to

geometries in adjacent placed cells. These errors can't be found by the DRC of the single cell. The DRC will be explained in detail in the next section.

If the schematic of the cell is changed during or after the layout of the cell has been designed,the following commands could be of interest:

command menu bar command

change the nets at the terminalsof an instance

Connectivity - Propagate Nets

update of components and netsConnectivity - Update -Components And Nets


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After hitting OK the DRC is carried out and any violations are highlighted in the layout by

flashing markers and the errors are reported in the CIW (see Fig. 26).

Fig. 26 CIW DRC errors.

Processing DRC errors

To get a complete list of all errors select

HIT-Kit utilities - Find DRC Markers

Only the errors listed in Fig. 27 should be identified by the DRC of the inverter.

Fig. 27 Expected errors in the inverter.

They could easily be avoided when we set the switch no_coveragein the DRC options form.These errors (Minimum ... density ...) only make sense in the scope of the whole layout of the

chip where they must be treated as severe errors. Generally, if you neglect a DRC error youshould really be able to explain why this error can be ignored.


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When we select an error in the list, Virtuoso XL focuses to the area in the layout where theerror occurs. If there is more than one error with the same name, we can switch betweenthese errors with the Error Numberslider. TheZoom Factorapplied by Virtuoso XL to focus toan error can also be set with a slider.

To delete all markers press the button Delete all Marker in the DRC Error Search form or

select Verify - Markers - Delete Allfrom the Virtuoso XL menu bar.

Some c35b3 rules are:

Minimal: Width Spacing

NTUB 3 3

DIFF 0,3 0,6

POLY1 0,35 0,45

PPLUS/NPLUS 1,6 1,6

POLY2 0,65 0,5

CONT 1 1,2MET1 0,5 0,45*

VIA 1,2 1,6

MET2 0,6 0,5**

PAD 15 25

* If the MET1 is wide (width>10m) then 0,8

** If the MET2 is wide (width >10m) then 0,8

Minimum spacing between different layers:DIFF PPLUS 0,35

CONT in MET1 POLY1 0,8CONT in POLY2 POLY1 1,6

POLY1 VIA 1

POLY2 VIA 1,2

CONT VIA1,2

POLY1 POLY2 1,4

POLY1 DIFF 0,4

POLY2 DIFF 1,2

Overhang in transistors:

POLY1 over DIFF 0,6DIFF over POLY1 1,4

Spacing inside the surrounding layer (overlap)

VIA in MET1 0,2

VIA in MET2 0,3

NDIFF in NTUB 0,2

DIFF in NPLUS 0,45

DIFF in PPLUS 0,45

Spacing

Width


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7. Extraction

Circuit extraction is performed after the mask layout design of the cell is completed. It createsa detailed netlist (extracted netlist) of the cell which can be used for example in the Layout-versus-Schematic check or by a circuit simulator. The circuit extractor is capable of identifying

the individual transistors and their interconnections as well as the parasitic resistances andcapacitances that are inevitably present in the cell. Thus, the extracted netlist provides a veryaccurate model of the cell.

Starting extraction

To start the extraction select

Verify - Extract

from the menu bar of the Virtuoso Layout XL Editor where the layout intended for extraction isopened. In the appearing form, the options for the extractor can be given. Set the following

options:

option set to comment

Extract Method flatany instances of other cells found in the layout shouldalso be extracted (layout of this cells must also beavailable!)

Switch Names capallto set additional options for the extraction process e.g.capalltells the extractor to additionally extract parasiticcapacitances

ViewNames Extracted

extracted

Rules File ../divaEXT.rul extraction rules file name

Rules Library TECH_C35B3 Disable the library that contains the extraction rules file

After hitting OK the extraction is carried out and a new view called extractedis generated forthe cell (Library Manager).

8. Layout-versus-Schematic Check (LVS Check)

After the mask layout design of the cell is completed, it should be checked against theschematic of the cell created earlier. The Layout-versus-Schematic check (LVS check) will

compare the circuit given by the schematic with that one extracted from the mask layout andtries to prove that both networks are equivalent.

The LVS step provides an additional level of confidence for the integrity of the design andensures that the mask layout is a correct realization of the intended circuit. Note that the LVScheck only guarantees topological match: A successful LVS check will not guarantee that themask layout of the cell will actually satisfy the performance requirements.

Any errors that may show up during the LVS check (such as unintended connections betweentransistors, missing connections/devices, ...) should be corrected in the mask layout. Notethat the extraction step must be repeated every time the layout of the cell is modified.


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Starting LVS checking

To start the LVS check select

Verify - LVS

from the menu bar of the Virtuoso Layout Editor where the extracted netlist of the cellintended for LVS checking is opened. If a form called "LVS Form Contents Different" appears,select Use: Form Contentsand press OK. In the next form, the options for the LVS check canbe set: It can be specified which cell views should be compared and where to find the LVSrules file. Fill out the form as Fig. 28.

Fig. 28 LVS options.

After clicking Runthe LVS check is started.

Analyzing LVS results

When the LVS check is finished, a window appears that indicates whether the check wassuccessful or not. To view the LVS check results in detail, press the Outputbutton in the LVSWindow. The file si.out in the given working directory contains the LVS check results. For

further information (LVS run log file, schematic/extracted netlist, ...) press the Infobutton.


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Fig. 29 LVS result.

Parasitics probing

The different nets in the extracted netlist can be probed to get a summary of the parasitics(resistances, capacitances) present on the nets. Since we could only extract parasiticcapacitances during the extraction of the netlist, no values for parasitic resistances areindicated.

To set a parasitics probe press the button Parasitic Probe in the LVS Window. In the nextwindow press the button Whole Netand select a net in the layout window where the extractedview is shown. It is also possible to get a summary of parasitics between nets. Therefore, use

the button Net To Netbefore selecting two nets in the extracted view.


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9. Post-Layout Simulation

It is now easy to simulate the layout (more exactly the extracted netlist) with the VirtuosoAnalog Circuit Design Environment. Close the layout editor window and open the test benchfor the simulation of the cell schematic (Section 4. Schematic Simulation). The same test

bench can be used for the extracted simulation. Open the test bench schematic and selectfrom the Composer window of the simulation schematic

Tools - Analog Environment

Configure the simulation conditions as described in Section 4 and choose:

Setup - Environment

and set Switch View Listto spectreS cmos_sch extracted schematic. As a result of this, if thesimulator now creates the netlist of the simulated circuit it uses the extracted netlist of the cellrather than the schematic.

10. GDSII Export of the Cell Layout

To export the mask layout of the cell in GDSII format select the following command in theCIW:

File - Export - Stream.

Fill out the appearing form like depicted below:


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Fig. 30 GDSII export.

Note that the run directory gds2Exportmust be created in the current directory cds_tutorialbefore the export can be started. The log file of the export process (PIPO.LOG), which

explains warnings and errors during export in detail, and the GDS2-file itself will be stored inthe run directory.

The Layer Map Table, which can be stated by pressing the button User-Defined Data, shouldbe set to

/soft/ams/artist/HK_C35/TECH_C35B3/strmInOut.layertable

There are two warnings given for the export process concerning the layers (changedLayer220 tool0) and (prBoundary 235 drawing). These warnings can be safely ignored.

Date post:	02-Jun-2018
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