TUTORIAL - Iterative Detection & Turbo-Like Codes-K. Chugg

8/13/2019 TUTORIAL - Iterative Detection & Turbo-Like Codes-K. Chugg

http://slidepdf.com/reader/full/tutorial-iterative-detection-turbo-like-codes-k-chugg 1/52

Iterative Detection & Topics in Turbo-Like Codes

Wireless Communications Seminar SeriesStanford University

March, 2002

Keith M. Chugg

Electrical Engineering Department

University of Southern [email protected]

TrellisWare Technologies, Inc.

[email protected]



Iterative Detection & TLCs c K. M. Chugg – March 2002

Acknowledgments

• Financial Support:

– National Science Foundation: NCR-9616663, CCR-9726391,

CCR-0082987.– TrellisWare...

• Contributors:

– Prof. Peter Beerel, USC– Dr. Jun Heo, USC– Dr. Phunsak Thiennviboon, USC/TrellisWare– Dr. Xiaopeng Chen, Marvell (pictures!)

1




Outline/Summary/Conclusions

• Iterative Detection: There is a standard set of rules iterativedetection (message passing)

– This is a very general and powerful technique for statistical inference

• Turbo-Like Codes (TLCs): TLCs are excellent design choices fornearly all operational scenarios in practice

– TLCs perform near the theoretical limits over a wide range of code rates, blocksizes, and target BERs/BLERs.

• TLC Codecs Can be Built Fast:– 100’s of megabits/sec in FPGA, 10’s of Gigabits/sec in standard CMOS ASIC.

• TLC Designs Exist with Very Low Decoding Complexity:– Based on single-parity checks

• A Lot of Fertile Work for Architecture/ImplementationTypes

– We’re hair-splitting over 0.2 dB of E b/N 0 without hardware

2




Progress

1. Iterative Detection: There is a standard set of rules iterativedetection (message passing)

2. Turbo-Like Codes (TLCs): TLCs are excellent design choices fornearly all operational scenarios in practice

3. TLC Codecs Can be Built Fast

4. TLC Designs Exist with Very Low Decoding Complexity

3




Motivation: What’s “optimal”?

modulation

noise

like-signal interferencedistortion (ltering, fading etc.)

demodulation

estimationchannel

demodulationdecoderdeinterleaving

andunformatting mitigation

channelbit decisions

(b)

estimationchannel

demodulation

channelcoding and formatting

interleaving a k

source coderbits from(a)

exhaustive

transmitter modelaccurate channel and

bit decisionslikelihood

search(c)

decoder mitigationchannel

bit decisions deinterleavingunformattinginterleavingformatting

possibly a singleprocessor

(d)

channel

4




General System

C

GF

a m xnD HEB

M

• The block diagram of a generic concatenated network.

• Decomposition is an arbitrary design choice.

5




Iterative Detection

D -s

F -s G -s

E -s

C -s

H -s (from channel

soft demodulator)

SI[x n ]

B -s

(a-prioriinformation)

C

a m

SI[a m ]

• The iterative detector implied by the concatenated system on the

previous slide.

6




Marginal Soft-Inverse of a System

• Inputs: Set of marginal soft-inputs on the system inputs & outputs– Think of these as probability mass functions on the digital variables – Soft information before exploiting local system structure

• Outputs: Set of marginal soft-outs on system inputs and outputs– Soft information after exploiting local system structure

• Local/Isolated Optimality: Dened relative to a particular choiceof combining and marginalization operators

– MAP symbol detection vs. MAP sequence detection (when it’s optimal)– “Probability domain” vs. “Metric (neg-log-probability) Domain”

• Intuition: Update soft-information assuming memoryless inputs andchannels using only the (sub)system structure

• Signicance: this is the fundamental concept in iterativemessage-passing algorithms!

– Same processing is done in other interpretations (Belief Propogation, factor graphs, etc. – see the great ref. [Wi96]).

7





M M − s

......

......

a 0

a 1

x 0

x 1

SI[a 0 ]

SI[a 1 ]

SO[x 0 ]

SO[x 1 ]

SO[a 0 ]

SO[a 1 ] SI[x 1 ]

SI[x 0 ]

M M − sa m xn

x N − 1

SO[a m ] SI[x n ]

SO[x n ]SI[a m ]

SO[a M − 1 ]SI[a M − 1 ]

SI[x N − 1 ]SO[x N − 1 ]

(a)

(b)

a M − 1

• The marginal soft inverse of a system in the (a) implicit and (b)explicit index block diagram conventions.

8





• Computational Problem: (semi-ring C&M):

S[a , x(a)] = S[x(a)] c S[a] (1)

= (N −1

cn=0

SI[xn(a)] ) c (M −1

cm=0

SI[am] ) (2)

SO[am] = ( ma :am S[a , x(a)] ) c−1

SI[am] (3)

SO[xn] = ( ma :xn

S[a , x(a)] ) c−1SI[xn] (4)

• This is a sort of “likelihood updater”

• Intrinsic (e.g., MSM - minimum sequence metric) vs. extrinsic (e.g.,MO).

9




Summary of Combining/Marginalization

Marg. Combining Reliability Measure Associated Likelihoodsum product APP average likelihood (AL)min∗ sum neg-log-APP (M∗SM) neg-log AL

max product generalized APP generalized likelihood (GL)min sum MSM neg-log GL

min∗(x, y) ∆= −ln e−x + e−y = min( x, y) −ln(1 + e−|x−y|)

•Signicance:– General problem: generalized shortest path

problem [CoLeRi90, ChAnCh01] or marginalize a productfunction [AjMc00].

– General solution:

∗Derive an algorithm based on one combining/marginalizationsemi-ring, you have all others – e.g., Generalized DistributiveLaw (GDL) [AjMc00].

∗

Pick the easiest to work with (intuition vs. mathematics)

10




Commonly Used Systems and their Soft-Inverses

SO[a k (0)]SI[a k (0)]

SI[a k (1)]SO[a k (1)]

SO[a k (I − 1)]SI[a k (I − 1)]

SO[x k (0)]SI[x k (1)]

SI[x k (J − 1)]SO[x k (J − 1)]

SO[x k (1)]

SI[x k (0)]

SI[x k (0)]SO[x k (0)]SI[x k (1)]SO[x k (1)]

SO[x k (J − 1)]SI[x k (J − 1)]

FSMa k x k

Finite State Machine

a k

I

x k (0)

x k (1)

x k (J − 1)

...

a k

x k (0)

x k (1)...x k (J − 1)

x k

Serial-to-Parallel

Parallel-to-Serial

...

...

a m (0)

a m (1)

a m (I − 1)

x n

SO[a m (0)]SI[a m (0)]SO[a m (1)]SI[a m (1)]

SO[a m (I − 1)]SI[a m (I − 1)]

x n

am

(0)a m (1)

a m (I − 1)

SI[am

(0)]SO[a m (0)]SI[a m (1)]SO[a m (1)]

SI[a m (I − 1)]SO[a m (I − 1)]

a k (0)

a k (1)

a k (I − 1)

...

System

Memoryless Mapper

Broadcaster

Interleaver

SISOSO[a k ]

SI[a k ]

SI[x k ]

SO[x k ]

SO[a k ]

SI[a k ]

SI[x k ]

SO[x k ]II− 1

SO[a k ]

SI[a k ]

......

...

...

...

SI[x n ]

SO[x n ]

SI[x n ]

SO[x n ]

Marginal Soft Inverse

[BeDiMoPo98] Nice, underappreciated paper!!

11




Forward Backward Algorithm

0

1

2

3

0

1

2

3

s 0 sK

1

2

3

1

2

3

0 0

s k +1s k

Mk [t k ]MSMK − 1

k +1 [s k +1 ]MSMk − 10 [s k ]

• FBA is an algorithm for computing the soft-inverse of an FSM

• The FBA consists of three steps:

– Forward recursion– Backward recursion– “Completion” operation

MSMK −10 [uk] = min

tk:ukMSMk−1

0 [sk] + Mk[tk] + MSMK −1k+1 [sk+1 ] (5)

12



4

5

47

6

4

11

3

12

3

6

10

8

13

10

10

F k − 1[s k ] F k [s k +1 ]M k [t k ]

Forward Recursion (ACS)

4

5

47

6

4

11

3

5

6

13

9

1

6

22

9

M k [t k ]

Backward Recursion (ACS)

Bk +1 [sk +1 ]B k [s k ]

4

5

47

6

4

11

3

12

3

6

10

F k − 1[sk ] M k [t k ]

Completion

Bk +1 [sk +1 ]

1

6

22

9

MSMK − 10 [a k = − 1] = min {(12 + 4 + 22) , (3 + 7 + 22) , (6 + 4 + 9) , (10 + 6 + 9) } = 19

MSMK − 10 [a k = +1] = min {(12 +4 + 1) , (3 + 5 + 1) , (6 + 11 + 6) , (10 + 3 + 6) } = 9


FBA Toy Example

13



1+32+3

3+1

6+1

5+1

3+1

8+3

0+3

12

3

6

10

F k − 1[s k ]

Completion (extrinsic output)

B k +1 [sk +1 ]

1

6

22

9

MI[a k = +1] = 3

MI[a k = − 1] = 1

M k [t k ] = MI[ xk ( tk )] + MI[ a k (tk )]

MO[a k = +1] = 9 − 3 = 6 = (3 + 2 + 1)

MO[a k = − 1] = 19 − 1 = 18 = (6 + 3 + 9)


FBA Toy Example

• Extrinsic information does not contain the current soft-in information

• Note that best hard decision is ˆak = +1 - why?

14




Progress


2. Turbo-Like Codes (TLCs): TLCs are excellent design choices fornearly all operational scenarios in practice.



15




Turbo-Like Codes

• Examples:– Parallel Concatenated Convolutional Codes (PCCCs) or “turbo

codes” [BeGlTh93, BeGl96, BeMo96, BeMo96b]

– Serially Concatenated Convolutional Codes (SCCCs) [BeDiMoPo98b].– Low-Density Parity Check (LDPC or Gallager Codes [Ga62, Ga63, Ma97]– (Parallel Concatenated) Zig-Zag Codes [PiHuPh99].– (Generalized) Repeat-Accumulate Codes [JiKhMc00].

– Variations on the theme: turbo-product/block codes, Hybrid-CCCs, etc.

• Common Elements:– Modeled as a concatenated network of codes or, equivalently, a graph with cycles.– Decoded suboptimally, yet effectively, using the standard iterative

message-passing rules.– In SNR region of interest, performance is not dominated by minimum distance,

but rather by the “thinness” of the neighborhood.

16




TLC Myths and Realities

• Myth (?): TLCs work well only when the block size islarge, so they are not applicable to low-latencyapplications.– Reality: TLCs are favorable to more traditional designs even for

small block sizes (e.g., as low as 32 input bits or smaller).

∗ 20 msec of 10 kpbs speech is 200 bits; higher-speed sources yield larger blocks

•Myth (?): TLCs hit an “error-oor” and therefore are notsuited for applications requiring very high delity.– Reality: “Floor(s)” are inection points where the dominant error

distance changes.

∗

Careful interleaver design can knock PCCC oors down 2-4 decades in

BER [CrGu01].

∗ SCCCs and other variations much less susceptible.

∗ Carefully designed TLC will still have a minimum distance larger than atraditional convolutional code – i.e., “oor” performance is better thantraditional designs.

17




TLC Myths and Realities

• Myth (?): Decoding speeds or TLCs are limited to about100-200 Mbps.

– Reality: Demonstrations in a single FPGA nearing those rates.Much higher speeds in ASIC are attainable.

• Myth (?): TLC decoding is computationally intensive.

– Reality: 10-20 iterations using constituent codes of 2, 4, or 8 statesis usually comparable to Viterbi decoding of the traditionalconvolutional codes (64-256 states).

• Myth (?): TLC decoders are memory intensive.

– Reality: TLC decoders are memory intensive.∗ BUT, most of the gains are achieved with block sizes below 4K.

18




Measuring “Good” Performance (Block Error Rate)

• Nice Reference: [DoDiPo98]

• Shannon Capacity:

– Limit for error-free performance– Limit as block size (latency) tends toward innity– Simple to include binary modulation constraint

• Sphere Packing Lower Bound:– Lower Bound for any (k, n ) code (i.e. , nite block size!)– Tends toward Shannon limit as block size→ ∞– Not so simple to include binary modulation constraint (possible).

19




Measuring “Good” Performance (Block Error Rate)

• Random Coding Upper Bound:

– Upperbound on the BLER averaged over all (k, n ) codes (i.e. , nite

block size!)– Tends toward Shannon limit as block size→ ∞– Simple to include binary modulation constraint (possible).– Approaches SPB quickly as k

→ ∞(e.g., k

∼100 & moderate

rates)– Excellent guideline to judge achievable practical code

performance!

P word ≤e−k(E b/N 0) min0≤ρ≤1

2ρr +1 ∞0

e−y2

2

√ 2πcosh1+ ρ y 2r (E b/N 0)

1 + ρdy

n

• k input block size, n output block size, r = k/n rate.

20



0

0.2

0.4

0.6

0.8

1

-2 0 2 4 6 8

r a t e

EbNo (dB) required for (dB) BLER=1e-4

4567891014


Comparison of RCB and Capacity

• Diminishing returns with increasing block size (log2(k) shown on plot).

21



10 -6

10 -5

10 -4

10 -3

10 -2

10 -1

10 0

0 1 2 3 4 5

128 state (r=1/2) CCk=64 SCCC (4-state/4-state)k=128 SCCC (4-state/4-state)

B E R

Eb/No (dB)


Example: 4-state SCCC vs. Convolutional Codes

• Increasing the block size to k = 200, the TLC beats a 256-state CC by about 0.8 dB.

22



0

0.2

0.4

0.6

0.8

1

-1 0 1 2 3 4 5 6 7

c o

d e r a

t e

Required Eb/No (dB) for BLER = 1e-2

k = 4096 k = 128

Random Coding Bound

< 1 dB

< 1 dB


Example: A Representative TLC compared to the RCB

• Target BLER is 10−2.

23



0

0.2

0.4

0.6

0.8

1

-2 0 2 4 6 8

c o

d e r a

t e

Required Eb/No (dB) for BLER = 1e-4

k = 4096

k = 128

Random Coding Bound

< 1 dB

< 1 dB


Example: A Representative TLC compared to the RCB

• Target BLER is 10−4.

• Very best codes are within 0.5 dB for r = 1/ 2, k = 1024

−4096.

24



10-5

10 -4

10 -3

10 -2

10 -1

10 0

0 1 2 3 4 5 6

Random Coding BoundMLSD (optimal)min-sum Iterative

B L E R

EbNo(dB)

k= 24


How Well Does the Iterative Decoding Approach Work?

• ML decoder implemented using a suitably modied version of the branch-and-bound

algorithm in [GaChPiScBe01]. (Will write a small paper sometime...).25




How Well Does the Iterative Decoding Approach Work?

10-5

10-4

10-3

10-2

10-1

1.6 1.8 2 2.2 2.

std IDsummaxsequencereliability

B E R

Eb/No

CID

• Constrained Iterative Decoder is based on running multiple decoders with constraintson some variables to cut some cycles [HeCh01].

26




Progress





27




Fixed-Interval-FBA-SISO

· · ·

· · ·

· · ·

completion

(a)

(b)

s 0

s 0

s K

s K

Two different schedules for executing the FI-SISO via the forward-backwardalgorithm: (a) the serial forward backward schedule and (b) the parallel

forward and backward recursions.

• Computes exact soft-inverse!

• Too much memory for the state metrics...

28




Min-Lag/Max-Lag SISO

• The min-lag/max-lag architecture with parallel backward recursion is

nice for hardware [Vi98, MaPiRoZa99]

• Based on computation of MO[uk] = MSMk+ d0 [uk]−MI[uk], with

Dmin ≤d ≤Dmax ensured.

•Can be parallelized with little extra hardware.

• Trades computation for memory

• Good approximation of the soft-inverse (i.e. , like nite trace-backdepth in the Viterbi Algorithm).

29

K M Ch M h 2002



F

B1B1

completion warm-up

B2

F

warm-upcompletion

B1

warm-up

F F

B1

completion

B2 B2

warm-up

D


Min-Lag/Max-Lag SISO

•Two backwards ACS processors, one forward, and completion circuits

• Produces one set of soft-outputs per “ACS clock cycle”

30

It ti D t ti & TLC K M Chugg March 2002



SISO I/deI SISO I/deI SISO

Block 1,iter=10Block 10,

iter=1

Pipelined over iterations

TLCDecoder

...

TLCDecoder

TLCDecoder

S/P P/S

Parallel Decoders


Standard Speed-Up Approaches

• Main problem (rough estimates):

– 8-state min-lag/max-lag SISO∼30K transistors– 2K soft-info memory

∼

150K transistors (w/o address forinterleaver)

• Not the best area/speed-up possible =⇒ build a faster (bigger) SISO

31






Iterative Detection & TLCs c K. M. Chugg March 2002

Tree-Structured SISO

• Tree-Structured SISO [BeCh01] (patent pending).s k

C[s k , s m ]s m

C-fusion

s ls k

C[s k , s l ] C[s l , s m ]s m

operation

The C-fusion operator.

• These are multi-step transition metrics: C[sk, sm] ∆= MSMm−1k [sk, sm]

• Marginalize out the middle state:

C[sk0, sk1] = C[sk0, sm]

⊗

C C[sm , sk1] ∆= min

sm[C[sk0, sm] + C[sm , sk1]].

(6)

33




Iterative Detection & TLCs c gg


• Computing the forward (backward) state metrics is a prex (suffix)computation problem:

C[s0, sk] = C[s0, s1]⊗C C[s1, s2]⊗

C · · ·C[sk−1, sk] (7)C[sk, sK ] = C[sk, sk+1 ]⊗C · · ·C[sK −2, sK −1]⊗C C[sK −1, sK ] (8)

MSMk−10 [sk] = min

s0C[s0, sk] (9)

MSMK −1

k [sk] = min

sK C[sk, sK ] (10)

• Highly-parallel tree-structured algorithms exist for thisproblem [CoLeRi90]

– Usually, this is used for a tree-adder in VLSI– Latency is logarithmic in block size as opposed to linear.

34





m

C-fusion processor

C[s 0 , s 1 ]

C[s 1 , s 2 ]

C[s 2 , s 3 ]

C[s 3 , s 4 ]

C[s 4 , s 5 ]

C[s 5 , s 6 ]

C[s 6 , s 7 ]

C[s 7 , s 8 ]

C[s 0 , s 8 ]

C[s 0 , s 1 ]

C[s 0 , s 2 ]

C[s 1 , s 2 ]

C[s 2 , s 3 ]

C[s 2 , s 4 ]

C[s 3 , s 4 ]

C[s 4 , s 5 ]

C[s 4 , s 6 ]

C[s 5 , s 6 ]

C[s 6 , s 7 ]

C[s 6 , s 8 ]

C[s 7 , s 8 ]

C[s 0 , s 1 ]

C[s 0 , s 2 ]

C[s 0 , s 3 ]

C[s 0 , s 4 ]

C[s 1 , s 4 ]

C[s 2 , s 4 ]

C[s 3 , s 4 ]

C[s 4 , s 5 ]

C[s 4 , s 6 ]

C[s 4 , s 7 ]

C[s 4 , s 8 ]

C[s 5 , s 8 ]

C[s 6 , s 8 ]

C[s 7 , s 8 ]

C[s 0 , s 1 ]

C[s 0 , s 2 ]

C[s 0 , s 3 ]

C[s 0 , s 4 ]

C[s 0 , s 5 ]

C[s 0 , s 6 ]

C[s 0 , s 7 ]

C[s 1 , s 8 ]

C[s 2 , s 8 ]

C[s 3 , s 8 ]

C[s 4 , s 8 ]

C[s 5 , s 8 ]

C[s 6 , s 8 ]

C[s 7 , s 8 ]

F[s 1 ]

F[s 2 ]

F[s 3 ]

F[s 4 ]

F[s 5 ]

F[s 6 ]

F[s 7 ]

B[s 2 ]

B[s 3 ]

B[s 4 ]

B[s 5 ]

B[s 6 ]

B[s 7 ]

B[s 1 ]

A tree-SISO shown for K = 8. Dashed lines represent only forward orbackward information while solid lines represent bi-directional information.

• Computes the same numbers as the FBA! Exact soft-inverse.

35





C-fusion processor

B-C-fusion processor

F-C-fusion processor

F[s 1 ] F[s 1 ]

F[s 2 ]

C[s 1 , s 2 ]

C[s 2 , s 3 ]

C[s 2 , s 4 ]

C[s 3 , s 4 ]

C[s 4 , s 5 ]

C[s 4 , s 6 ]

C[s 5 , s 6 ]

C[s 6 , s 7 ]

B[s 6 ]

B[s 7 ]

C[s 1 , s 2 ]

C[s 2 , s 3 ]

C[s 3 , s 4 ]

C[s 4 , s 5 ]

C[s 5 , s 6 ]

C[s 6 , s 7 ]

B[s 7 ]

F[s 1 ]

F[s 2 ]

F[s 3 ]

F[s 4 ]

C[s 1 , s 4 ]

C[s 2 , s 4 ]

C[s 3 , s 4 ]

C[s 4 , s 5 ]

C[s 4 , s 6 ]

C[s 4 , s 7 ]

B[s 4 ]

B[s 5 ]

B[s 6 ]

B[s 7 ]

F[ s 1 ]

F[ s 2 ]

F[ s 3 ]

F[ s 4 ]

F[ s 5 ]

F[ s 6 ]

F[ s 7 ]

B[s 1 ]

B[s 2 ]

B[s 3 ]

B[s 4 ]

B[s 5 ]

B[s 6 ]

B[s 7 ]

The tree-SISO with simplication in the edge computations at the earliestpossible stage. Dashed lines represent only forward or backward information

while solid lines represent bi-directional information

• Specically:MSMk−1

0 [sk] = minsm

[MSMm0 [sm] + C[sm , sk]] (11)

MSMK −1k [sk] = min

smC[sk, sm] + MSMK −1

m [sm] (12)

36




Tree-Structured SISO Summary

• Can be viewed as a tree-structured set of constraints to enforce theFSM structure with standard message-passing on thistree-model [ThCh00, ChAnCh01]

• Can be used in place of FBA on a trellis for any application (e.g.,parity-check trellis decoding)

• Various tree-adder structures are applicable (e.g., [CoLeRi90])

• Can be used as a basis for very fast TLC decoder design

• Exponential speed-up with linear area gain

– Doesn’t scale well with number of trellis states

• Generalization of the ACS-bottleneck-breaking Viterbiarchitectures [FeMe89, Bl93].

37




Progress





38




Codes Based on Single Parity Checks

• Low-Density Parity Check Codes

– Encoding is awkward (order n2 operation)– Linear-Time Encodable (constrained) LDPC

Codes [PiHuPh99b, NaAlNa01]

•(Parallel Concatenated) Zig-Zag Codes [PiHuPh99]

• (Generalized) Repeat-Accumulate Codes [JiKhMc00]

• These codes receive a lot of attention in academia

– All variables are binary (i.e. , states too), which allows application of density evolution for iterative decoding threshold E b/N 0

– Provably good properties– Low computational complexity...

39




Class of TLCs based on Recursive Single Parity Checks

• PCZZ, Generalized-RA, and LTE-LDPCs are all essentially the same

code• Performance is slightly worse than traditional PCCC/SCCC

• Irregular designs yield a 0.5-0.7 dB improvement and are competitivewith traditional TLCs

• Current Issue: Are these codes good for practical applications?

– Usually require more iterations than traditional TLCs, so thecomplexity/performance trade is roughly a wash (?)

∗10 iterations ×8 states ×2 codes∼20 iterations ×2 states ×4codes (very rough)– Can simplied recursions be exploited in digital circuitry?– Moderate/small interleaver performance

40




1/ (1 + D )puncture(1 of J)

1/ (1 + D )paritycomputation

S/P

(1 to J)

0 0

11

s iJ = pi− 1s ( i+1) J = pieven parity

J-tuple inputs

odd parityJ-tuple inputs

ZZ/RSPC

ZZ/RSPC

Basic Code: Recursive Single Parity Check (Zig-Zag)

41




RSPC Has Very Simple FBA Computations

• Exploits the fact that all soft information can be represented by asingle number (i.e. , log-likelihood ratio...).

• Based on simple relation:min(x, y) −min(0, x + y) = sign(x)sign(y)min{|x|, |y|}

• A min-sum FBA SISO requires only these min/sign calculations, one

add per forward (backward) ACS, and a “second-min” calculation forthe completion [PiHuPh99].

• How to do min/sign computations and adds easily in hardware?

42




RSPCI

systematic

parity

(Generalized) RepeatAcculate Code

systematic

RSPC parity(0)

(Parallel Concatenated)Zig-Zag Code

RSPCI1parity(1)

RSPCI2parity(2)

RSPCI3 parity(3)

Codes Based on RSPCs

43





• LTE-LDPC Parity Check Matrix Constrained Structure:

H =

1 0 0

· · · 0

∗ · · · ∗1 1 0 0 ∗ · · · ∗0 1 1 0 ∗ · · · ∗0 0 1 0 ∗ · · · ∗... .. . 0 ∗ · · · ∗0 0 0 1 ∗ · · · ∗• Exactly the same code as the Generalized-RA

44




...

...

Permutation

Input bits (systematic)

Parity CheckSubsytem

Parity Bits


• PCZZs are obtained by permutation constraint and several “cuts” of the parity recursion trellis.

• Irregular designs: vary the repetition factor and the J parameter of the RSPC ( i.e. , the nodedegrees) while keeping the averages xed.

45




(Regular) PC-ZZ vs. 8-state PCCC (3GPPP)

• PCCC is at 10 iterations. Roughly the same complexity as PC-ZZ with 20 iterations if min-sgntype simplications are not exploited [PiHuPh99].

46




(Irregular) Repeat Accumulate vs. 8-state PCCC (3GPPP)

• PCCC is at 10 iterations ( k = 1024).

• IRA code has irregularity in the variable node only [JiKhMc00].

47




Summary/Conclusions

• Iterative Detection: There is a standard set of rules iterativedetection (message passing)

•Turbo-Like Codes (TLCs): TLCs are excellent design choices fornearly all operational scenarios in practice.

• TLC Codecs Can be Built Fast

• TLC Designs Exist with Very Low Decoding Complexity

• Likely that best code for the job is a TLC - which TLC islikely determined by implementation trades...

48



*




References

[AjMc00] S. M. Aji and R. J. McEliece. The generalized distributive law. IEEE Trans. Information Theory , 46(2):325–343,

March 2000.

[BeCh01] P. A. Beerel and K. M. Chugg. An low latency SISO with application to broadband turbo decoding. IEEE J. Select. Areas Commun. , 2001.

[BeDiMoPo98b] S. Benedetto, D. Divsalar, G. Montorsi, and F. Pollara. Serial concatenation of interleaved codes: performanceanalysis, design, and iterative decoding. IEEE Trans. Information Theory , 44(3):909–926, May 1998.

[BeDiMoPo98] S. Benedetto, D. Divsalar, G. Montorsi, and F. Pollara. Soft-input soft-output modules for the construction anddistributed iterative decoding of code networks. European Trans. Telecommun. , 9(2):155–172, March/April 1998.

[BeMo96] S. Benedetto and G. Montorsi. Design of parallel concatenated convolutional codes. IEEE Trans. Commununication , 44:591–600, May 1996.

[BeMo96b] S. Benedetto and G. Montorsi. Unveiling turbo codes: some results on parallel concatenated coding schemes.IEEE Trans. Information Theory , 42(2):408–428, March 1996.

[BeGl96] C. Berrou and A. Glavieux. Near optimum error correcting coding and decoding: turbo-codes. IEEE Trans. Commununication , 44(10):1261–1271, October 1996.

[BeGlTh93] C. Berrou, A. Glavieux, and P. Thitmajshima. Near shannon limit error-correcting coding and decoding:turbo-codes. In Proc. International Conf. Communications , pages 1064–1070, Geneva, Switzerland, May 1993.

[Bl93] P. J. Black. Algorithms and Architecturees for High-Speed Viterbi Decoding . PhD thesis, Stanford University, PaloAlto, CA, 1993.

[ChAnCh01] K. M. Chugg, A. Anastasopoulos, and X. Chen. Iterative Detection: Adaptivity, Complexity Reduction, and Applications . Kluwer Academic Publishers, 2001.

[CoLeRi90] T. H. Cormen, C. E. Leiserson, and R. L. Rivest. Introduction to Algorithms . MIT Press, Cambridge, Mass., 1990.

[CrGu01] S. Crozier and P. Guinand. High-performance low-memory interleaver banks for turbo-codes. In Proc. Vehicular Tech. Conf. , pages 2394–2398, Atlantic City, NJ, oct. 2001.

[DoDiPo98] S. Dolinar, D. Divsalar, and F. Pollara. Code performance as a function of block size. Technical report, JPL-TDA,May 1998. 42–133.

50




[FeMe89] G. Fettweis and H. Meyr. Parallel Viterbi algorithm implementation: Breaking the ACS-bottleneck. IEEE Trans. Commununication , 37:785–790, August 1989.

[Ga62] R. G. Gallager. Low density parity check codes. IEEE Trans. Information Theory , 8:21–28, January 1962.

[Ga63] R. G. Gallager. Low-Density Parity-Check Codes . MIT Press, Cambridge, MA, 1963.

[GaChPiScBe01] R. Garello, F. Chiaraluce, P. Pierleoni, M. Scaloni, and S. Benedetto. On error oor and free distance of turbocode. In Proc. International Conf. Communications , pages 45–49, Helsinki, Finland, jun. 2001.

[HeCh01] J. Heo and K. M. Chugg. Constrained iterative decoding: performance and convergence analysis. InProc. Asilomar Conf. Signals, Systems, Comp. , pages 275–279, Pacic Grove, CA, nov. 2001.

[JiKhMc00] H. Jin, A. Khandekar, and R. McEliece. Irregular repeataccumulate codes. In Turbo Code Conf. , Brest, France,2000.

[Ma97] D. J. C. MacKay. Good error-correcting codes based on very sparse matrices. IEE Electronics Letters , 33:457–458,March 1997.

[MaPiRoZa99] G. Masera, G. Piccinini, M. Ruo Roch, and M. Zamboni. VLSI architectures for turbo codes. IEEE Trans. VLSI ,7(3), September 1999.

[NaAlNa01] K. R. Narayanan, I. Altunbas, and R. Narayanaswami. On the design of LDPC codes for MSK. In Proc. Globecom Conf. , pages 1011–1015, San Antonio, Texas, nov. 2001.

[PiHuPh99] L. Ping, X. Huang, and N. Phamdo. Zigzag codes and concatenated zigzag codes. IEEE Trans. Information Theory , 47:800–807, Feb. 2001.

[PiHuPh99b] L. Ping, W. K. Leung, and N. Phamdo. Low density parity check codes with semi-random parity check matrix.IEE Electron. Lett. , 35(1):38–39, Jan. 1999.

[ThCh00] P. Thiennviboon and K. M. Chugg. A low-latency SISO via message passing on a binary tree. In Proc. Allerton Conf. Commun., Control, Comp. , October 2000.

[Vi98] A. J. Viterbi. Justication and implementation of the MAP decoder for convolutional codes. IEEE J. Select. Areas Commun. , 16:260–264, February 1998.

[Wi96] N. Wiberg. Codes and Decoding on General Graphs . PhD thesis, Link¨oping University (Sweden), 1996.

51

Date post:	04-Jun-2018
Category:	Documents
Upload:	pdfee
View:	227 times
Download:	0 times

TUTORIAL - Iterative Detection & Turbo-Like Codes-K. Chugg

Documents