ECE 520 Project – Differential Input Differential Output OP­AMP  

    

         by     

Karthikvel Rathinavel  Salman Safdar 

           

In partial fulfillment of the requirements for the course of 

Analog CMOS Integrated Circuits         

Department of Electrical Engineering and Computer Science Oregon State University 

Corvallis June, 2015 

Project Statement: 

Design a differential input differential output op­amp with capacitive feedback.  Given Specifications: 

Closed Loop Gain  5 

Load Capacitance   2p F 

Settling Time   30nS for 0.01% settling 

Supply Voltage (Vdd)  1.8 V 

HD3 (Closed Loop)  < ­50 dB 

Reference Current Source  100u A 

 Design Approach In our design, we have used a two stage folded cascode differential amplifier. Since we were getting about                                   43 dB gain from our first stage, we used a second stage amplifier in order to achieve higher gain. But, it                                         came with expense of not getting required bandwidth and phase margin. In order to compensate our                               phase, we used Ahuja compensation by using two capacitors as a feedback from our differential outputs.                               The real challenge was to find the best points and capacitor values to get our desired bandwidth and phase                                     margin. After many simulations of changing capacitance and Ahuja compensation points, we were able to                             find the excellent bandwidth and phase margin. In figure 1, shows the points in our schematic where we                                   did our compensation and capacitance. We ran the simulation and found the phase margin to be at 67.1                                   degrees, which keeps the output response stable.   The second stage under open loop operation had a simulated bandwidth of 290.4 MHz and a gain of 94                                     dB. Device sizes were first fixed according to the ratio of current through the transistors. For example in                                   figure 1, T1 and T23 carry twice the current of T22. Thus we initially used a channel width which was                                       twice the channel width of T22. In order to bring all the transistors in saturation we took into account the                                       square law and accordingly kept changing the bias voltages and device sizes, until we reached the                               optimum condition where all the MOSFETs were in saturation.  Next we designed our common mode feedback circuit in addition to the bias circuit which consists of                                 active current mirrors supplied by a single DC voltage of 1.8V and a current source of 100 uA. By                                     carefully varying the device sizes of the transistors, we got the required DC biasing voltages for all the                                   transistors, including common mode voltage which was later designed after we performed the closed loop                             analysis.      

Our simulated project specifications are summarized in the table below.   

Our Project Specifications  Values 

Closed Loop Gain  14.04 dB 

Open Loop Gain  94 dB 

Bandwidth  290.4 MHz 

Phase Margin (PM)  67.1 Degree 

Capacitance for Ahuja Compensation  1.7 p F  

                    

Project Schematics 

Figure 1: Open loop Schematic without common mode feedback 

Figure 2: Open loop Schematic including common mode feedback  

Figure 3: Biasing Circuit used to keep all the transistors in saturation                     

Simulated AC Performances 

 Figure 4: 290.4 MHz Open Loop Bandwidth  

 

 Figure 5: Open Loop Phase Margin 

Closed Loop Our project requires us to have a closed loop gain of 5 (13.98 dB), in order to achieve this                                     requirement we used a series capacitance of 10pF and a feedback capacitance of 2pF. We                             simulated our closed loop circuit loop and got 14.04 gain which was above the minimum project                               requirement (as shown in figure 6).  

 Figure 6: Closed loop Schematic without Common Mode feedback Circuit 

 Figure 7: Closed Loop Gain  

Our project requirement for closed loop gain is 5 or 13.98 dB. This determined our choice of capacitance                                   of feedback and series capacitors. In the above plot, the steady state closed loop gain is observed to be                                     14.04 dB. 

 Figure 8: Closed Loop Phase Response  

 Common Mode For the common mode to differential mode rejection we used a single AC voltage source of peak                                 amplitude 500mV for both our inputs and used a capacitor and inductor divider to isolate the DC                                 bias and AC signals in our closed loop circuit. The schematic used for our common mode to                                 differential mode rejection is shown below. 

 Figure 9: Schematic for Common mode to Differential mode rejection 

 Since we applied the same AC signal to both our inputs (positive and negative inputs) the amplifier tries                                   to reject the common signal and the output response between the differential nets is thus negative. This is                                   illustrated in the plot below.  

 Figure 10: Common Mode to differential mode rejection 

Transient simulation with positive and negative step responses with settling time 

 Figure 11: Schematic for Transient Simulation  

 Figure 12: Plot for Rise Settling Time 

Rise time Calculation:  V­(0.01/100) = 99.999, here V is 100. As seen from the plot, 1.93­1.90=0.03 ms which is equal to 30 ns,                                       making it a decent settling time. 

 

 Figure 13: Plot for Fall Settling time 

 In order to conduct transient analysis, we observed the simulation of the response of the amplifier to a                                   positive and negative pulse and observed its fall time and rise time. We then found the rise time by                                     observing the time it took for the response to go from 0% to 99.99%. A similar observation of the                                     simulation was made for the fall time. As seen from the above figure settling time here 30ns, which is in                                       accordance with our project requirement. The test bench proved to be a useful tool in finding the transient                                   response of the amplifier.  

 Figure 14: Plot for finding settling time for a step response 

 

                    

Simulation of HD2 and HD3 using transients 

 Figure 15: Closed Loop Schematic for analyzing harmonic distortion (1) 

 

 Figure 16: Closed Loop Schematic for analyzing harmonic distortion (2), Common Mode feedback 

Plot for analysing HD2 and HD3 in Closed Loop operation of the amplifier: 

 Figure 17: HD2 and HD3 under Closed Loop 

  Open Loop Schematic: 

 Figure 18: Open Loop Schematic (1) 

 

 Figure 19: Open Loop Schematic (2), Common mode feedback Circuit 

 Figure 20: HD2 and HD3 under Open Loop  

 Results: The differential input differential output amplifier (two stage folded cascode topology) was successfully designed and was observed to meet all the project requirements. References