APPLICATION NOTE U-165 - SLUU096 - JUNE 2001Lisa Dinwoodie

Reference Design:Isolated 50 Watt Flyback Converter Using

the UCC3809 Primary Side Controller

1

U-165UNITRODE CORPORATION

Reference Design:Isolated 50 Watt Flyback Converter Using the UCC3809 Primary Side ControllerBy Lisa Dinwoodie

ABSTRACTThe flyback power stage is a popular choice for single and multiple output dc-to-dc converters at powerlevels of 150 Watts or less. Without the output inductor required in buck derived topologies, such as theforward or push-pull converter, the component count and cost are reduced. This application note will re-view the design procedure for the power stage and control electronics of a flyback converter. In these iso-lated converters, the error signal from the secondary still needs to cross the isolation boundary to achieveregulation. By using the UC3965 Precision Reference with Low Offset Error Amplifier on the secondaryside to drive an optocoupler and the UCC3809 Economy Primary Side Controller on the primary side, asimple and low cost 50 Watt isolated power supply is realized.

INTRODUCTIONThe flyback converter reviewed in this applicationnote is specifically designed to interface with thevoltage ranges used in the telecommunications in-dustry. The primary goal of this 5V, 50 Watt powersupply is an efficient design which meets all thespecifications while maintaining low cost. This goal

is achieved by using the UCC3809 on the primaryside for fixed frequency current mode control andusing the error amplifier and precision reference ofthe UC3965 on the secondary side. Each of these8-pin integrated circuits requires minimal externalparts resulting in an economical yet effective de-sign. The schematic is shown in Figure 1 and thelist of materials is tabulated on page 16.

2

U-165APPLICATION NOTE

C23

6800

pF

T1

80µH

5:1

C10

0.22

µF

R9

2K 3W

TP

5

TP

4R

10 10

R13

1.1K

R11

680

Q3

IRF

640

D3

SF

24Q

22N

2907

A

D4

1N52

40

8 7 6 54321

UC

C38

09

U1

FB

RE

F

SS

RT

1

RT

2

VD

D

OU

T

GN

D

C8

1µF

C9

0.1µ

FC

70.

47µF

TP

3

TP

1

R5

470

R20

5.62

K

C22

0.1µ

FQ

42N

2222

A

R18

3.01

K

C6

330p

FD

11N

5231

BD

21N

5245

R7

15K

R6

1K

R8

0.15

3W

R4

6.19

K

R3

12.1

K

TP

2

C5

1nF

C4

0.01

µF

Q1

2N22

22A

R1

5.1K R2

1.1K

ON

/OF

F

–VIN

C3

1µF

+V

IN

C2

150µ

F

C1

150µ

F

R12

27K

1 2 3 45678

UC

3965

GN

D

VO

UT

VC

C

OF

FS

ET

CO

MP

VF

B

VR

EF NI

U4

C12

0.1µ

F

C11

1µF

C21

47µF

R15

10K

C14

470p

F

R21

475

1%

R16

12.1

K1%

D5

1N58

19

R14

750

H11

AV

1

U3

321

456

TP

6

R17

12.1

K1%

C13

0.1µ

F

C15

0.01

5µF

R19

5.1K 3W

U2

MB

R25

35C

TL

13

2

C16

330µ

F6.

3V

C17

330µ

F6.

3V

C18

330µ

F6.

3V

C19

330µ

F6.

3V

L1 2µH

C20

33µF

10V

V0

+5V SG

ND

2

SG

ND

1

PG

ND

2

PG

ND

2

PG

ND

1

Figure 1. Schematic diagram of the –48V to +5V flyback converter.

UDG-98125-1

3

U-165APPLICATION NOTE

POWER SUPPLY SPECIFICATIONS

Input VoltageRange:

–72VDC to –32VDC(–48VDC nominal)

Output Voltage: +5VDCLoad: 0A to 10ARegulation: ±2% Over Load, Line, and

TemperatureIsolation: 1500VRMS

DESIGNING THE POWER STAGE

Flyback TopologyThere are many standard power converter topolo-gies available to choose from, each with its advan-tages and disadvantages [1]. After carefulconsideration, taking into account factors such aslow power, simplicity, isolation, input and output rip-ple currents, and low cost, the flyback configurationwas chosen. The basic flyback converter topologyis shown in Figure 2.

Control MethodVoltage mode control was past over in favor of cur-rent mode control because current mode controlresponds immediately to line voltage changes andprovides inherent over current protection for theswitching device. Traditional peak current modecontrol compares the amplified output voltage errorwith the primary inductor current signal. Using theUCC3809 pulse width modulator (PWM) as thecontroller, the amplified output voltage error andthe primary inductor current ramp are summed andcompared to a 1V threshold. The inner current con-trol loop contains a small current sense resistorwhich senses the primary inductor current. The re-sistor transforms this current waveform into a volt-

age signal that is fed directly into the primary sidePWM comparator. This inner loop determines theresponse to input voltage changes. The outer volt-age control loop involves comparing a portion ofthe output voltage to a reference voltage at the in-put of the secondary side error amplifier. This di-vided down output voltage drives the invertinginput to the error amplifier in the UC3965 whichthen drives an internal inverting output buffer. Theresulting output then drives an optocoupler. Theoptocoupler output is also fed directly into the pri-mary side PWM comparator. As the output voltageincreases above the desired level, the optocoupleris driven harder on, forcing the PWM comparator toshut off the gate drive to the switching element.This outer loop determines the response to loadchanges.

Peak current mode control requires simpler com-pensation, has pulse-by-pulse current limiting, andhas better load current regulation. Because thesecondary currents are already quite large, contin-uous conduction mode (CCM) was chosen. Pri-mary and secondary RMS currents can be up totwo times higher for discontinuous mode than forCCM. Discontinuous conduction mode would re-quire using a transistor with a higher current rating.Because the output ripple current is less than itwould be if discontinuous mode were used, theoutput capacitors are smaller.

Continuous conduction mode has the disadvan-tage of requiring a higher magnetizing inductanceto stay in CCM throughout the entire operatingrange and a right-half-plane zero in its transferfunction. Feedback loop stabilization will be dis-cussed in a later section.

Maximum Duty Cycle and Turns RatioNow that the topology (flyback) and control method(peak current mode control) have been decidedupon, the next decision to be made is what themaximum duty cycle, Dmax, should be. The dutycycle is the ratio of on-time of Q1, Figure 2, to totalperiod, or D = ton/ T. In a CCM flyback converterthe maximum duty cycle will determine the turnsratio of the transformer and impact the maximumvoltage stress on the switching element. For thisdesign, a maximum duty cycle of 45% was se-lected. Limiting the duty cycle increases the num-ber of controller ICs to chose from because manyavailable today have maximum duty cycle limita-tions of 50%.

COUT VOUT

IS ILOAD

NSNP

IP

VIN D

S

Q1G

D1

-

-

+ +

Figure 2. Flyback converter circuitconfiguration.

UDG-98126

4

U-165APPLICATION NOTE

The DC transfer function of a CCM flyback con-verter is:

V VV V N

DD

O D

IN Rds on

+= ×

(min) ( )

max

max– –1

1

(1)

where VO equals the output voltage, 5V,

VD = forward voltage drop across rectifier D1, as-sumed to be 0.8V,

VIN = 32 to 72V, VIN(min) = 32V,

VRds(on) = on voltage drop across MOSFET Q1,equal to Rds(on) x I(primary), assumed to be 1V,

N = turns ratio, equal to NP/NS,

NS = number of transformer secondary turns,

NP = number of transformer primary turns,

D = duty cycle.

Maximum duty cycle, 0.45, occurs at minimum in-put voltage. Substituting these values into (1) givesus a turns ratio of 4.66. The turns ratio is inverselyproportional to the peak primary current, IPEAK, butdirectly proportional to the voltage stress on theswitching element. So the peak currents will notbecome unreasonably high and the voltage stresson the MOSFET will be kept as low as possible,the turns ratio is rounded up only to the next inte-ger value, 5, or simply five primary turns for everyone secondary turn. Recalculating equation (1) re-sults in an actual Dmax of 48%.

Switching FrequencyBecause the magnetic components and filters willbe smaller, the tendency is to have as high aswitching frequency as possible. Unfortunately, thedecision is not quite that clear cut. Core losses,gate charge currents, and switching losses in-crease with higher switching frequencies; peak cur-rents increase with lower switching frequencies. Acompromise must be reached between componentsize, current levels, and acceptable losses. Syn-chronization with other systems and backwardcompatibility may also be deciding factors. For thisdesign, a fixed frequency (fsw) of 70kHz was cho-sen. At Dmax equal to 48%, ton(max) becomes6.9µs.

Transformer Design [2]The transformer in a flyback converter is actually acoupled inductor with multiple windings. Trans-

formers provide coupling and isolation whereasinductors provide energy storage. The energystored in the air gap of the inductor is equal to:

( )E

L IP PEAK=× 2

2

(2)

where E is in Joules, LP is the primary inductancein Henries, and IPEAK is the peak primary current inAmperes. When the switch is on, D1 (from Figure2) is reverse biased due to the dot configuration ofthe transformer. No current flows in the secondarywindings and the current in the primary windingramps up at a rate of:

∆

∆

I

t

V V

L

L IN Rds

P=

(min) (– on) (3)

where VIN(min) and VRds(on) were defined previouslyand ∆t is equal to ton(max) at VIN(min). The outputcapacitor, COUT, supplies all of the load current atthis time. Because the converter is operating in thecontinuous conduction mode, ∆IL is the change inthe inductor current which appears as a positiveslope ramp on a step. The step is present becausethere is still current left in the secondary windingswhen the primary turns on. When the switch turnsoff, current flows through the secondary windingand D1 as a negative ramp on a step, replenishingCOUT and supplying current directly to the load.

Based on (3), the primary inductance can be calcu-lated given an acceptable current ripple, IL. Forthis design, IL was set to equal one-half the peakprimary current. For a CCM flyback design, thepeak primary current is calculated based upon (4).

( )I

I

N DI

PEAKOUT L=

×

+

max

max–1

1 2

∆ (4)

By replacing IL with ½(IPEAK), IOUT(max) with 10A,Dmax with 0.48, and N with 5 as detailed earlier,the peak primary current is calculated to be 5.16Aand IL calculates to 2.58A. The root mean square,RMS, current of a ramp on a step waveform is de-fined in (5) and calculates to be 2.74A for this ap-plication.

( ) ( ) ( )I

t

TI I I

I

rms

onPEAK L PEAK

L

=

× × +

max–

22

3∆

∆

(5)

5

U-165APPLICATION NOTE

Using (3), LP calculates to approximately 80µH.Due to cost considerations and a switching fre-quency of 70kHz, the core material was chosen tobe manganese zinc ferrite 3C85 from Philips. Be-cause the inductor (a.k.a. the flyback transformer)is driven in one quadrant of the B-H plane only, alarger core is required in a flyback design. Becausethis converter is operating in the continuous con-duction mode at a relatively low frequency, themaximum peak flux density, Bmax, is limited by thesaturation flux density, Bsat. Taking all this into con-sideration, the minimum core size is determined by(6).

APL I I

k BP PEAK rms=

× × ×× ×

10

420

4 1 31

max

. (6)

where AP = the core area product in cm4,

k = winding factor, equal to 0.2 for a continuousmode flyback,

Bmax ≈ Bsat, or 0.33 Telsa for 3C85 material at100 C.

The result of (6) is compared to the product of thewinding area, Aw (cm2), and effective core area,Ae (cm2), listed in the core manufacturer’s datasheet. For this design, a Philips EFD30 core metthe minimum criteria.

The minimum number of primary turns is deter-mined by:

NL I

B AePP PEAK=

× ××

104

max

(7)

Based upon this result and the predeterminedturns ratio, the number of secondary turns is estab-lished. With a turns ratio of 5 and NP equal to 20,NS is calculated to be 4.

The energy stored in the flyback transformer is ac-tually stored in an air gap in the core.This is be-cause the high permeability of the ferrite materialcan’t store much energy without saturating first. Byadding an air gap, the hysteresis curve of the mag-netic material is actually tilted, requiring a muchhigher field strength to saturate the core. The sizeof the air gap is calculated using (8).

( )gap o r N Ae

LP

P=

× × × ×µ µ 2 210– (8)

In (8), the gap is measured in centimeters, µo is thepermeability of free space equal to 4 10-7 H/m,and µr is equal to the relative permeability of thegap material (in this case the gap material is air, µr=1). This gap is calculated to be 0.043cm and isevenly distributed between the center post and twoouter legs of the EFD30 core.

The primary windings are two strands of 21AWGmagnet wire in parallel, the first layer wound clos-est to the core, the second layer over the second-ary windings. The secondary windings consist offour strands of 18AWG magnet wire in parallel, fill-ing a single layer for maximum coupling.

Using a primary inductance of 80µH and a maxi-mum duty cycle of 48% means the converter willnot stay in continuous mode control over the entireoperating range because of the relationship ex-pressed in (9).

( )( ) ( ) ( )( )P

V V V t

T L

O

IN D IN on

P

(min)

min min max–

.

=

× ×

× ×

2

2 5

(9)

According to (9), at the 32V minimum input voltagethe converter will enter discontinuous mode at anoutput load current of less than 3.33A. To remain inCCM would require a much larger transformer,264.5µH at 48% duty cycle. Increasing the primaryinductor value requires a much larger core, such asthe E41/17/2 core set from Philips. This would re-quire 60% more circuit board space than the pres-ent core.

Another approach to guarantee remaining in con-tinuous mode is to reduce the maximum duty cycleto approximately 26% and continue to use an 80µHflyback inductor.Unfortunately, the result of thiswould be considerably higher peak currents. Higherpeak currents result in an increase of all the I2Rlosses, and a larger core would be needed anywayto satisfy the core area product limit which is de-pendent upon the peak primary current as ex-pressed in (6).

6

U-165APPLICATION NOTE

It is far better to design for continuous mode and totransition into discontinuous mode than the otherway around. Discontinuous mode is actually un-avoidable at zero load. A continuous mode feed-back control loop has the ability to maintainstability while in discontinuous mode. However, acontrol loop designed for discontinuous operationdoes not take into account the already eluded toright-half-plane zero present in continuous mode.This design has the fortuitous advantage of show-ing the user waveforms for both operating modesdependent upon input voltage and load current(see Figures 16 and 17).

MOSFET SelectionThe switching element in a flyback converter musthave a voltage rating high enough to handle themaximum input voltage and the reflected second-ary voltage, not to mention any leakage inductanceinduced spike that is inevitably present. Approxi-mate the required voltage rating of the MOSFETusing (10).

( )( ) ( )

V

V VNN

V V

ds

IN LP

SO D

=

+ +

× +

×max .1 3

(10)

where Vds = the required drain to source voltagerating of the MOSFET,

VL = the voltage spike due to the leakage induc-tance of the transformer, estimated to be thirty per-cent of VIN(max),

and the additional 1.3 factor includes an overallthirty percent margin.

For the flyback converter presented, the requiredminimum voltage rating of the MOSFET calculatesto be 160V. An IRF640 N-channel power MOSFETwas chosen. This device has a voltage rating of200V, a continuous DC current rating of 18A, andan Rds(on) of only 0.18Ω. By consulting the typicalgate charge vs. gate-to-source voltage waveform inthe manufacturer’s data book, calculating the aver-age current required to drive the gate capacitor ofthe FET is possible:

I Q fgate sw= ×max (11)

Qmax is the total gate charge in Coulombs, esti-mated to be 70nC based upon a gate to sourcevoltage of 15V and a drain to source voltage of160V. According to (11), the average supply currentof the controller, IVDD, needs to increase by 4.9mAto switch the gate at the selected operating fre-quency.

This FET will experience both switching and con-duction losses. The conduction losses will be equalto the I2R losses, as shown by (12).

( ) ( )P I Rcond rms ds on= ×2 (12)

Switching losses are the result of overlapping draincurrent and drain to source voltage at turn on andturn off [3]. At turn on the drain current begins toflow through the FET device when the gate voltagehas reached the Vgs threshold. This drain currentwill continue to rise until reaching its final value.Meanwhile, the drain to source voltage will remainat Vds, calculated earlier in (10). This voltagestarts to fall only after the “Miller” capacitor beginsto charge. The charging time, tch, for the “Miller” ca-pacitor is a function of the gate resistor, Rg (R10 inFigure 1), and the gate to drain “Miller” charge,Qgd, as shown in (13).

( )t

Q R

VDD Vchgd g

gs th=

×–

(13)

In (13), VDD is the bias voltage of the UCC3809and Vgs(th) is the gate threshold voltage of the FET.The whole process repeats itself in reverse at turnoff. The power dissipation of the FET’s output ca-pacitance, Coss, also contributes to the switchinglosses in the form of ½CV2f. The total switchinglosses are estimated based on equation (14).

( )P

C V fV I t fSW

oss ds swds PEAK ch sw=

× ×+ × × ×

2

2

(14)

The total FET losses are the sum of the conductionlosses (12) and the switching losses (14), calcu-lated to be 3.3W for the IRF640 FET. Without ap-propriate heatsinking, this device would have ajunction to ambient thermal resistance of 62 C/W,resulting in a junction temperature rise of 206 Cabove ambient. Heat sinking is obviously requiredto prevent the junction temperature, Tj, from ex-ceeding 150 C and avert device failure due to ex-cessive heating. The IRF640 has a junction to casethermal resistance, jc, of 1 C/W, using a siliconeelastomer heat sink pad provides a case to heatsink thermal resistance, θ A heatsink which provides a maximum thermal resis-tance, sa, of 35 C/W must be chosen for a use inan ambient temperature, Ta, of 25 C, as shown in(15a) and (15b).

( ) ( )T P P

Tj cond sw jc cs sa

a

= + × + +

+

Θ Θ Θ (15a)

7

U-165APPLICATION NOTE

( )Θ Θ Θsaj a

cond swjc cs

T T

P P=

++

––

(15b)

Diode SelectionSchottky rectifiers have a lower forward voltagedrop than typical PN devices, making it the rectifierof choice when considering reducing converterlosses and improving overall efficiency. Selectingthe appropriate Schottky for a specific applicationdepends mainly on the working peak reverse volt-age rating, the peak repetitive forward current, andthe average forward current rating of the device. Ifthe maximum working peak reverse voltage is ex-ceeded the reverse leakage current will rise aboveits specified limit. The peak reverse voltage that thedevice will be subjected to is equal to the reflectedmaximum input voltage minus the voltage dropacross the FET added to the output voltage. Themaximum average forward current rating of the de-vice must not be exceeded if the junction tempera-ture of the device is to remain within its safeoperating range. Because all current to the outputcapacitor and load must flow through the diode, theaverage forward diode current is equal to thesteady-state load current. The peak repetitive for-ward current is equal to the reflected primary peakcurrent. An MBR2535CTL Schottky rectifier fromMotorola met the requirements for the given de-sign. This device is a common cathode dualSchottky with a forward voltage drop of 0.47V anda working peak reverse voltage rating of 35V, ex-ceeding the 20V requirement of the design. Theaverage rectified forward current rating is specifiedat 12.5A per leg, 25A total, and the peak repetitiveforward current is rated for 25A per leg, or a total of50A. The design requirement is 10A total averageforward current and 26A total peak repetitive for-ward current.

Power loss in the Schotty is the summation of con-duction losses and the reverse leakage losses.Conduction losses are calculated using the forwardvoltage drop and the average forward current. TheMBR2535CTL will have conduction losses equal to4.7W. Reverse leakage losses, which are depend-ent upon the reverse leakage current, the blockingvoltage, and the on-time of the FET, are calculatedto be 0.05W. Heat sink selection is once againbased upon the required thermal resistance of theheat sink to air interface in order to maintain ajunction temperture of less than 125 C.

Input and Output CapacitorsThe input capacitors are chosen based upon theirripple current rating and their rated voltage. The in-put current waveform is shown in Figure 3. Theshaded regions represent the current actually sup-plied by the input capacitors during the switch’s on-and off-times. Because this example uses a dutycycle that is very close to 50%, this RMS current isalmost equal to the primary RMS current calcu-lated in (5).The actual capacitor value is not thatcritical as long as the minimum capacitance givesan acceptable ripple voltage determined by the fol-lowing equation:

CI

f Vrms

swmin =

× ×8 ∆(16)

In (16), Irms is equal to the RMS current, calculatedfrom Figure 3, and V is equal to the acceptableripple voltage. Two United Chemi-Con SXE series150µF capacitors in parallel met the requirementsfor the design when derated for ambient tempera-ture and frequency. The small 1µF ceramic capaci-tor is added at the converter input to provide ashorter path for high frequency ripple.

The output capacitors are also chosen based upontheir low equivalent series resistance (ESR), ripplecurrent and voltage ratings, and (16). The ripplecurrent that the output capacitor experiences is aresult of supplying the load current during the FETconduction time and its charging current during theFET off-time, as illustrated by the shaded regionsin Figure 4. During the conduction time of the FET,the secondary windings of the transformer are notconducting. The discharging of the output capacitorsupplies the 10A load current. During the FEToff-time, the secondary windings are conductingand the secondary peak current is charging theoutput capacitor and delivering the 10A current tothe load. The RMS current is calculated to be ap-proximately 14A. Four Sanyo OSCON 6SH330M330µF capacitors in parallel met the requirementsfor the demo board design when derated for ambi-ent temperature and frequency.

8

U-165APPLICATION NOTE

SETTING UP THE UCC3809The UCC3809 was selected as the primary sidecontroller for this application because of its flexibil-ity, low cost, and built in features such as program-mable maximum duty cycle, full cycleprogrammable soft start, undervoltage lockout, andlow operating current.

VDD Bias/UVLOThe employment of a constant current biasingscheme, as shown in Figure 5, minimizes trans-former design costs by eliminating the need for abootstrap winding. It also avoids any high powerdissipation that would be present in a single biasresistor. This is especially true with a wide inputvoltage range, such as seen in the telecommunica-tions industry. The current biasing scheme suppliesenough current for the gate drive, determined by(11), in addition to the maximum IVDD current re-quired to operate the internal functions of the IC.

The zener diode, D1, minus the VBE drop of thesmall signal PNP transistor, sets up a constantvoltage across the emitter resistor, Re, resulting ina constant emitter current. The selection of the col-lector resistor, Rc, ensures the transistor remainsin the active mode throughout the entire range ofVIN while maintaining VDD above the under volt-age lockout level. All of these components haveminimal power dissipation and are sur-face-mountable if desired. Although the internalshunt regulator can sink up to 25mA, D2 wasadded to minimize the power dissipation in the IC.

The UCC3809 is available with two differentundervoltage lockout (UVLO) levels and hysteresisoptions. Off-line users can take advantage of thewider hysteresis option available in the –2 devicewhile the tighter hysteresis of the –1 is optimizedfor dc-to-dc converter use. UVLO insures that theIC bias is within specification before enabling theoutput stage. This guarantees the output drive iscapable to fully turn on the MOSFET once theUVLO threshold has been reached. The outputdrive and reference voltage are actively held lowduring power-up and the IVDD starting current isless than 100µA until VDD crosses the turn-onthreshold. As VDD crosses the turn-off thresholdduring power-down, REF and the output drive arepulled low.

+VIN

IVDDVDD

D1

Rb

Re

Rc

D2

Figure 5. Constant current biasing.

UDG-98128I(A)

T

IOUT

tON tOFF

2T

Figure 4. Output capacitor current waveform.

I(A)

T

IIN

tON tOFF

2T

Figure 3. Input capacitor current waveform.

9

U-165APPLICATION NOTE

DecouplingBoth VDD and REF should be decoupled withgood quality, low ESR/ESL, ceramic capacitorsplaced as close to the VDD or REF pin as possibleand returned directly to the GND pin for the besthigh frequency performance. Because the refer-ence voltage provides the bias to many of the inter-nal circuits of the IC, its decoupling capacitorshould be at least 0.47µF for adequate filtering.

Soft Start and ShutdownThe soft start feature enables the IC to start up in acontrolled manner. While the IC is in UVLO, the SSpin is held low. Once the UVLO threshold has beencrossed, an internal 6µA current source chargesthe external soft start capacitor (C4, Figure 1). Asthe capacitor voltage ramps up from 0.8V to 2V,the output duty cycle linearly increases to a levelrequired for output voltage regulation. The soft startcapacitor is chosen so that there is a delay of ap-proximately 3 milliseconds before VOUT ramps upto its full potential. Pulling the SS pin below 0.5Vwill shut down the output and pull REF low. Thisfeature is easily implemented using a small signalNPN and a pull-down resistor to accept a logiclevel command signal.

Output DriverThe totem pole output stage of the UCC3809 hasthe ability to source 0.4A and sink 0.8A. Placing asmall resistor (R10, Fig. 1) in series with the ICoutput and the gate of the FET will damp any oscil-lations caused by the parasitic wiring inductanceand the FET’s input capacitance. To insure theMOSFET gate does not get charged to its turn-onthreshold during device start up, a pull-down resis-tor (R7, Fig. 1) is added to the gate drive. The out-put stage provides a low resistance duringovershoot and undershoot, eliminating the need forSchottky diodes on the output.

OscillatorThe data sheet gives a complete description of theoperation of the internal oscillator and optional syn-chronization schemes. The external RT1 resistor(R3, Fig. 1) and the internally generated voltageacross it control the charge current of CT (C5, Fig-ure 1). When the CT voltage is equal to 2/3 of thereference voltage, sensed through RT2 (R4, Figure1), the oscillator initiates a discharge cycle. Thedischarge current is set by RT2 and the CT voltageis sensed through RT1. When CT has dischargedto 1/3 of the reference voltage, the charging cyclebegins again.

The converter design in Figure 1 requires 48%, or6.9µs, of unrestrained on-time during its full rangeof operation. The duty cycle clamp is set at 66%, or9.5µs, so that within the range of normal operation,the output regulation is not sacrificed because ofhitting the duty cycle clamp. This clamp will effec-tively prevent the transformer from saturating whenthe input voltage is less than the minimum operat-ing range, such as during start-up, brown-outs, andshut down, without inhibiting normal operation. For100kHz switching frequency, the recommended ca-pacitor for CT is approximately 1nF, and the inter-nal capacitance of the IC is estimated to be 27pF.Setting ton of the duty cycle clamp to 9.5µs, andCT equal to 1nF, RT1 is determined by:

( )t CT pF RTON = × + ×074 27 1. (17)

RT2 is then selected to satisfy the switching fre-quency period. The oscillator frequency is approxi-mated by the following equation:

( ) ( )f

CT pF RT RTsw =× + × +

1

0 74 27 1 2.(18)

For good noise immunity, the timing componentsmust be placed as close as possible to the IC pins.

Current LimitingSelection of the current sense resistor is accom-plished by dividing the FB 1V threshold value bythe peak primary current at the desired current limitpoint, typically 120% of IPEAK.

RFB

Isensethreshold

PEAK=

×1 2.(19)

This ground-referenced resistor must be a low in-ductance type and have a rated power level tomeet the (IRMS)2 x Rsense requirement. The closeststandard value resistor that meets this requirementis used. The UCC3809/UC3965 circuit uses a0.15 resistor for current sensing. This value resis-tor equates to a maximum primary side currentlimit point of 6.67A. This would lead to a worst caseaverage short circuit output current, Isc, of 12.9Aas calculated using (4), substituting Isc forIOUT(max). Upon crossing the PWM comparatorthreshold, the internal PWM latch is reset, turningoff the output driver until the beginning of the nextoscillator charge cycle.

10

U-165APPLICATION NOTE

Current spikes caused by the leakage inductanceof the flyback transformer and the reverse recoveryof the diode could trip the current sense latch andprematurely shut off the output. This unwantedspike can be suppressed by adding a small RC fil-ter for effective leading edge blanking (Figure 6).Usually adding a few hundred nanoseconds ofblanking time is enough to ignore (or “blank”) anyunwanted current spikes. An internal 250 NMOSFET discharges the high frequency capacitor usedin this filter during the PWM off-time.

Slope Compensation [4]Sensing peak inductor current instead of averageinductor current results in a loop response that isless than ideal. Adding slope compensation to thecurrent sense signal cancels this error by maintain-ing a constant average current independent of dutycycle. Slope compensation is required for openloop stability in a current mode system with 50% orgreater duty cycles, but will benefit any currentmode application at the cost of a few small parts.

The circuit described resistively divides the oscilla-tor sawtooth at the CT node and superimposes itonto the current sense signal using an emitter fol-lower configuration as detailed in [4].

The first step in implementing slope compensationis to calculate the flyback inductor down slope onthe secondary side in amps per second:

( )S Ldidt

VL

= = sec

sec

(20)

where Vsec = VO + VD and Lsec = LP/N2. Thentransform this slope to the primary side and calcu-late the equivalent slope voltage at the sense re-sistor in volts per second:

( )( )

VS LS L

NRsense'= (21)

Next, calculate the oscillator slope at the timing ca-pacitor, CT, in volts per second:

( )( )

VS oscV

tosc

on=

∆

max

(22)

Vosc is equal to the CT peak to peak voltage,1.67V for the UCC3809. Because the oscillatorwaveform has a valley voltage greater than zero,an AC coupling capacitor is required (Fig. 6). Usingsuperpositioning and neglecting the coupling andLEB capacitors, the voltage ramp equation at theFB pin can be derived (23).

( )( ) ( )

V rampVS L RR R

VS osc RR R

SC

LEB SC

LEB

LEB SC=

×+

+×

+' (23)

The value of the RSC resistor (Figure 6) is depend-ent upon the amount of slope compensation to beadded. By equating a portion (M) of the inductor

+

–

8

1

3

4

RT2

CT

RT1

RPULLDOWN

ACCOUPLING

CAP

RSC

CLEB

RLEB

RSENSE

VOLTAGEFEEDBACK

PRIMARYCURRENT

CURRENTSENSE

1V

REF

FB

RT1

RT2

SLOPECOMPENSATION

Figure 6. The FB pin serves as a summing node for current sense, voltage feedback, and slopecompensation.

UDG-98129

11

U-165APPLICATION NOTE

downslope to the resistively divided oscillatorcharge slope, RSC can be determined.

( ) ( )VS osc RR R

MVS L RR R

LEB

LEB SC

SC

LEB SC

×+

= ××+

' (24)

( )( )R

R VS oscVS L MSC

LEB=×

×'Ω (25)

To guarantee current loop stability at 100% dutycycle, a minimum compensation of ½ the inductordown slope (M = 0.5) must be added. By addingslope compensation equal to the down slope of theinductor current (M = 1), any current perturbationwill be eliminated in one cycle. This design incor-porates approximately 80% slope compensation byusing 5.62KΩ and 1KΩ resistors for RSC and RLEB,respectively.

Voltage FeedbackThe FB pin of the UCC3809 sums the voltage feed-back signal to the current sense signal and anyadded slope compensation. The voltage feedbacksignal is from an optocoupler, which is driven froman error amplifier on the secondary side of the con-verter.The signal from the optocoupler is designedto trip the 1V threshold of the UCC3809 internalcomparator when the output voltage exceeds itsspecified limit.

SETTING UP THE SECONDARY SIDEERROR AMPLIFIER, UC3965

Because the flyback converter in this design is in-put-output isolated, the error amplifier needed tosense the output voltage is on the secondary side.The designers of the UCC3809 considered thiswhen designing the circuit and omitted the erroramplifier from this IC. Utilizing the UC3965 Preci-sion Reference and Low Offset Error Amplifier sat-isfies the requirement for a secondary side erroramplifier and has an on-board precision referenceneeded for accurate regulation.

Biasing, UVLO, and DecouplingBecause the UVLO threshold of the UC3965 is4.1V, the secondary side IC can be biased from the5V output bus. To prevent the ripple voltage fromtripping the under voltage lockout, a 47µF decoup-ling capacitor is used. A Schottky diode in serieswith the input pin is required to prevent the de-coupling capacitors from discharging with the out-put capacitors during the FET on-time.

Output Voltage SensingThe precision reference of the UC3965 is tied tothe non-inverting input of the device’s internal erroramplifier. The output voltage of the converter is re-sistively divided and compared to this reference atthe inverting input. This error amplifier has a low1mV input offset voltage that insures accurate reg-ulation of Vo. The error amplifier drives the invert-ing input of an internal buffer whose output is thenused to drive an optocoupler diode. As the outputvoltage increases beyond its desired value, thevoltage difference at the error amplifier increases.This results in less drive at the inverting input ofthe internal buffer, increasing its output drive to theoptocoupler. If the application does not require in-put-output isolation, this buffer could be used todrive the PWM directly.

Loop Compensation [5] [6]As previously alluded to, a continuous currentmode flyback will contain a right-half-plane (RHP)zero in its transfer function. What exactly does thismean? Basically, any increase in load current willrequire the primary peak inductor current to in-crease. The duty cycle must increase to accom-plish this. In a flyback converter, the inductorcurrent flows to the output only when the FET is offand the diode is conducting. Increasing the dutycycle increases the FET conduction time but de-creases the diode conduction time. Ironically, theresult of this is the average diode current, the cur-rent that supplies the load, actually decreases. Thisis a temporary situation; as the inductor currentrises, the diode current eventually reaches itsproper value. The condition where the average di-ode current must actually decrease before it canincrease is referred to as a right-half-plane zero. Tocomplicate matters, this zero contributes a phaselag, not a phase lead as a normal zero would. Thiszero moves in frequency as a function of load andinput voltage, as shown in (26), making it impossi-ble to cancel out by the insertion of a pole.

( )

f

R N V

L V N V

RHPZERO

OUT IN

OUT P IN OUTv

=

× ×

× × × × + ×

2

22 π ( )

(26)

The easiest way to deal with a right-half-plane zerois to roll off the loop gain at a relatively low fre-quency using simple dominant pole compensation.Unfortunately, the result of this is poor dynamic re-sponse.

12

U-165APPLICATION NOTE

The primary goal of the compensation network isto provide good line and load regulation and dy-namic response. These objectives are best met byproviding high gain at low frequencies for good DCregulation and high bandwidth for good transientresponse. Optimum closed loop performance canonly be achieved by first knowing what the transfercharacteristic of the PWM and switching circuitlooks like. Constructing a Bode plot of the knownpoles and zeroes in the power stage does this.Bode plots give a visual interpretation of the gainversus frequency and phase versus frequencycharacteristics of a system. In the gain plot, thegain shown at each frequency represents theamount by which the feedback loop will reduce adisturbance at that frequency.

Besides the RHP zero, the output capacitor andthe load contribute a pole at a frequency deter-mined by (27), and the output capacitor alone willcontribute a zero based upon its ESR and capaci-tance as shown in (28).

fD

R CpoleOUT OUT

=+

× ××1

2 π(27)

fESR Czero

OUT=

××1

2π(28)

The control to output gain [7] is calculated using(29):

( ) ( )

GAIN

I R V

V D N V Vsc OUT IN

C O IN

=

× ×× ×

× × × × +

20

1 2log

–

(29)

In this equation, the output short circuit current, Isc,was calculated previously. Vc is the control voltage,equal to 2.5V in the UC3965. In addition to the con-trol to output gain, the optocoupler will also contrib-ute a gain based upon its current transfer ratio anda phase lag due to its large collector to base ca-pacitance. Because the optocoupler data sheetusually does not include any frequency dependentcurves, the bandwidth was measured in the lab us-ing a network analyzer. The gain contribution fromthe optocoupler averaged 7dB and the expectedpole was not evident in scans run up to 60kHz. Theclosed loop gain of the inner current loop is equalto the inverse of the sense resistor, 1/Rsense, or16dB. By adding all of these factors together, aBode plot of the uncompensated system can be re-alized.

Once the frequency response of the uncompen-sated system is determined, the next step is to de-termine what compensation is needed around theerror amplifier for optimum performance. As statedearlier, optimum performance requires a high gainat low frequencies for good DC regulation and highbandwidth for good transient response. The cross-over frequency, fc, is the frequency at which thegain magnitude equals 0dB. High bandwidth isachieved by having the highest possible fc. Be-cause of the RHP zero, the highest possible cross-over frequency is limited to fRHPZERO/ .The phasemargin, or the amount the phase lag measures atfc less 180 , should be at least 45° for good tran-sient response with little overshoot.The magnitudeof the gain at the frequency where the phase plotmeasures –180 is referred to as the gain margin.If the slope of the gain plot is –2, or –40dB/decade,at low frequencies, it must transition to a –20dB/de-cade slope, also known as a –1 slope, one decadebefore crossing the 0dB point.If the slope remainsat the –2 slope the resultant gain margin would betoo small causing severe underdamped oscillationsat fc.

With all these tricks of the trade in mind, the com-pensation network is designed around the erroramplifier.A certain amount of juggling is inevitablebut, in general, the scheme shown in Figure 7 willhandle most compensation requirements. There isa pole at the origin which contributes a –1 slope inthe gain plot, a low frequency zero, fEAZERO (30),flattens out the slope so the midrange gain is equalto Rf/Ri. A high frequency pole, fEAPOLE (31), helpssuppress any high frequency noise from propagat-ing through the system. Rd forms a voltage dividerwith Ri and provides a DC offset. By combining theBode plots of the PWM and power stage with theerror amplifier compensation, a plot of the entiresystem is realized.

Ri

Rd

Rf

Cp

Cf

VO

VC

Figure 7. Error amplifier compensation network.

UDG-98130

13

U-165APPLICATION NOTE

fR CEAZERO

f f=

× × ×1

2 π(30)

fR CEAPOLE

f p=

× × ×1

2 π(31)

The following graphs show examples of Bode plotsbefore and after compensation.

SNUBBERS AND CLAMPS [7]Transformer leakage inductance imposes hightransients in the switch, requiring a switching de-vice with an excessive voltage rating. The primaryside of the demo board utilizes a passive polarizedvoltage clamp (Figure 12) to suppress the voltageovershoot during the turn-off transition of the FET.This circuit limits the peak switch voltage, reducingthe power dissipation in the switching device. Thetotal dissipated energy remains the same, but it isnow divided between the clamp resistor and theFET.

The parasitic inductance of the transformer is dis-charged into the capacitor during each switchingcycle. The value of the capacitor is selected basedupon the amount of energy that this leakage induc-tance stores plus the initial energy stored in the ca-pacitor from the input voltage and the reflectedoutput voltage. Equation 32 determines the mini-mum capacitor value.

Figure 10. Phase Bode plot withoutcompensation.

-50

-40

-30

-20

-10

0

10

20

30

40

50

1 10 100 1000 10000 100000 1000000

FREQUENCY (Hz)

GA

IN(d

B)

Error Amplifier Combined Uncompensated Overall

Figure 9. Gain Bode plot with compensation.

Figure 11. Phase bode plot with compensation.

Figure 8. Gain Bode plot withoutcompensation.

CR

D

NVIN

VIN+N(VO+VD)

Figure 12. RCD clamp on the primary sidesuppresses voltage overshoot across the FET.

UDG-98131

14

U-165APPLICATION NOTE

( )( )C

L I

V V VL PEAK

c c=

×

× +

2

2∆ ∆

(32)

In the above equation, ∆Vc is equal to the accept-able change of voltage across the capacitor, usu-ally between 40 and 60V. LL is equal to the leakageinductance of the transformer. IPEAK is equal to thepeak current in the inductor at the time of turn-off.V is equal to the DC bias across the capacitor. ThisDC bias is a result of the DC path through the re-sistor and diode and the secondary side voltagereflected to the primary:

( )V N V VO D= × + (33)

The resistor is selected such that the RC time con-stant is much longer than the switching period. Thisresistor must not only dissipate the energy storedin the leakage inductance, but also the voltage dueto the DC bias of the capacitor:

( )P

L I f VRR

L PEAK sw=× ×

+2 2

2

(34)

The resistor used on the demo board must dissi-pate 2.4W of power. The diode is selected basedupon the charging current of the capacitor.

The secondary side of the converter requires anRC snubber across the diode (Figure 13) to dampthe high frequency ringing on the 5V bus due tothe parasitic inductance of the transformer and par-asitic capacitance of the Schottky.

The capacitor is chosen such that, when placedacross the Schottky, the oscillating frequency, fosc,is reduced by approximately half. The leakage in-ductance, LSL and parasitic capacitance, Cp can bedetermined by simultaneously solving (35a)

fL Cosc

SL p=

× × ×1

2 π(35a)

( )f

L C C

osc

SL p2

1

2=

× × × +π

(35b)

In (35b), C is the capacitor that was added to re-duce the oscillation frequency. The appropriatevalue of the resistor is selected to provide criticaldamping to the oscillation:

( )RL

C C

L

p

=+

(36)

Because the time constant of this RC snubber ismuch less than the switching period but much lon-ger than the voltage rise time, the power dissipatedby the resistor is dependent upon the energystored in the capacitor. Since the capacitor chargesand discharges each cycle, the power the resistormust dissipate is equal to:

P C V fR sw= × ×2 (37)

In (37), C is the RC snubber capacitor value. V isequal to the drain to source voltage reflected to thesecondary side added to the output voltage plusthe voltage drop across the diode. This snubber cir-cuit will prevent the anode of the diode from ringingbelow the reverse voltage rating of the Schottky de-vice.

LC FILTERThe voltage ripple on the output will occur at theswitching frequency and is required to be less than50mV peak to peak. To meet the output noisespecification, an LC filter was added to the con-verter output. The unfiltered ripple, VR, will beequal to the peak secondary current multiplied bythe ESR of the output capacitor bank. The amountof attenuation needed to filter the ripple, VR, to anacceptable level is determined by (38)

ATTENV

dbR= × ×

– log

.20

0 05(38)

An LC filter will produce a gain plot with a–40dB/decade slope. The selected LC filter shouldhave a pole that results in a minimum gain derivedfrom (38) at the switching frequency. The pole fre-quency will occur at:

fLCpole =

× ×1

2 π(39)

This design employs a 2mH iron powder toroid anda 33mF electrolytic capacitor for a pole frequencyof 20kHz and a minimum gain of –8dB.

C R

N

Figure 13. RC snubber on the secondary sidedampens parasitic oscillations.

UDG-98132

15

U-165APPLICATION NOTE

EXPERIMENTAL RESULTSThe oscilloscope traces refer to the test points (TP)indicated and are referenced to the appropriateground, either primary or secondary.

In Figure 18, the FB pin is shown in the bottomtrace. Region A is the summation of the currentsense and voltage feedback , at 1V the gate isturned off, resulting in the drain establishing a volt-age with respect to the source. Region B resultsfrom the FB pin still sensing the voltage feedbackduring the remaining oscillator charge time. RegionC is where the internal 250 on resistance FET isturned on during the PWM off time, discharging allexternal capacitance at that node.

Efficiency measurements performed yielded thefollowing results.

VIN(V)

IIN(A)

PIN(W)

VOUT(V)

IOUT(A)

POUT(W)

n

31.763 1.830 58.126 5.019 9.211 46.225 0.795

31.954 1.809 57.805 5.014 9.178 46.022 0.796

48.014 1.178 56.560 5.017 9.202 46.168 0.816

48.073 1.172 56.342 5.015 9.185 46.060 0.818

72.038 0.780 56.190 5.015 9.187 46.071 0.820

Figure 14. The UCC3809 gate drive andoscillator.

Figure 15. Soft start capacitor chargingwaveform.

Figure 16. Gate and drain in continuousconduction mode.

Figure 17. Gate and drain in discontinuousconduction mode.

TP2OSCILLATORAT C5-R3-R4

NODE

TP5DRAIN

VOLTAGE

TP1FB PIN

AB

C

Figure 18. The FB pin in continuous conductionmode.

16

U-165APPLICATION NOTE

ALTERNATE OUTPUT VOLTAGESA user may require an output voltage different fromthe 5V discussed thus far. By working through thisdesign review and substituting the required outputvoltage level, new peak currents and maximumduty cycles can be determined. These changes willbe reflected in the selection of appropriate compo-nents such as the MOSFET, sense resistor, diode,and output capacitors. The transformer would beredesigned for the optimum turns ratio, wire sizes,and core requirements for the given design.

ReferenceDesignator

Description Manufacturer Part Number

C1, C2 150mF, 80V, Aluminum Capacitor United Chemi-Con SXE80VB151M12X20LL

C3 1µF, 100V, Ceramic Capacitor KEMET C340C105K1R5CA

C4, C22 0.01µF, 50V, Ceramic Capacitor

C5 1nF, 50V, Ceramic Capacitor

C6 330pF, 50V, Ceramic Capacitor

C7 0.47µF, 50V, Ceramic Capacitor

C8 1µF, 50V, Ceramic Capacitor

C9, C12 0.1µF, 50V, Ceramic Capacitor

C10 0.22µF, 100V, Ceramic Capacitor KEMET C330C224K1R5CA

C11 1µF, 35V, Tantalum Capacitor

C14 0.22µF, 50V, Ceramic Capacitor

C15 0.015µF, 50V, Ceramic Capacitor

C16, C17, C18, C19 330µF, 6.3V, Aluminum Capacitors SANYO OSCON 6SH330M

C20 33µF, 10V, Tantalum Capacitor

C21 47µF, 25V, Aluminum Electrolytic Panasonic ECE-A1AFS470

C23 6800pF, 50V, Ceramic Capacitor

D1 ZENER, 5.1V 1N5231

D2 ZENER, 15V 1N5245

D3 2A, 200V, Ultra Fast SF24

D4 ZENER, 10V 1N5240

D5 1A Schottky 1N5819

L1 2.5 H, 11A Coiltronics, Inc. CTX08-14017

Q1, Q4 small signal NPN MPS2222A

Q2 small signal PNP MPS2907A

Q3 200V, 18A, N-Channel MOSFET Motorola or IR IRF640

R1 5.1K, ¼W, 5%

R2, R13 1.1K, ¼W, 5%

R3 12.1K, ¼W, 5%

R4 6.19K, ¼W, 5%

R5 470, ¼W, 5%

Table 1. Bill of Materials.

OUTPUTRIPPLE

Figure 19. Output voltage ripple waveform.

17

U-165APPLICATION NOTE

ReferenceDesignator

Description Manufacturer Part Number

R6 1.0K, ¼W, 5%

R7 15K, ¼W, 5%

R8 0.15, 3W, 5% RCD RSF2B0.15 ohm 5%

R9 2K, 3W, 5% RCD RSF2B2K ohm 5%

R10 10, ¼W, 5%

R11 680, ¼W, 5%

R12 27K, ¼W, 5%

R14 750, ¼W, 5%

R16, R17 12.1K, ¼W, 1%

R18 3.01K, ¼W, 5%

R19 5.1, 3W, 5% RCD RSF2B5.1 ohm 5%

R20 5.62K, ¼W, 5%

R21 475, ¼W, 1%

T1 80µH, N = 5 Coiltronics, Inc. CTX08-13916

U1 PWM Controller Unitrode UCC3809

U2 25A, 35V Power Schottky Rectifier Motorola MBR2535CTL

U3 Optocoupler Motorola H11AV1

U4 Error Amplifier, Reference Unitrode UC3965

Heatsink For TO-220 AAVID 529802 B 0 25 00

SUMMARYThe UCC3809/UC3965 design is an example of a 50Watt continuous current mode flyback converter thatincludes features such as a duty cycle clamp, slopecompensation, input to output isolation, and primaryand secondary snubbers, just to name a few. A de-tailed step by step approach is given for power stagecomponent selection, transformer design, loop com-pensation, and component power dissipation calcu-lations. The features of the UCC3809 offer designflexibility for a wide range of applications in simple touse 8-pin packages.

REFERENCES[1] Abraham I. Pressman, Switching Power Supply De-

sign, McGraw-Hill, Inc., 1991.

[2] Lloyd H. Dixon, Jr., Filter Inductor and FlybackTransformer Design for Switching Power Supplies,Unitrode Power Supply Design Seminar ManualSEM-1100, 1996.

[3] Bill Andreycak, Practical Considerations in HighPerformance MOSFET, IGBT and MCT Gate DriveCircuits, Unitrode Application Note U-137, UnitrodeApplications Handbook IC# 1051, 1997.

[4] Bill Andreycak, Practical Considerations in CurrentMode Power Supplies, Unitrode Application NoteU-111, Unitrode Applications Handbook IC# 1051,1997.

[5] Lloyd H. Dixon, Jr., Control Loop Cookbook,Unitrode Power Supply Design Seminar ManualSEM-1100, 1996.

[6] Lloyd H. Dixon, Jr., Closing the Feedback Loop,Unitrode Power Supply Design Seminar ManualSEM-700, 1990.

[7] Philip C. Todd, Snubber Circuits: Theory, Design,and Application, Unitrode Power Supply DesignSeminar Manual SEM-900, 1993.

UNITRODE CORPORATION7 CONTINENTAL BLVD. • MERRIMACK, NH 03054TEL. (603) 424-2410 • FAX (603) 424-3460

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