Semiconductor Components Industries, LLC, 2004 October, 2004 - Rev. 6 1 Publication Order Number: UC3842B/D UC3842B, UC3843B, UC2842B, UC2843B, NCV3843BV High Performance Current Mode Controllers The UC3842B, UC3843B series are high performance fixed frequency current mode controllers. They are specifically designed for Off-Line and DC-DC converter applications offering the designer a cost-effective solution with minimal external components. These integrated circuits feature a trimmed oscillator for precise duty cycle control, a temperature compensated reference, high gain error amplifier, current sensing comparator, and a high current totem pole output ideally suited for driving a power MOSFET. Also included are protective features consisting of input and reference undervoltage lockouts each with hysteresis, cycle-by-cycle current limiting, programmable output deadtime, and a latch for single pulse metering. These devices are available in an 8-pin dual-in-line and surface mount (SOIC-8) plastic package as well as the 14-pin plastic surface mount (SOIC-14). The SOIC-14 package has separate power and ground pins for the totem pole output stage. The UCX842B has UVLO thresholds of 16 V (on) and 10 V (off), ideally suited for off-line converters. The UCX843B is tailored for lower voltage applications having UVLO thresholds of 8.5 V (on) and 7.6 V (off). Features • Trimmed Oscillator for Precise Frequency Control • Oscillator Frequency Guaranteed at 250 kHz • Current Mode Operation to 500 kHz • Automatic Feed Forward Compensation • Latching PWM for Cycle-By-Cycle Current Limiting • Internally Trimmed Reference with Undervoltage Lockout • High Current Totem Pole Output • Undervoltage Lockout with Hysteresis • Low Startup and Operating Current • Pb-Free Packages are Available Figure 1. Simplified Block Diagram 5.0V Reference Latching PWM V CC Undervoltage Lockout Oscillator Error Amplifier 7(12) V C 7(11) Output 6(10) Power Ground 5(8) 3(5) Current Sense Input V ref 8(14) 4(7) 2(3) 1(1) GND 5(9) R T /C T Voltage Feedback Input R R + - V ref Undervoltage Lockout Output Compensation Pin numbers in parenthesis are for the D suffix SOIC-14 package. V CC 14 SOIC-14 D SUFFIX CASE 751A 1 See detailed ordering and shipping information in the package dimensions section on page 16 of this data sheet. ORDERING INFORMATION See general marking information in the device marking section on page 18 of this data sheet. DEVICE MARKING INFORMATION 1 8 PDIP-8 N SUFFIX CASE 626 PIN CONNECTIONS Compensation NC Voltage Feedback NC Current Sense NC R T /C T Compensation Voltage Feedback Current Sense R T /C T V ref V ref NC V CC V C Output GND Power Ground V CC Output GND (Top View) 8 7 6 5 1 2 3 4 1 2 3 4 14 13 12 11 5 6 7 10 9 8 (Top View) SOIC-8 D1 SUFFIX CASE 751 1 8 http://onsemi.com
Transcript
Semiconductor Components Industries, LLC, 2004
October, 2004 − Rev. 61 Publication Order Number:
UC3842B/D
UC3842B, UC3843B,UC2842B, UC2843B,NCV3843BV
High PerformanceCurrent Mode Controllers
The UC3842B, UC3843B series are high performance fixedfrequency current mode controllers. They are specifically designed forOff−Line and DC−DC converter applications offering the designer acost−effective solution with minimal external components. Theseintegrated circuits feature a trimmed oscillator for precise duty cyclecontrol, a temperature compensated reference, high gain erroramplifier, current sensing comparator, and a high current totem poleoutput ideally suited for driving a power MOSFET.
Also included are protective features consisting of input andreference undervoltage lockouts each with hysteresis, cycle−by−cyclecurrent limiting, programmable output deadtime, and a latch for singlepulse metering.
These devices are available in an 8−pin dual−in−line and surfacemount (SOIC−8) plastic package as well as the 14−pin plastic surfacemount (SOIC−14). The SOIC−14 package has separate power andground pins for the totem pole output stage.
The UCX842B has UVLO thresholds of 16 V (on) and 10 V (off),ideally suited for off−line converters. The UCX843B is tailored forlower voltage applications having UVLO thresholds of 8.5 V (on) and7.6 V (off).Features• Trimmed Oscillator for Precise Frequency Control• Oscillator Frequency Guaranteed at 250 kHz• Current Mode Operation to 500 kHz• Automatic Feed Forward Compensation• Latching PWM for Cycle−By−Cycle Current Limiting• Internally Trimmed Reference with Undervoltage Lockout• High Current Totem Pole Output• Undervoltage Lockout with Hysteresis• Low Startup and Operating Current• Pb−Free Packages are Available
Figure 1. Simplified Block Diagram
5.0VReference
LatchingPWM
VCCUndervoltage
Lockout
Oscillator
ErrorAmplifier
7(12)
VC
7(11)
Output
6(10)
PowerGround
5(8)
3(5)
CurrentSenseInput
Vref
8(14)
4(7)
2(3)
1(1)GND 5(9)
RT/CT
VoltageFeedback
Input
R
R
+−
VrefUndervoltage
Lockout
OutputCompensation
Pin numbers in parenthesis are for the D suffix SOIC−14 package.
VCC
14
SOIC−14D SUFFIX
CASE 751A1
See detailed ordering and shipping information in the packagedimensions section on page 16 of this data sheet.
ORDERING INFORMATION
See general marking information in the device markingsection on page 18 of this data sheet.
DEVICE MARKING INFORMATION
1
8
PDIP−8N SUFFIXCASE 626
PIN CONNECTIONS
Compensation
NC
Voltage Feedback
NC
Current Sense
NC
RT/CT
Compensation
Voltage Feedback
Current Sense
RT/CT
Vref
Vref
NC
VCC
VC
Output
GND
Power Ground
VCC
Output
GND
(Top View)
8
7
6
5
1
2
3
4
1
2
3
4
14
13
12
11
5
6
7
10
9
8
(Top View)
SOIC−8D1 SUFFIXCASE 751
1
8
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UC3842B, UC3843B, UC2842B, UC2843B, NCV3843BV
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MAXIMUM RATINGS
Rating Symbol Value Unit
Bias and Driver Voltages (Zero Series Impedance, see also Total Device spec) VCC, VC 30 V
Total Power Supply and Zener Current (ICC + IZ) 30 mA
Output Current, Source or Sink IO 1.0 A
Output Energy (Capacitive Load per Cycle) W 5.0 J
Current Sense and Voltage Feedback Inputs Vin − 0.3 to + 5.5 V
Error Amp Output Sink Current IO 10 mA
Power Dissipation and Thermal CharacteristicsD Suffix, Plastic Package, SOIC−14 Case 751A
Maximum Power Dissipation @ TA = 25°CThermal Resistance, Junction−to−Air
D1 Suffix, Plastic Package, SOIC−8 Case 751Maximum Power Dissipation @ TA = 25°CThermal Resistance, Junction−to−Air
N Suffix, Plastic Package, Case 626Maximum Power Dissipation @ TA = 25°CThermal Resistance, Junction−to−Air
PDRJA
PDRJA
PDRJA
862145
702178
1.25100
mW°C/W
mW°C/W
W°C/W
Operating Junction Temperature TJ +150 °COperating Ambient Temperature
UC3842B, UC3843BUC2842B, UC2843B
UC3842BV, UC3843BVNCV3843BV
TA0 to 70
− 25 to + 85−40 to +105−40 to +125
°C
Storage Temperature Range Tstg − 65 to +150 °CMaximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limitvalues (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,damage may occur and reliability may be affected.
ELECTRICAL CHARACTERISTICS (VCC = 15 V [Note 1], RT = 10 k, CT = 3.3 nF. For typical values TA = 25°C, for min/max valuesTA is the operating ambient temperature range that applies [Note 2], unless otherwise noted.)
UC284XB UC384XB, XBV
Characteristics Symbol Min Typ Max Min Typ Max Unit
REFERENCE SECTION
Reference Output Voltage (IO = 1.0 mA, TJ = 25°C) Vref 4.95 5.0 5.05 4.9 5.0 5.1 V
Line Regulation (VCC = 12 V to 25 V) Regline − 2.0 20 − 2.0 20 mV
Load Regulation (IO = 1.0 mA to 20 mA) Regload − 3.0 25 − 3.0 25 mV
Temperature Stability TS − 0.2 − − 0.2 − mV/°CTotal Output Variation over Line, Load, and Temperature Vref 4.9 − 5.1 4.82 − 5.18 V
Output Noise Voltage (f = 10 Hz to 10 kHz, TJ = 25°C) Vn − 50 − − 50 − V
Long Term Stability (TA = 125°C for 1000 Hours) S − 5.0 − − 5.0 − mV
Output Short Circuit Current ISC − 30 − 85 −180 − 30 − 85 −180 mA
OSCILLATOR SECTION
FrequencyTJ = 25°CTA = Tlow to ThighTJ = 25°C (RT = 6.2 k, CT = 1.0 nF)
fOSC4948225
52−
250
5556275
4948225
52−
250
5556275
kHz
Frequency Change with Voltage (VCC = 12 V to 25 V) fOSC/V − 0.2 1.0 − 0.2 1.0 %
Frequency Change with Temperature, TA = Tlow to Thigh fOSC/T − 1.0 − − 0.5 − %
Oscillator Voltage Swing (Peak−to−Peak) VOSC − 1.6 − − 1.6 − V
Discharge Current (VOSC = 2.0 V)TJ = 25°C, TA = Tlow to Thigh
UC284XB, UC384XBTA = Tlow to Thigh UC384XBV
Idischg7.87.5−
8.3−−
8.88.8−
7.87.67.2
8.3−−
8.88.88.8
mA
1. Adjust VCC above the Startup threshold before setting to 15 V.2. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
Tlow = 0°C for UC3842B, UC3843B; −25°C for UC2842B, UC2843B; −40°C for UC3842BV, UC3843BVThigh = +70°C for UC3842B, UC3843B; +85°C for UC2842B, UC2843B; +105°C for UC3842BV, UC3843BVNCV3843BV: Tlow = −40°C, Thigh = +105°C. Guaranteed by design. NCV prefix is for automotive and other applications requiring site andchange control.
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ELECTRICAL CHARACTERISTICS (VCC = 15 V [Note 3], RT = 10 k, CT = 3.3 nF. For typical values TA = 25°C, for min/max valuesTA is the operating ambient temperature range that applies [Note 4], unless otherwise noted.)
UC284XB UC384XB, XBV
Characteristics Symbol Min Typ Max Min Typ Max Unit
ERROR AMPLIFIER SECTION
Voltage Feedback Input (VO = 2.5 V) VFB 2.45 2.5 2.55 2.42 2.5 2.58 V
Input Bias Current (VFB = 5.0 V) IIB − − 0.1 −1.0 − − 0.1 − 2.0 A
Open Loop Voltage Gain (VO = 2.0 V to 4.0 V) AVOL 65 90 − 65 90 − dB
Output Voltage SwingHigh State (RL = 15 k to ground, VFB = 2.3 V)Low State (RL = 15 k to Vref, VFB = 2.7 V)
UC284XB, UC384XBUC384XBV
VOHVOL
5.0
−−
6.2
0.8−
−
1.1−
5.0
−−
6.2
0.80.8
−
1.11.2
V
CURRENT SENSE SECTION
Current Sense Input Voltage Gain (Notes 5 and 6)UC284XB, UC384XB
UC384XBV
AV2.85
−3.0−
3.15−
2.852.85
3.03.0
3.153.25
V/V
Maximum Current Sense Input Threshold (Note 5)UC284XB, UC384XB
UC384XBV
Vth0.9−
1.0−
1.1−
0.90.85
1.01.0
1.11.1
V
Power Supply Rejection Ratio (VCC = 12 V to 25 V, Note 5) PSRR − 70 − − 70 − dB
Input Bias Current IIB − − 2.0 −10 − − 2.0 −10 A
Propagation Delay (Current Sense Input to Output) tPLH(In/Out) − 150 300 − 150 300 ns
OUTPUT SECTION
Output VoltageLow State (ISink = 20 mA)
(ISink = 200 mA) UC284XB, UC384XBUC384XBV
High State (ISource = 20 mA) UC284XB, UC384XBUC384XBV
(ISource = 200 mA)
VOL
VOH
−−−13−12
0.11.6−
13.5−
13.4
0.42.2−−−−
−−−13
12.912
0.11.61.613.513.513.4
0.42.22.3−−−
V
Output Voltage with UVLO Activated (VCC = 6.0 V, ISink = 1.0 mA) VOL(UVLO) − 0.1 1.1 − 0.1 1.1 V
Output Voltage Rise Time (CL = 1.0 nF, TJ = 25°C) tr − 50 150 − 50 150 ns
Output Voltage Fall Time (CL = 1.0 nF, TJ = 25°C) tf − 50 150 − 50 150 ns
UNDERVOLTAGE LOCKOUT SECTION
Startup Threshold (VCC)UCX842B, BVUCX843B, BV
Vth157.8
168.4
179.0
14.57.8
168.4
17.59.0
V
Minimum Operating Voltage After Turn−On (VCC)UCX842B, BVUCX843B, BV
VCC(min)9.07.0
107.6
118.2
8.57.0
107.6
11.58.2
V
3. Adjust VCC above the Startup threshold before setting to 15 V.4. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
Tlow = 0°C for UC3842B, UC3843B; −25°C for UC2842B, UC2843B; −40°C for UC3842BV, UC3843BVThigh = +70°C for UC3842B, UC3843B; +85°C for UC2842B, UC2843B; +105°C for UC3842BV, UC3843BVNCV3843BV: Tlow = −40°C, Thigh = +125°C. Guaranteed by design. NCV prefix is for automotive and other applications requiring site andchange control.
5. This parameter is measured at the latch trip point with VFB = 0 V.6. Comparator gain is defined as: AV
V Output CompensationV Current Sense Input
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ELECTRICAL CHARACTERISTICS (VCC = 15 V [Note 7], RT = 10 k, CT = 3.3 nF, for typical values TA = 25°C, for min/max valuesTA is the operating ambient temperature range that applies [Note 8], unless otherwise noted.)
UC284XB UC384XB, BV
Characteristics Symbol Min Typ Max Min Typ Max Unit
Power Supply CurrentStartup (VCC = 6.5 V for UCX843B, Startup VCC 14 V for UCX842B, BV)(Note 7)
ICC + IC−
−
0.3
12
0.5
17
−
−
0.3
12
0.5
17
mA
Power Supply Zener Voltage (ICC = 25 mA) VZ 30 36 − 30 36 − V
7. Adjust VCC above the Startup threshold before setting to 15 V.8. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
Tlow = 0°C for UC3842B, UC3843B; −25°C for UC2842B, UC2843B; −40°C for UC3842BV, UC3843BVThigh = +70°C for UC3842B, UC3843B; +85°C for UC2842B, UC2843B; +105°C for UC3842BV, UC3843BVNCV3843BV: Tlow = −40°C, Thigh = +125°C. Guaranteed by design. NCV prefix is for automotive and other applications requiring site andchange control.
0.8
2.0
5.0
8.0
20
50
80
RT,
TIM
ING
RE
SIS
TOR
(k
)Ω
1.0 M500 k200 k100 k50 k20 k10 k
fOSC, OSCILLATOR FREQUENCY (kHz)
VCC = 15 VTA = 25°C
Figure 2. Timing Resistorversus Oscillator Frequency
Figure 3. Output Deadtimeversus Oscillator Frequency
1.0 M500 k200 k100 k50 k20 k10 k
fOSC, OSCILLATOR FREQUENCY (kHz)
1.0
2.0
5.0
10
20
50
100
% D
T, P
ER
CE
NT
OU
TP
UT
DE
AD
TIM
E
1
2
Figure 4. Oscillator Discharge Currentversus Temperature
Figure 5. Maximum Output Duty Cycleversus Timing Resistor
1 1 Compensation This pin is the Error Amplifier output and is made available for loop compensation.
2 3 VoltageFeedback
This is the inverting input of the Error Amplifier. It is normally connected to the switchingpower supply output through a resistor divider.
3 5 CurrentSense
A voltage proportional to inductor current is connected to this input. The PWM uses thisinformation to terminate the output switch conduction.
4 7 RT/CT The Oscillator frequency and maximum Output duty cycle are programmed byconnecting resistor RT to Vref and capacitor CT to ground. Operation to 500 kHzis possible.
5 GND This pin is the combined control circuitry and power ground.
6 10 Output This output directly drives the gate of a power MOSFET. Peak currents up to 1.0 A aresourced and sunk by this pin.
7 12 VCC This pin is the positive supply of the control IC.
8 14 Vref This is the reference output. It provides charging current for capacitor CT through resistor RT.
8 PowerGround
This pin is a separate power ground return that is connected back to the power source. It isused to reduce the effects of switching transient noise on the control circuitry.
11 VC The Output high state (VOH) is set by the voltage applied to this pin. With a separatepower source connection, it can reduce the effects of switching transient noise on thecontrol circuitry.
9 GND This pin is the control circuitry ground return and is connected back to the powersource ground.
2,4,6,13 NC No connection. These pins are not internally connected.
UC3842B, UC3843B, UC2842B, UC2843B, NCV3843BV
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OPERATING DESCRIPTION
The UC3842B, UC3843B series are high performance,fixed frequency, current mode controllers. They arespecifically designed for Off−Line and DC−to−DCconverter applications offering the designer a cost−effectivesolution with minimal external components. Arepresentative block diagram is shown in Figure 18.
OscillatorThe oscillator frequency is programmed by the values
selected for the timing components RT and CT. Capacitor CTis charged from the 5.0 V reference through resistor RT toapproximately 2.8 V and discharged to 1.2 V by an internalcurrent sink. During the discharge of CT, the oscillatorgenerates an internal blanking pulse that holds the centerinput of the NOR gate high. This causes the Output to be ina low state, thus producing a controlled amount of outputdeadtime. Figure 2 shows RT versus Oscillator Frequencyand Figure 3, Output Deadtime versus Frequency, both forgiven values of CT. Note that many values of RT and CT willgive the same oscillator frequency but only one combinationwill yield a specific output deadtime at a given frequency.The oscillator thresholds are temperature compensated towithin ±6% at 50 kHz. Also because of industry trendsmoving the UC384X into higher and higher frequencyapplications, the UC384XB is guaranteed to within ±10% at250 kHz. These internal circuit refinements minimizevariations of oscillator frequency and maximum output dutycycle. The results are shown in Figures 4 and 5.
In many noise−sensitive applications it may be desirableto frequency−lock the converter to an external system clock.This can be accomplished by applying a clock signal to thecircuit shown in Figure 21. For reliable locking, thefree−running oscillator frequency should be set about 10%less than the clock frequency. A method for multi−unitsynchronization is shown in Figure 22. By tailoring theclock waveform, accurate Output duty cycle clamping canbe achieved.
Error AmplifierA fully compensated Error Amplifier with access to the
inverting input and output is provided. It features a typicalDC voltage gain of 90 dB, and a unity gain bandwidth of1.0 MHz with 57 degrees of phase margin (Figure 8). Thenon−inverting input is internally biased at 2.5 V and is notpinned out. The converter output voltage is typically divideddown and monitored by the inverting input. The maximuminput bias current is −2.0 A which can cause an outputvoltage error that is equal to the product of the input biascurrent and the equivalent input divider source resistance.
The Error Amp Output (Pin 1) is provided for externalloop compensation (Figure 32). The output voltage is offsetby two diode drops (≈1.4 V) and divided by three before itconnects to the non−inverting input of the Current SenseComparator. This guarantees that no drive pulses appear atthe Output (Pin 6) when pin 1 is at its lowest state (VOL).
This occurs when the power supply is operating and the loadis removed, or at the beginning of a soft−start interval(Figures 24, 25). The Error Amp minimum feedbackresistance is limited by the amplifier’s source current(0.5 mA) and the required output voltage (VOH) to reach thecomparator’s 1.0 V clamp level:
Rf(min) ≈3.0 (1.0 V) + 1.4 V
0.5 mA= 8800
Current Sense Comparator and PWM LatchThe UC3842B, UC3843B operate as a current mode
controller, whereby output switch conduction is initiated bythe oscillator and terminated when the peak inductor currentreaches the threshold level established by the ErrorAmplifier Output/Compensation (Pin 1). Thus the errorsignal controls the peak inductor current on acycle−by−cycle basis. The Current Sense Comparator PWMLatch configuration used ensures that only a single pulseappears at the Output during any given oscillator cycle. Theinductor current is converted to a voltage by inserting theground−referenced sense resistor RS in series with thesource of output switch Q1. This voltage is monitored by theCurrent Sense Input (Pin 3) and compared to a level derivedfrom the Error Amp Output. The peak inductor current undernormal operating conditions is controlled by the voltage atpin 1 where:
Ipk =V(Pin 1) − 1.4 V
3 RS
Abnormal operating conditions occur when the powersupply output is overloaded or if output voltage sensing islost. Under these conditions, the Current Sense Comparatorthreshold will be internally clamped to 1.0 V. Therefore themaximum peak switch current is:
Ipk(max) =1.0 VRS
When designing a high power switching regulator itbecomes desirable to reduce the internal clamp voltage inorder to keep the power dissipation of RS to a reasonablelevel. A simple method to adjust this voltage is shown inFigure 23. The two external diodes are used to compensatethe internal diodes, yielding a constant clamp voltage overtemperature. Erratic operation due to noise pickup can resultif there is an excessive reduction of the Ipk(max) clampvoltage.
A narrow spike on the leading edge of the currentwaveform can usually be observed and may cause the powersupply to exhibit an instability when the output is lightlyloaded. This spike is due to the power transformerinterwinding capacitance and output rectifier recovery time.The addition of an RC filter on the Current Sense Input witha time constant that approximates the spike duration willusually eliminate the instability (refer to Figure 27).
UC3842B, UC3843B, UC2842B, UC2843B, NCV3843BV
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+−
ReferenceRegulator
VCCUVLO
+− Vref
UVLO3.6V
36V
S
RQ
InternalBias
+ 1.0mA
Oscillator
2.5V
R
R
R
2R
ErrorAmplifier
VoltageFeedback
Input
Output/Compensation Current Sense
Comparator
1.0V
VCC 7(12)
GND 5(9)
VC
7(11)
Output
6(10)
Power Ground
5(8)
Current Sense Input
3(5)RS
Q1
VCC Vin
1(1)
2(3)
4(7)
8(14)
RT
CT
Vref
= Sink Only Positive True LogicPin numbers adjacent to terminals are for the 8−pin dual−in−line package.Pin numbers in parenthesis are for the D suffix SOIC−14 package.
Figure 18. Representative Block Diagram
Figure 19. Timing Diagram
Large RT/Small CTSmall RT/Large CT
PWMLatch
(SeeText)
Capacitor CT
LatchSet" Input
Output/Compensation
Current SenseInput
LatchReset" Input
Output
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Undervoltage LockoutTwo undervoltage lockout comparators have been
incorporated to guarantee that the IC is fully functionalbefore the output stage is enabled. The positive powersupply terminal (VCC) and the reference output (Vref) areeach monitored by separate comparators. Each has built−inhysteresis to prevent erratic output behavior as theirrespective thresholds are crossed. The VCC comparatorupper and lower thresholds are 16 V/10 V for the UCX842B,and 8.4 V/7.6 V for the UCX843B. The Vref comparatorupper and lower thresholds are 3.6 V/3.4 V. The largehysteresis and low startup current of the UCX842B makesit ideally suited in off−line converter applications whereefficient bootstrap startup techniques are required(Figure 34). The UCX843B is intended for lower voltageDC−to−DC converter applications. A 36 V Zener isconnected as a shunt regulator from VCC to ground. Itspurpose is to protect the IC from excessive voltage that canoccur during system startup. The minimum operatingvoltage (VCC) for the UCX842B is 11 V and 8.2 V for theUCX843B.
These devices contain a single totem pole output stage thatwas specifically designed for direct drive of powerMOSFETs. It is capable of up to ±1.0 A peak drive currentand has a typical rise and fall time of 50 ns with a 1.0 nF load.Additional internal circuitry has been added to keep theOutput in a sinking mode whenever an undervoltage lockoutis active. This characteristic eliminates the need for anexternal pull−down resistor.
The SOIC−14 surface mount package provides separatepins for VC (output supply) and Power Ground. Properimplementation will significantly reduce the level ofswitching transient noise imposed on the control circuitry.This becomes particularly useful when reducing the Ipk(max)clamp level. The separate VC supply input allows thedesigner added flexibility in tailoring the drive voltageindependent of VCC. A Zener clamp is typically connectedto this input when driving power MOSFETs in systemswhere VCC is greater than 20 V. Figure 26 shows properpower and control ground connections in a current−sensingpower MOSFET application.
ReferenceThe 5.0 V bandgap reference is trimmed to ±1.0%
tolerance at TJ = 25°C on the UC284XB, and ±2.0% on theUC384XB. Its primary purpose is to supply charging currentto the oscillator timing capacitor. The reference has short−circuit protection and is capable of providing in excess of20 mA for powering additional control system circuitry.
Design ConsiderationsDo not attempt to construct the converter on
wire−wrap or plug−in prototype boards. High frequencycircuit layout techniques are imperative to preventpulse−width jitter. This is usually caused by excessive noisepick−up imposed on the Current Sense or Voltage Feedbackinputs. Noise immunity can be improved by lowering circuitimpedances at these points. The printed circuit layout shouldcontain a ground plane with low−current signal andhigh−current switch and output grounds returning onseparate paths back to the input filter capacitor. Ceramicbypass capacitors (0.1 F) connected directly to VCC, VC,and Vref may be required depending upon circuit layout.This provides a low impedance path for filtering the highfrequency noise. All high current loops should be kept asshort as possible using heavy copper runs to minimizeradiated EMI. The Error Amp compensation circuitry andthe converter output voltage divider should be located closeto the IC and as far as possible from the power switch andother noise−generating components.
Current mode converters can exhibit subharmonicoscillations when operating at a duty cycle greater than 50%with continuous inductor current. This instability isindependent of the regulator’s closed loop characteristicsand is caused by the simultaneous operating conditions offixed frequency and peak current detecting. Figure 20Ashows the phenomenon graphically. At t0, switchconduction begins, causing the inductor current to rise at aslope of m1. This slope is a function of the input voltagedivided by the inductance. At t1, the Current Sense Inputreaches the threshold established by the control voltage.This causes the switch to turn off and the current to decay ata slope of m2, until the next oscillator cycle. The unstablecondition can be shown if a perturbation is added to thecontrol voltage, resulting in a small I (dashed line). Witha fixed oscillator period, the current decay time is reduced,and the minimum current at switch turn−on (t2) is increasedby I + I m2/m1. The minimum current at the next cycle(t3) decreases to (I + I m2/m1) (m2/m1). This perturbationis multiplied by m2/m1 on each succeeding cycle, alternatelyincreasing and decreasing the inductor current at switchturn−on. Several oscillator cycles may be required beforethe inductor current reaches zero causing the process tocommence again. If m2/m1 is greater than 1, the converterwill be unstable. Figure 20B shows that by adding anartificial ramp that is synchronized with the PWM clock tothe control voltage, the I perturbation will decrease to zeroon succeeding cycles. This compensating ramp (m3) musthave a slope equal to or slightly greater than m2/2 forstability. With m2/2 slope compensation, the averageinductor current follows the control voltage, yielding truecurrent mode operation. The compensating ramp can bederived from the oscillator and added to either the VoltageFeedback or Current Sense inputs (Figure 33).
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Figure 20. Continuous Current Waveforms
2(3) EA
Bias
+
Osc
R
R
R
2R
5(9)
1(1)
4(7)
8(14)
RT
CT
Vref
0.01
The diode clamp is required if the Sync amplitude is large enough to cause the bottomside of CT to go more than 300 mV below ground.
Virtually lossless current sensing can be achieved with the implementation of aSENSEFET power switch. For proper operation during over−current conditions, areduction of the Ipk(max) clamp level must be implemented. Refer to Figures 23 and 25.
VPin 5 RS Ipk rDS(on)rDM(on) RS
If: SENSEFET = MTP10N10MRS = 200
Then : VPin5 0.075Ipk
(12)
Figure 26. Current Sensing Power MOSFET
+−
5.0V Ref
+−
S
RQ
7(11)
6(10)
5(8)
3(5)
RS
Q1
VCC Vin
C
R
The addition of the RC filter will eliminate instability caused by the leadingedge spike on the current waveform.
7(12)
Comp/Latch
Figure 27. Current Waveform Spike Suppression
UC3842B, UC3843B, UC2842B, UC2843B, NCV3843BV
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Figure 28. MOSFET Parasitic Oscillations
6(10)
5(8)
3(5) RS
Q1
Vin
C1
Base ChargeRemoval
The totem pole output can furnish negative base current for enhancedtransistor turn−off, with the addition of capacitor C1.
S
R
5.0V Ref
Q
7(11)
6(10)
5(8)
3(5)
RS
Q1
VCC
IB
+
−
0
Vin
IsolationBoundary
VGS Waveforms
+
−0
+
−
0
50% DC 25% DC
Ipk V(Pin1) 1.4
3RSNS
Np
Comp/Latch
7(12)
R
C NSNP
+−
+−
Bias
+
Osc
R
R
R
2R
EA
5(9)
1(1)
2(3)
4(7)
8(14)
The MCR101 SCR must be selected for a holding of < 0.5 mA @ TA(min). The simple twotransistor circuit can be used in place of the SCR as shown. All resistors are 10 k.
MCR101
2N3905
2N3903
1.0 mA
S
R
5.0V Ref
Q
7(11)
6(10)
5(8)
3(5) RS
Q1
VCC Vin
Series gate resistor Rg will damp any high frequency parasitic oscillationscaused by the MOSFET input capacitance and any series wiring inductance inthe gate−source circuit.
The buffered oscillator ramp can be resistively summed with either the voltagefeedback or current sense inputs to provide slope compensation.
m− 3.0m
−m
RfCf
Ri
Rd
From VORSlope
MPS3904
5(9)
Comp/Latch
Figure 32. Error Amplifier Compensation
+
R
2R1.0mA
EA
2(3)
5(9)
2.5V
1(1)
RfCfRd
Ri
From VO
Error Amp compensation circuit for stabilizing any current mode topology except for boost and flybackconverters operating with continuous inductor current.
Rf ≥ 8.8 k
+
R
2R1.0mA
EA
2(3)
5(9)
2.5V
1(1)
RfCfRd
Rp
From VO
Error Amp compensation circuit for stabilizing current mode boost and flybacktopologies operating with continuous inductor current.
− 15 H at 5.0 A, Coilcraft Z7156− 25 H at 5.0 A, Coilcraft Z7157
1N5819
Test Conditions Results
Line Regulation: 5.0 V±12V
Vin = 95 to 130 Vac = 50 mV or ± 0.5% = 24 mV or ± 0.1%
Load Regulation: 5.0 V
±12V
Vin = 115 Vac, Iout = 1.0 A to 4.0 A
Vin = 115 Vac, Iout = 100 mA to 300 mA
= 300 mV or ± 3.0%
= 60 mV or ± 0.25%
Output Ripple: 5.0 V±12V
Vin = 115 Vac 40 mVpp80 mVpp
Efficiency Vin = 115 Vac 70%
All outputs are at nominal load currents, unless otherwise noted
UC3842B, UC3843B, UC2842B, UC2843B, NCV3843BV
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ORDERING INFORMATION
DeviceOperating
Temperature Range Package Shipping †
UC2842BD SOIC−14 55 Units/Rail
UC2842BD1 SOIC−8 98 Units/Rail
UC2842BD1R2TA = −25° to +85°C
SOIC−8 2500 Tape & Reel
UC2842BD1R2GTA = −25° to +85°C
SOIC−8(Pb−Free)
2500 Tape & Reel
UC2842BN PDIP−8 1000 Units/Rail
UC3842BN PDIP−8 1000 Units/Rail
UC3842BNG PDIP−8(Pb−Free)
1000 Units/Rail
UC3842BD SOIC−14 55 Units/Rail
UC3842BDR2 SOIC−14 2500 Tape & Reel
UC3842BD1 TA = 0° to +70°C SOIC−8 98 Units/Rail
UC3842BD1R2 SOIC−8 2500 Tape & Reel
UC3842BD1R2G SOIC−8(Pb−Free)
2500 Tape & Reel
UC3842BDR2G SOIC−14(Pb−Free) 2500 Tape & Reel
UC3842BVDR2 SOIC−14 2500 Tape & Reel
UC3842BVD1 SOIC−8 98 Units/Rail
UC3842BVD1R2 TA = −40° to +105°C SOIC−8 2500 Tape & Reel
UC3842BVD1R2G SOIC−8(Pb−Free)
2500 Tape & Reel
UC2843BD SOIC−14 55 Units/Rail
UC2843BDR2 SOIC−14 2500 Tape & Reel
UC2843BDR2G SOIC−14(Pb−Free)
2500 Tape & Reel
UC2843BD1 SOIC−8 98 Units/Rail
UC2843BD1R2 TA = −25° to +85°C SOIC−8 2500 Tape & Reel
UC2843BD1R2GSOIC−8
(Pb−Free) 2500 Tape & Reel
UC2843BN PDIP−8 1000 Units/Rail
UC2843BNGPDIP−8
(Pb−Free) 1000 Units/Rail
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel PackagingSpecifications Brochure, BRD8011/D.
UC3842B, UC3843B, UC2842B, UC2843B, NCV3843BV
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ORDERING INFORMATION
DeviceOperating
Temperature Range Package Shipping †
UC3843BD SOIC−14 55 Units/Rail
UC3843BDR2 SOIC−14 2500 Tape & Reel
UC3843BD1 SOIC−8 98 Units/Rail
UC3843BD1GSOIC−8
(Pb−Free) 98 Units/Rail
UC3843BD1R2 SOIC−8 2500 Tape & Reel
UC3843BN TA = 0° to +70°C PDIP−8 1000 Units/Rail
UC3843BD1R2G SOIC−8(Pb−Free)
2500 Tape & Reel
UC3843BDR2G SOIC−14(Pb−Free)
2500 Tape & Reel
UC3843BNG PDIP−8(Pb−Free) 1000 Units/Rail
UC3843BVD SOIC−14 55 Units/Rail
UC3843BVDR2 SOIC−14 2500 Tape & Reel
UC3843BVDR2G SOIC−14(Pb−Free)
2500 Tape & Reel
UC3843BVD1 TA = −40° to +105°C SOIC−8 98 Units/Rail
UC3843BVD1R2
A
SOIC−8 2500 Tape & Reel
UC3843BVD1R2GSOIC−8
(Pb−Free) 2500 Tape & Reel
UC3843BVN PDIP−8 1000 Units/Rail
NCV3843BVDR2 SOIC−14 2500 Tape & Reel
NCV3843BVDR2G TA = −40° to +125°C SOIC−14(Pb−Free)
2500 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel PackagingSpecifications Brochure, BRD8011/D.
UC3842B, UC3843B, UC2842B, UC2843B, NCV3843BV
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x = 2 or 3A = Assembly LocationWL, L = Wafer LotYY, Y = YearWW, W = Work Week
SOIC−14D SUFFIX
CASE 751A
MARKING DIAGRAMS
UC384xBDAWLYWW
14
1
UC384xBN FAWL YYWW
PDIP−8N SUFFIXCASE 626
1
8
SOIC−8D1 SUFFIXCASE 751
UC384xBVDAWLYWW
14
1
UC3843BVN AWL YYWW
1
8
UC284xBDAWLYWW
14
1
UC284xBN AWL YYWW
1
8
*This marking diagram also applies to NCV3843BV.
*
384xBALYW
1
8
384xBALYWV
1
8
284xBALYW
1
8
UC3842B, UC3843B, UC2842B, UC2843B, NCV3843BV
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PACKAGE DIMENSIONS
PDIP−8N SUFFIX
CASE 626−05ISSUE L
NOTES:1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).3. DIMENSIONING AND TOLERANCING PER ANSI
L 7.62 BSC 0.300 BSCM −−− 10 −−− 10 N 0.76 1.01 0.030 0.040
UC3842B, UC3843B, UC2842B, UC2843B, NCV3843BV
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SOIC−8 NBD1 SUFFIX
CASE 751−07ISSUE AC
1.520.060
7.00.275
0.60.024
1.2700.050
4.00.155
mminches
SCALE 6:1
*For additional information on our Pb−Free strategy and solderingdetails, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
SEATINGPLANE
1
4
58
N
J
X 45
K
NOTES:1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.127 (0.005) TOTALIN EXCESS OF THE D DIMENSION ATMAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEWSTANDARD IS 751−07.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further noticeto any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liabilityarising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. Alloperating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rightsnor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicationsintended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. ShouldBuyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or deathassociated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an EqualOpportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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UC3842B/D
SENSEFET is a trademark of Semiconductor Components Industries, LLC.
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