UCS2113 Data Sheet - Microchip Technologyww1.microchip.com/downloads/en/DeviceDoc/20005680A.pdf ·...

UCS2113USB Dual-Port Power Switch and Current Monitor

Features• Dual-Port Power Switches:

- 2.9V to 5.5V source voltage range- 3.0A continuous current per VBUS port with

40 m On resistance per switch- Independent port power switch enable pins- DUAL fault ALERT# active drain output pins- Constant Current or Trip mode current

limiting behaviors- Undervoltage and overvoltage lockout- Back-drive, back-voltage protection- Auto-recovery fault handling with low test

current- BOOST# logic output to increase DC-DC

converter output under large load conditions• SMBus 2.0/I2C Mode Features:

- Eight programmable current limits assignable to each power switch

- Other SMBus addresses available upon request

- Block read and block write• Self-Contained Current Monitoring (No External

Sense Resistor Required)• Fully Programmable Per-Port Charge Rationing

and Behaviors• Configurable Per-Port BC1.2 VBUS Discharge

Function• Wide Operating Temperature Range:

- -40°C to +105°C• UL Recognized and EN/IEC 60950-1 (CB)

Certified

DescriptionThe UCS2113 is a dual USB port power switchconfiguration which can provide 3.0A continuouscurrent (3.4A maximum) per VBUS port with precisionovercurrent limiting (OCL), port power switch enables,auto-recovery fault handling, undervoltage andovervoltage lockout, back-drive protection andback-voltage protection, and thermal protection.

The UCS2113 is well suited for both stand-alone andapplications having SMBus/I2C communications.

For applications with SMBus, the UCS2113 providesper-port current monitoring and eight programmablecurrent limits per switch, ranging from 0.53A to 3.0Acontinuous current (3.4A maximum). Per-port chargerationing is also provided ranging from 3.8 mAh to246.3 Ah.

In stand-alone mode, the UCS2113 provides eightcurrent limits for both switches, ranging from0.53A + 0.53A to 3A + 3A total continuous current(see Table 1-1).

Both power switches include an independent VBUSdischarge function and constant current mode currentlimiting for BC1.2 applications.

The UCS2113 is available in a 4x4 mm 20-pin QFNpackage.

Package TypeA

LER

T#2

2

BOOST#

VBUS1

PWR_EN1 PWR_EN2

GND

VS

COMM_ILIM

VS

VD

D VS

VBUS2

ALE

RT#

1

GN

D

SM

DAT

A

SM

CLK

GNDEP

20

1

19 18 17

3

4

14

13

12

11

6 7 8 9

21

5

10

15

16

VBUS1

VS

VBUS2

UCS21134 x 4 QFN*

* Includes Exposed Thermal Pad (EP); see Table 3-1.

2016 Microchip Technology Inc. DS20005680A-page 1

UCS2113

Block Diagram

Charger Control,

Measurement, OCL

Inte

rface

Log

ic

SMCLKSMDATA

PWR_EN2

PowerSwitch 2

Temp

ALERT#2

VBUS

GND

COMM_ILIM

PowerSwitch 1

VBUSVS

UVLO, OVLO

PWR_EN1

BOOST#

ALERT#1

VBUSdischarge

VDD

VS

DS20005680A-page 2 2016 Microchip Technology Inc.

UCS2113

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings †Voltage on VDD, VS, and VBUS pins ...................................................................................................................-0.3 to 6VPull-Up Voltage (VPULLUP) ..................................................................................................................... -0.3 to VDD + 0.3Port Power Switch Current ..................................................................................................................... Internally limitedVoltage on any Other Pin to Ground ...................................................................................................-0.3 to VDD + 0.3VCurrent on any Other Pin ..................................................................................................................................... ±10 mAPackage Power Dissipation ........................................................................................................................ See Table 1-1Operating Ambient Temperature Range................................................................................................. -40°C to +105°CStorage Temperature Range .................................................................................................................. -55°C to +150°C

† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This isa stress rating only and functional operation of the device at those or any other conditions above those indicated in theoperation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods mayaffect device reliability.

TABLE 1-1: POWER DISSIPATION SUMMARY

Board Package JC JADerating Factor

Above +25°CTA < +25°C

Power RatingTA = +70°C

Power RatingTA = +85°C

Power Rating

High K (Note)

20-pin QFN 4x4 mm

6 °C/W 41 °C/W 24.4 mW/°C 2193 mW 1095 mW 729 mW

Low K(Note)

20-pin QFN 4x4 mm

6 °C/W 60 °C/W 16.67 mW/°C 1498 mW 748 mW 498 mW

Note: A High-K board uses a thermal via design with the thermal landing soldered to the PCB ground plane with0.3 mm (12 mil) diameter vias in a 3x3 matrix (9 total) at 0.5 mm (20 mil) pitch. The board is multilayer with1-ounce internal power and ground planes and 2-ounce copper traces on top and bottom. A Low-K boardis a two-layer board without thermal via design with 2-ounce copper traces on the top and bottom.

TABLE 1-2: ELECTRICAL SPECIFICATIONSElectrical Characteristics: Unless otherwise specified, VDD = 4.5V to 5.5V, VS = 2.9V to 5.5V, VPULLUP = 3V to 5.5V, TA = -40°C to 105°C. All typical values at VDD = VS = 5V, TA = 27°C.

Characteristic Symbol Min. Typ. Max. Unit Conditions

Power and Interrupts - DC Supply Voltage VDD 4.5 5 5.5 V

Supply Current in Active (IDD_ACT + IS1_ACT + IS2_ACT)

IACTIVE — 700 — µA Average current IBUS = 0 mA

Supply Current in Sleep (IDD_SLEEP + IS1_SLEEP + IS2_SLEEP)

ISLEEP — 6 20 µA Average current VPULLUP VDD

Power-On ResetVDD Low Threshold VDD_TH — 4 4.3 V VDD voltage increasing (Note 1)VDD Low Hysteresis VDD_TH_HYST — 500 600 mV VDD voltage decreasing (Note 1)Note 1: This parameter is characterized, not 100% tested.

2: This parameter is ensured by design and not 100% tested.3: The current measurement full scale range maximum value is 3.4A. However, the UCS2113 cannot report values above

ILIM (if IBUS_R2MIN ILIM) or above IBUS_R2MIN (if IBUS_R2MIN > ILIM and ILIM 1.6A).


UCS2113

I/O Pins - SMCLK, SMDATA, PWR_EN, ALERT#, BOOST# - DC ParametersOutput Low Voltage VOL — — 0.4 V ISINK_IO = 8 mA

SMDATA, ALERT#, BOOST# Input High Voltage VIH 2.0 — — V PWR_EN, SMDATA, SMCLKInput Low Voltage VIL — — 0.8 V PWR_EN, SMDATA, SMCLKLeakage Current ILEAK — — ±5 µA Powered or unpowered

VPULLUP VDDTA < 85°C (Note 1)

Interrupt Pins - AC ParametersALERT# Pin Blanking Time tBLANK — 25 — ms Blanking time, coming out of

resetALERT# Pin Interrupt Masking Time

tMASK — 5 — ms

BOOST# Pin Minimum Assertion Time

tBOOST_MAT — 1 — s

BOOST# Pin Assertion Current

IBOOST — 1.9 — A

SMBus/I2C TimingInput Capacitance CIN — 5 — pFClock Frequency fSMB 10 — 400 kHzSpike Suppression tSP — — 50 nsBus Free Time Stop to Start tBUF 1.3 — — µsStart Setup Time tSU:STA 0.6 — — µsStart Hold Time tHD:STA 0.6 — — µsStop Setup Time tSU:STO 0.6 — — µsData Hold Time tHD:DAT 0 — — µs When transmitting to the masterData Hold Time tHD:DAT 0.3 — — µs When receiving from the masterData Setup Time tSU:DAT 0.6 — — µsClock Low Period tLOW 1.3 — — µsClock High Period tHIGH 0.6 — — µsClock/Data Fall Time tFALL — — 300 ns Min. = 20+0.1CLOAD ns

(Note 1)Clock/Data Rise Time tRISE — — 300 ns Min. = 20+0.1CLOAD ns

(Note 1)Capacitive Load CLOAD — — 400 pF Per bus line (Note 1)Timeout tTIMEOUT 25 — 35 ms Disabled by default (Note 1)Idle Reset tIDLE_RESET 350 — — µs Disabled by default (Note 1)

TABLE 1-2: ELECTRICAL SPECIFICATIONS (CONTINUED)Electrical Characteristics: Unless otherwise specified, VDD = 4.5V to 5.5V, VS = 2.9V to 5.5V, VPULLUP = 3V to 5.5V, TA = -40°C to 105°C. All typical values at VDD = VS = 5V, TA = 27°C.


Note 1: This parameter is characterized, not 100% tested.2: This parameter is ensured by design and not 100% tested.3: The current measurement full scale range maximum value is 3.4A. However, the UCS2113 cannot report values above



UCS2113

Port Power SwitchPort Power Switch - DC ParameterOvervoltage Lockout VS_OV — 6 — V Note 2VS Low Threshold VS_UVLO — 2.5 — V Note 2VS Low Hysteresis VS_UVLO_HYST — 100 — mV Note 2On Resistance RON_PSW — 40 — m 4.75V < VS < 5.25VVS Leakage Current ILEAK_VS — — 5 µA Sleep state into VS pin on one

channel (Note 1)Back-Voltage Protection Threshold

VBV_TH — 150 — mV VBUS > VSVS > VS_UVLO

Leakage Current ILKG_1 — 0 3 µA VDD < VDD_TH,Leakage current from VBUS pins to the VDD and the VS pins (Note 1)

ILKG_2 — 0 2 µA VDD > VDD_TH,Leakage current from VBUS pins to the VS pins, when the power switch is open

Selectable Current Limits ILIM1 — 530 — mA ILIM Resistor = 0 or 47 k(530 mA setting)

ILIM2 — 960 — mA ILIM Resistor = 10 k or 56 k(960 mA setting)





ILIM7 2500 2670 2900 mA ILIM Resistor = 27 k or 150 k(2670 mA setting)

ILIM8 3000 3200 3400 mA ILIM Resistor = 33 k or VDD(3200 mA setting)

Pin Wake Time tPIN_WAKE — 3 — msSMBus Wake Time tSMB_WAKE — 4 — msIdle Sleep Time tIDLE_SLEEP — 200 — msFirst Thermal Shutdown Stage Threshold

TTSD_LOW — 120 — °C Die Temperature at which the power switch will open if it is in constant current mode

First Thermal Shutdown Stage Hysteresis

TTSD_LOW_HYST — 10 — °C Hysteresis for TTSD_LOW func-tionality. Temperature must drop by this value before any of the power switches can be closed.






UCS2113

Second Thermal Shutdown Stage Threshold

TTSD_HIGH — 135 — °C Die Temperature at which both power switches will open

Second Thermal Shutdown Stage Hysteresis

TTSD_HIGH_HYST — 25 — °C Hysteresis for TTSD_HIGH functionality. Temperature must drop by this value before any of the power switches can be closed.

Auto-Recovery Test Current ITEST — 190 — mA Portable device attached, VBUS= 0 V, Die temp < TTSD

Auto-Recovery Test Voltage VTEST — 750 — mV Portable device attached, VBUS = 0 V before application, Die temp < TTSDProgrammable, 250 - 1000 mV, default listed

Discharge Impedance RDISCHARGE — 100 — Port Power Switch - AC ParametersTurn-On Delay tON_PSW — 0.9 — ms PWR_EN active toggle to

switch on time, VBUS discharge not active

Turn-Off Time tOFF_PSW_INA — 0.75 — ms PWR_EN inactive toggle to switch off timeCBUS = 120 µF

Turn-Off Time tOFF_PSW_ERR — 1 — ms Over-current Error, VBUS Min Error, or Discharge Error to switch off CBUS = 120 µF

Turn-Off Time tOFF_PSW_ERR1 — 100 — ns TSD or Back-drive Error to switch offCBUS = 120 µF

VBUS Output Rise Time tR_BUS — 1.1 — ms Measured from 10% to 90% of VBUS, CLOAD = 220 µFILIM = 1.0A

Soft Turn-On Rate IBUS/t — 100 — mA/µsTemperature Update Time tDC_TEMP — 200 — msShort-Circuit Response Time tSHORT_LIM — 1.5 — µs Time from detection of short to

current limit applied.No CBUS applied

Short-Circuit Detection Time tSHORT — 6 — ms Time from detection of short to port power switch disconnect and ALERT# pin assertion

Latched Mode Cycle Time tUL — 7 — ms From PWR_EN edge transition from inactive to active to begin error recovery






UCS2113

Auto-Recovery Mode Cycle Time

tCYCLE — 25 — ms Time delay before error condition check.Programmable 15-50 ms, default listed

Auto-Recovery Delay tTST — 20 — ms Portable device attached, VBUS must be > VTEST after this time.Programmable 10-25 ms, default listed

Discharge Time tDISCHARGE — 200 — ms Amount of time discharge resistor applied.Programmable 100-400 ms, default listed

Port Power Switch Operation With Trip Mode Current Limiting Region 2 Current Keep-Out

IBUS_R2MIN_1 — — 0.1 A Note 2

Minimum VBUS Allowed at Output

VBUS_MIN_1 2.0 — — V Note 2

Port Power Switch Operation With Constant Current Limiting (Variable Slope)Region 2 Current Keep-Out

IBUS_R2MIN — — 2.13 A Note 2

Minimum VBUS Allowed at Output

VBUS_MIN 2.0 — — V Note 2

Current Measurement - DCCurrent Measurement Range IBUS_M 0 — 3400 mA Range (Note 2 and Note 3)Reported Current Measurement Resolution

IBUS_M — 13.3 — mA 1 LSB

Current Measurement Accuracy

— ±2 — % 200 mA < IBUS < ILIM— ±2 — LSB IBUS < 200 mA

Current Measurement - AC Sampling Rate — — 1.1 — ms Note 2Conversion Time Both Channels

tCONV — 2.2 — ms All registers updated in digital(Note 2)

Charge Rationing - DCAccumulated Current Measurement Accuracy

— — ±4.5 — %

Charge Rationing - AC Current Measurement Update Time

tPCYCLE — 1 — s






UCS2113

FIGURE 1-1: SMBus Timing.

SMDATA

SMCLK

TBUF

P S S - Start Condition P - Stop Condition PS

T HIGHT LOW T HD:STA T SU:STO

T HD:STAT HD:DAT

T SU:DAT T SU:STA

T FALL

T RISE

TABLE 1-3: TEMPERATURE SPECIFICATIONSParameters Sym. Min. Typ. Max. Units Conditions

Temperature RangesOperating Temperature Range TA -40 — +105 °COperating Junction Temperature TJ -40 — +125 °CStorage Temperature Range TA -55 — +150 °CThermal Package Resistances - see Table 1-1


UCS2113

1.1 ESD and Transient Performance

1.1.1 HUMAN BODY MODEL (HBM) PERFORMANCE

HBM testing verifies the ability to withstand ESDstrikes, like those that occur during handling andmanufacturing, and is done without power applied tothe IC. To pass the test, the device must have nochange in operation or performance due to the event.

1.1.2 CHARGED DEVICE MODEL (CDM) PERFORMANCE

CDM testing verifies the ability to withstand ESDstrikes, like those that occur during handling andassembly, with pick-and-place-style machinery and isdone without power applied to the IC. To pass the test,the device must have no change in operation orperformance due to the event.

TABLE 1-4: ESD RATINGSESD Specification Rating or Value

Human Body Model (JEDEC JESD22-A114) - All pins 8 kVCharged Device Model (JEDEC JESD22-C101) - All pins 500V


UCS2113

NOTES:


UCS2113

2.0 TYPICAL PERFORMANCE CURVES

Note: Unless otherwise indicated, VDD = VS = 5V, TA = +27°C.

FIGURE 2-1: Short Applied After Power-Up.

FIGURE 2-2: Power-Up Into a Short.

FIGURE 2-3: Internal Power Switch Short Response.

FIGURE 2-4: VBUS Discharge Behavior.

FIGURE 2-5: Power Switch On Resistance vs. Temperature.

FIGURE 2-6: Power Switch On/Off Time vs. Temperature.

Note: The graphs and tables provided following this note are a statistical summary based on a limited number ofsamples and are provided for informational purposes only. The performance characteristics listed hereinare not tested or guaranteed. In some graphs or tables, the data presented may be outside the specifiedoperating range (e.g., outside specified power supply range) and therefore outside the warranted range.

-1

0

1

2

3

4

5

6

-1

0

1

2

3

4

5

6

0 2 4 6 8 10C

urre

nt (A

)

Volta

ge (V

)

Time (ms)

IBUS

VBUS

VS = VDD = 5VILIM = 3A min (3.4A max), short applied at 2 ms

-1

0

1

2

3

4

5

6

-1

0

1

2

3

4

5

6

0 20 40 60 80 100 120 140 160 180 200

Cur

rent

(A)

Volta

ge (V

)

Time (ms)

VS = VDD

ALERT#

IBUS

-4

0

4

8

12

16

20

24

28

-2

-1

0

1

2

3

4

5

6

0 20 40

Cur

rent

(A)

Volta

ge (V

)

Time (µs)

VS = VDD = 5VILIM = 2.13A (typical), short applied at 10 µs

IBUS

VBUS

-1

0

1

2

3

4

5

6

0 100 200 300 400 500

Volta

ge (V

)

Time (ms)

VBUS

05

1015202530354045

-40 -15 10 35 60 85 110

On

Res

ista

nce

(mΩ

)

Temperature (°C)

0,6

0,65

0,7

0,75

0,8

0,85

0,9

0,95

1

-40 -15 10 35 60 85 110

Tim

e (m

s)

Temperature (°C)

Turn on time

Turn off time


UCS2113


FIGURE 2-7: VS Overvoltage Threshold vs. Temperature.

FIGURE 2-8: VS Undervoltage Threshold vs. Temperature.

FIGURE 2-9: Trip Current Limit Operation vs. Temperature.

FIGURE 2-10: IBUS Measurement Accuracy.

FIGURE 2-11: Active State Current vs. Temperature (both channels on, PWR_EN1 = PWR_EN2 = 1).

5.905.925.945.965.986.006.026.046.066.086.10

-40 -15 10 35 60 85 110

V STh

resh

old

Volta

ge (V

)

Temperature (°C)

VDD = 5V

2.02.12.22.32.42.52.62.72.82.93.0

-40 -15 10 35 60 85 110

V STh

resh

old

Volta

ge (V

)

Temperature (°C)

VDD = 5V

Threshold

Hysteresis

-12%

-10%

-8%

-6%

-4%

-2%

0%

-40 -15 10 35 60 85 110

Cur

rent

Lim

it A

ccur

acy

%)

Temperature (°C)

VS = VDD = 5VILIM = 3.0A min. (3.2A typ., 3.4A max.)

Note: The percentage is relative to the maximum specification (3.4A)

-5

-4

-3

-2

-1

0

1

2

3

4

5

0.0 0.5 1.0 1.5 2.0 2.5 3.0

Acc

urac

y (%

)

Current (A)

0

100

200

300

400

500

600

700

800

-40 -15 10 35 60 85 110

Supp

ly C

urre

nt (

A)

Temperature (°C)

IDD + IS1 + IS2

IDD

IS1 + IS2


UCS2113


FIGURE 2-12: Sleep State Current vs. Temperature.

FIGURE 2-13: ILIM1 Trip Current Distribution.

FIGURE 2-14: ILIM2 Trip Current Distribution(1).




0

2

4

6

8

10

12

14

-40 -15 10 35 60 85 110

Supp

ly C

urre

nt (

A)

Temperature (°C)

IDD + IS1 + IS2

IDD

IS1 + IS2

0%

10%

20%

30%

40%

50%

60%

0.50

5

0.51

0.51

5

0.52

0.52

5

0.53

0.53

5

0.54

0.54

5

0.55

0.55

5

Sam

ples

(%)

VBUS Current (A)

0%

10%

20%

30%

40%

50%

60%

0.91

0.92

0.93

0.94

0.95

0.96

0.97

0.98

0.99 1

1.01

Sam

ples

(%)

VBUS Current (A)

0%

10%

20%

30%

40%

50%

60%

1.02

1.03

1.04

1.05

1.06

1.07

1.08

1.09 1.

1

1.11

1.12

Sam

ples

(%)

VBUS Current (A)

0%

10%

20%

30%

40%

50%

60%

1.23

1.24

1.25

1.26

1.27

1.28

1.29 1.

3

1.31

1.32

1.33

Sam

ples

(%)

VBUS Current (A)

0%

10%

20%

30%

40%

50%

60%

1.52

5

1.54

1.55

5

1.57

1.58

5

1.6

1.61

5

1.63

1.64

5

1.66

1.67

5

Sam

ples

(%)

VBUS Current (A)

Note 1: The histogram aspect is caused by a mixture of two normal distributions, corresponding to the two VBUS channels.


UCS2113





0%

10%

20%

30%

40%

50%

60%2.

03

2.05

2.07

2.09

2.11

2.13

2.15

2.17

2.19

2.21

2.23

Sam

ples

(%)

VBUS Current (A)

0%

10%

20%

30%

40%

50%

60%

2.54

5

2.57

2.59

5

2.62

2.64

5

2.67

2.69

5

2.72

2.74

5

2.77

2.79

5

Sam

ples

(%)

VBUS Current (A)

0%

10%

20%

30%

40%

50%

60%

3

3.04

3.08

3.12

3.16 3.

2

3.24

3.28

3.32

3.36 3.

4

Sam

ples

(%)

VBUS Current (A)

Note 1: The histogram aspect is caused by a mixture of two normal distributions, corresponding to the two VBUS channels.


UC

S2113

DS

20005680A-page 15

2016 M

icrochip Technology Inc.

Connection Type if Pin Not Used

Connect to ground or VDD (depending on the polarity decoded via COMM_ILIM pin)N/AConnect to ground

O Leave openO Connect to ground

N/AO Connect to ground

O Leave openN/A

N/AConnect to ground or VDD (depending on the polarity decoded via COMM_ILIM pin)Connect to ground Connect to VPULLUP(or to ground in Stand-Alone mode)Connect to VPULLUP (or to ground in Stand-Alone mode)N/AConnect to ground

N/A

3.0 PIN DESCRIPTIONDescriptions of the pins are listed in Table 3-1.

TABLE 3-1: PIN FUNCTION TABLEUCS21134x4 QFN Symbol Function Pin Type

1 PWR_EN1 Port power switch enable #1 DI

2 GND Ground Power3 BOOST# Logic output for DC-DC converter voltage increase (requires

pull-up resistor)OD

4, 5 VBUS1 Port power switch #1 output (requires both pins tied together) High Power, AI6, 7 VS Voltage input to port power switch VBUS1 (requires both pins

tied together)High Power, AI

8 VDD Common supply voltage Power9, 10 VS Voltage input to port power switch VBUS2 (requires both pins

tied together)High Power, AI

11, 12 VBUS2 Port power switch #2 output (requires both pins tied together) High Power, AI13 COMM_ILIM Enables SMBus or Stand-Alone mode at power-up. Hardware

strap for maximum current limit.AIO

14 GND Ground Power15 PWR_EN2 Port power switch enable #2 DI

16 ALERT#2 Output fault ALERT for VBUS2 (requires pull-up resistor) OD17 SMCLK SMCLK - SMBus clock input (requires pull-up resistor) DI

18 SMDATA SMDATA - SMBus data input/output (requires pull-up resistor) DIOD

19 GND Ground Power

20 ALERT#1 Output fault ALERT for VBUS1 (requires pull-up resistor) OD

21 EP Exposed thermal pad. Must be connected to electrical ground. EP

UCS2113

TABLE 3-2: PIN TYPESPin Type Description

Power This pin is used to supply power or ground to the device

Hi-Power This pin is a high-current pinAIO Analog Input/Output - this pin is used as

an I/O for analog signalsDI Digital Input - this pin is used as a digital

inputDIOD Open-Drain Digital Input/Output - this

pin is bidirectional. It is open-drain and requires a pull-up resistor.

OD Open-Drain Digital Output - used as a digital output. It is open-drain and requires a pull-up resistor.

EP Exposed thermal pad


UCS2113

4.0 TERMS AND ABBREVIATIONS

Note: The PWR_EN1 and PWR_EN2 pins each have configuration bits (“_S” in GeneralConfiguration 1 register (Address 11h) and General Configuration 2 register (Address 12h)) that may beused to perform the same function as the external pin state. These bits are accessed via the SMBus/I2Cand are OR’d with the respective pin. This OR’d combination of pin state and register bit is referenced asthe control.

TABLE 4-1: TERMS AND ABBREVIATIONSTerm/Abbreviation Description

CC Constant CurrentCurrent Limiting Mode

Determines the action that is performed when the IBUS current reaches the ILIM threshold. Trip opens the port power switch. Constant Current (variable slope) allows VBUS to be dropped by the portable device.

IBUS_R2MIN Current limiter mode boundaryILIM The IBUS current threshold used in current limiting. In Trip mode, when ILIM is reached, the

port power switch is opened. In Constant Current mode, when the current exceeds ILIM, operation continues at a reduced voltage and increased current; if VBUS voltage drops below VBUS_MIN, the port power switch is opened.

OCL Overcurrent limitPOR Power-on ResetPortable Device USB device attached to the USB portStand-Alone Mode Indicates that the communications protocol is not active and all communications between the

UCS2113 and a controller are done via the external pins only (PWR_EN1 and PWR_EN2 as inputs, and ALERT1# and ALERT2# as outputs)


UCS2113

NOTES:


UCS2113

5.0 GENERAL DESCRIPTIONThe UCS2113 is a dual-port power switch. Two USBpower ports are supported with current limits up to 3.0Acontinuous current (3.4A maximum) each. Selectableand programmable current limiting configurations arealso available to the application. A typical blockdiagram is shown in Figure 5-1.

FIGURE 5-1: Typical USB Application.

VBUS

2 PORT HUB

PD_ALERT1

PD_ALERT2

D+

D-

USB Port 1 Connector

SMDATSMCLK

SMDATSMCLK

D+

D-

D+

D-

UCS2113

PWR_EN1ALERT1

VBUS1

PWR_EN2ALERT2

VBUS2

USB Port 2 Connector

D+

D-

VBUS


UCS2113

5.1 UCS2113 Power StatesPower states are indicators of the device’s currentconsumption in the system and the functionality of thedigital logic. Table 5-1 details the UCS2113 powerstates.

Table 5-2 shows the settings for the various powerstates, except Off and Error. If VDD < VDD_TH, theUCS2113 is in the Off state.

5.1.1 OFF STATE OPERATIONThe device will be in the Off state if VDD is less thanVDD_TH. When the UCS2113 is in the Off state, it will donothing and all circuitry will be disabled. Digital registervalues are not stored and the device will not respond toSMBus commands.

5.1.2 SLEEP STATE OPERATIONThe PWR_EN1 and PWR_EN2 pins may be used tocause the UCS2113 to enter/exit Sleep. These pins areAND’ed for Sleep mode.

When the UCS2113 is in the Sleep state, the device willbe in its lowest power state. The port power switch willbe disabled. VBUS1 and VBUS2 will be near ground

potential. The ALERT#1 and ALERT#2 pins will not beasserted. If asserted prior to entering the Sleep state,the ALERT# pin will be released. SMBus activity is lim-ited to single byte read or write.

The first data byte read from the UCS2113 when it is inthe Sleep state will wake it; however, the data to beread will return all 0’s and should be considered invalid.This is a “dummy” read byte meant to wake theUCS2113. Subsequent read or write bytes will beaccepted normally. After the dummy read, theUCS2113 will be in a higher power state (seeFigure 5-2). After communication has not occurred fortIDLE_SLEEP, the UCS2113 will return to Sleep.

TABLE 5-1: POWER STATES DESCRIPTIONState Description

Off This power state is entered when the voltage at the VDD pin voltage is < VDD_TH. In this state, the device is considered “off”. The UCS2113 will not retain its digital states and register contents nor respond to SMBus/I2C communications. The port power switch will be off. See Section 5.1.1 “Off State Operation”.

Sleep This is the lowest power state available. While in this state, the UCS2113 will retain digital functionality and wake to respond to SMBus/I2C communications. See Section 5.1.2 “Sleep State Operation”.

Error This power state is entered when a fault condition exists. Error power state is one or both channels in Fault Handling. This state is updated as Priority One. The Interrupt Status Registers for each channel will update the fault detected per channel. Only the channel that has detected a Fault will be affected since the other channel can remain active if no fault is detected. See Section 5.1.4 “Error State Operation”.

Active Active power State is one, or both channels active and sourcing current to the VBUS Port. This state is updated as Priority Two. None of the channels have detected Fault. This power state provides full functionality. While in this state, operations include activation of the port power switch, current limiting, and charge rationing. See Section 5.1.3 “Active State Operation”.

TABLE 5-2: POWER STATES CONTROL SETTINGSPower State PWR_EN1 PWR_EN2 Behavior

Sleep disabled disabled • All switches disabled• VBUS will be near ground potential• The UCS2113 wakes to respond to SMBus

communicationsActive enabled disabled • Port power switch is on for VBUS1

• VBUS2 pins are near ground potential or floating (Note 1)disabled enabled • Port power switch is on for VBUS2

• VBUS1 pins are near ground potential or floating (Note 1)enabled enabled • Port power switch is on for VBUS1 and VBUS2

Note 1: If the bit EN_VBUS_DISCHG is '1', the VBUS is discharged automatically and VBUS is near ground potential. If the bit EN_VBUS_DISCHG is '0' then the corresponding VBUS pins are floating (VBUS discharge is controlled by the SMBus master).


UCS2113

FIGURE 5-2: Wake from Sleep using SMBus Read.

5.1.3 ACTIVE STATE OPERATIONEvery time the UCS2113 enters the Active state, theport power switches are closed. The UCS2113 cannotbe in the Active state (and therefore, the port powerswitch cannot be turned on) if any of the followingconditions exist:

• VS < VS_UVLO• PWR_EN1 and PWR_EN2 are disabled.

5.1.4 ERROR STATE OPERATIONThe UCS2113 will enter the Error state from the Activestate when any of the following events are detected:

• The maximum allowable internal die temperature (TTSD_HIGH) has been exceeded.

• The TTSD_LOW die temperature has been exceeded and any of the following conditions is met:- a power switch operates in constant current

mode- PWR_EN1 and/or PWR_EN2 controls

transition from inactive to active.- it is a power up situation and PWR_EN1

and/or PWR_EN2 pins are active.• An overcurrent condition has been detected. • An undervoltage condition on either VBUS pin has

been detected (see Section 5.3.4 “Undervoltage Lockout on VS”).

• A back-voltage condition has been detected (see Section 5.3.2 “Back-voltage Detection”).

• A discharge error has been detected. • An overvoltage condition on the VS pin.

When the UCS2113 enters the Error state, the portpower switch will be disabled while the ALERT# pin isasserted. It will remain off while in this power state. TheUCS2113 will leave this state as determined by the faulthandling selection.

With the Auto-recovery fault handler, after the tCYCLEtime period, the UCS2113 will check that all of the errorconditions have been removed.

If all of the error conditions have been removed, theUCS2113 will return to the Active state.

If both PWR_EN1 and PWR_EN2 controls transitionfrom active to inactive while the UCS2113 is in the Errorstate, the device will not enter the Sleep state. After thefault has been removed, the UCS2113 will not automat-ically enter the Sleep state if the EN_VBUS_DISCHGbit from the General Configuration 2 Register is not set(default setting). To enter the Sleep state, the PWR_ENpins must be toggled or an SMBus read register com-mand must be sent.

5.2 CommunicationThe UCS2113 can operate in SMBus mode (seeSection 7.0 “System Management Bus Protocol”)or Stand-Alone mode. The resistor connected to theCOMM_ILIM pin determines the operating mode andthe hardware-set ILIM setting, as shown in Table 5-3.Unless connected to GND or VDD, the resistors inTable 5-3 are external pull-down resistors.

The SMBus address is specified in Section 7.2“SMBus Address and RD/WR Bit”.

0101_1110 A invalid dataN P

SMBus Read

A0001_0000 0101_1110A valid data N P0001_0000SS

tIDLE_SLEEPSleep Sleep

Dummy read returns invalid data and places device in temporary

Active state Read returns valid data

0101_1111 AS 0101_1111 ASA

Power State temporary Active state(not all functionality available)

tSMB_WAKE

TABLE 5-3: COMMUNICATION DECODECOMM_ILIM Pull Down

Resistor (±1%)PWR_EN1 and

PWR_EN2 Polarity ILIM (A)Total ILIM (A)

(Note 1)Communication

Mode

GND Active-High 0.53 0.53 + 0.53 SMBUS

10 k Active-High 0.96 0.96 + 0.96 SMBUS





UCS2113

5.3 Supply Voltages

5.3.1 VDD SUPPLY VOLTAGEThe UCS2113 requires 4.5V to 5.5V to be present onthe VDD pin for core device functionality. Core devicefunctionality consists of maintaining register states andwake-up upon SMBus/I2C query.

5.3.2 BACK-VOLTAGE DETECTIONThe back-voltage detector is functional in all powerstates (Sleep and Active).

When in Sleep, the UCS2113 will enter the Error statefrom Sleep if a back-voltage condition was detected.

Whenever the following condition is true for either port,the port power switch will be disabled and aback-voltage event will be flagged. This will cause theUCS2113 to enter the Error power state (seeSection 5.1.4 “Error State Operation”).

5.3.3 BACK-DRIVE CURRENT PROTECTION

If a portable device is attached that is self-powered, itmay drive the VBUS port to its power supply voltagelevel; however, the UCS2113 is designed such thatleakage current from the VBUS pins to the VDD and/orthe VS pin shall not exceed ILKG_1 (if the VDD and/or VSvoltage is zero) or ILKG_2 (if the VDD and/or VS voltageexceeds VDD_TH and the power switch is open).

5.3.4 UNDERVOLTAGE LOCKOUT ON VSThe UCS2113 requires a minimum voltage (VS_UVLO)be present on the VS pin for Active power state.

5.3.5 OVERVOLTAGE DETECTION AND LOCKOUT ON VS

Both power switches will be disabled if the voltage onany VS pin exceeds a voltage (VS_OV) for longer thanthe specified time (tMASK). This will cause the device toenter the Error state and both ALERT#1 and ALERT#2pins will be asserted.

5.3.6 PWR_EN1 AND PWR_EN2 INPUTThe PWR_EN control affects the power state and enablesthe port power switch to be turned on if conditions are met(see Table 5-2). The port power switch cannot be closedif PWR_EN is disabled. However, if PWR_EN is enabled,the port power switch is not necessarily closed (seeSection 5.1.3 “Active State Operation”). In SMBusmode, the PWR_EN1 and PWR_EN2 pins states will beignored by the UCS2113 if the PIN_IGN configuration bitis set; otherwise, the PWR_EN1S and PWR_EN2Sconfiguration bits are checked along with the pins.




47 k Active-Low 0.53 0.53 + 0.53 Stand-Alone







VDD Active-Low 3.2 3.2 + 3.2 Stand-Alone

Note 1: The total maximum current depends on power dissipation characteristics of the design (see Table 1-1).

TABLE 5-3: COMMUNICATION DECODE (CONTINUED)COMM_ILIM Pull Down

Resistor (±1%)PWR_EN1 and

PWR_EN2 Polarity ILIM (A)Total ILIM (A)

(Note 1)Communication

Mode

Note: The VBUS voltage exceeds the VS and/orthe VDD pin voltage by VBV_TH and theport power switch is closed. The portpower switch will be opened immediately.If the condition lasts for longer than tMASK,then the UCS2113 will enter the Errorstate. Otherwise, the port power switchwill be turned on as soon as the conditionis removed.


UCS2113

5.4 Discrete Output Pins5.4.1 ALERT#1 AND ALERT#2 OUTPUT

PINSThe UCS2113 has two independent ALERT# out pins.ALERT#1 is tied to the status of the VBUS1 pin.ALERT#2 is tied to the status of the VBUS2 pin.The ALERT# pin is an active-low open-drain interruptto the host controller. The ALERT# pin is assertedwhen an error occurs. Also, when charge rationing isenabled, the ALERT# pin is asserted by default whenthe current rationing threshold is reached (asdetermined by RATION_BEH). The ALERT# pinis released when all error conditions that may assertthe ALERT# pin (such as an error condition and chargerationing) have been removed or reset as necessary.

The UCS2113 is compatible with the Microchip hubdevices supporting single pin power control feature.These hub devices have a single connection to thePWR_EN and ALERT# pins of the UCS2113, which aretied together in the application.

5.4.2 BOOST# OUTPUT PINThe UCS2113 provides a BOOST# output pin tocompensate for voltage drops during high loads. TheBOOST# pin is an active-low, open-drain output thatwould be connected to a resistor in the DC-DCconverter’s feedback error voltage loop (seeFigure 5-3).The BOOST# pin is asserted whenVBUS Current > IBOOST. IBOOST typical value is 1.9A.The BOOST# is OR’ed for both VBUS1 and VBUS2 ports.When the BOOST# pin is asserted, it will remain in thisstate for at least tBOOST_MAT (minimum assertion time).

FIGURE 5-3: Boost# Pin Usage.

5.5 Discrete Input Pins

5.5.1 COMM_ILIM INPUTThe COMM_ILIM input determines thecommunications mode, as shown in Table 6-1. This isalso the hardware strap for MAX Current Limit.

5.5.2 SMCLKWhen operated in Stand-Alone mode, this pin should betied to ground. When the UCS2113 is configured forSMBus communications, the SMCLK is the clock input.

5.5.3 SMDATAWhen used in Stand-Alone, this pin should be tied toground.When the UCS2113 is configured for SMBuscommunications, the SMDATA is the data input/output.

DC-DCConverter Block

5.0VOUT

FeedBack

GND

R1

R2

R3

R4

VFB

SM

CLK

/LO

AD

_SH

AR

EGND

PWR_EN1

BOOST#

VS

1

2

3

4

6 7 8 9

SM

DA

TA/L

OW

_ILM

5

10

15

14

13

12

20 19 18 17

VS

PWR_EN2

ALE

RT#

1

VS

GND

GN

DV

S

ALE

RT#

2VBUS1

VD

D

COMM_ILIM

11

16

GND FLAG

UCS2113 20-QFN 4 x 4 mm

VBUS1 VBUS2

VBUS2

5VOUTR1 R2 R3+ + VFB

R3--------------------------------------------------------=

VOUTR2 R3+ R1 VFB

R3 R4--------------------------------------------------------=

VOUT5VOUT

VFB--------------------

R1R3------–

R1 VFB

R4------------------------=

If R1 R3 VOUT5VOUT R1

R4---------------------------------


UCS2113

NOTES:


UCS2113

6.0 USB PORT POWER SWITCHTo assure compliance to various chargingspecifications, the UCS2113 contains a USB portpower switch that supports two current-limiting modes:Trip and Constant current (variable slope). The currentlimit (ILIM) is pin selectable (and may be updated viathe register set). The switch also includes soft startcircuitry and a separate short circuit current limit.

The port power switch is on in the Active state (exceptwhen VBUS is discharging).

6.1 Current Limiting

6.1.1 CURRENT LIMIT SETTINGThe UCS2113 hardware set current limit, ILIM, can beone of eight values. This resistor value is read onceupon UCS2113 power-up. The current limit can bechanged via the SMBus/I2C after power-up; however,the programmed current limit cannot exceed the hard-ware set current limit. Unless connected to VDD, theresistors in Table 6-1 are pull-down resistors.

At power-up, the communication mode (Stand-Aloneor SMBus/I2C) and hardware current limit (ILIM) aredetermined via the pull-down resistor (or pull-upresistor if connected to VDD) on the COMM_ILIM pin,as shown in Table 6-1.

6.1.2 SHORT CIRCUIT OUTPUT CURRENT LIMITING

Short circuit current limiting occurs when the outputcurrent is above the selectable current limit (ILIMx).This event will be detected and the current willimmediately be limited (within tSHORT_LIM time). If thecondition remains, the port power switch will flag anError condition and enter the Error state.

6.1.3 SOFT STARTWhen the PWR_EN control changes states to enable theport power switch, the UCS2113 invokes a soft startroutine for the duration of the VBUS rise time (tR_BUS).This soft start routine will limit current flow from VS intoVBUS while it is active. This circuitry will prevent currentspikes due to a step in the portable device current draw.In the case when a portable device is attached while thePWR_EN pin is already enabled, if the bus currentexceeds ILIM, the UCS2113 current limiter will respondwithin a specified time (tSHORT_LIM) and will operatenormally at this point. The CBUS capacitor will deliver theextra current, if any, as required by the load change.

6.1.4 CURRENT LIMITING MODESThe UCS2113 current limiting has two modes: Trip andConstant Current (variable slope). Either modefunctions at all times when the port power switch isclosed.

6.1.4.1 Trip ModeWhen using Trip current limiting, the UCS2113 USBport power switch functions as a low-resistance switchand rapidly turns off if the current limit is exceeded.While operating using Trip current limiting, the VBUSoutput voltage will be held relatively constant (equal tothe VS voltage minus the RON x IBUS current) for allcurrent values up to the ILIM.

If the current drawn by a portable device exceeds ILIM,the following occurs:

1. The port power switch will be turned off (Tripaction).

2. The UCS2113 will enter the Error state andassert the ALERT# pin.

3. The fault handling circuitry will then determinesubsequent actions.

TABLE 6-1: ILIM DECODECOMM_ILIM

Pulldown Resistor

(±1%)

PWR_EN1 and

PWR_EN2 Polarity

ILIM (A)Total ILIM

(A)(Note 1)

GND Active-High 0.53 0.53+0.5310 kΩ Active-High 0.96 0.96+0.9612 kΩ Active-High 1.07 1.07+1.0715 kΩ Active-High 1.28 1.28+1.2818 kΩ Active-High 1.6 1.6+1.622 kΩ Active-High 2.13 2.13+2.13 27 kΩ Active-High 2.67 2.67+2.6733 kΩ Active-High 3.2 3.2+3.247 kΩ Active-Low 0.53 0.53+0.5356 kΩ Active-Low 0.96 0.96+0.9668 kΩ Active-Low 1.07 1.07+1.0782 kΩ Active-Low 1.28 1.28+1.28

100 kΩ Active-Low 1.6 1.6+1.6120 kΩ Active-Low 2.13 2.13+2.13 150 kΩ Active-Low 2.67 2.67+2.67

VDD Active-Low 3.2 3.2+3.2Note 1: The total maximum current depends on

power dissipation characteristics of the design (see Table 1-1).


UCS2113

Figure 6-1 shows operation of current limits in Tripmode with the shaded area representing the USB 2.0specified VBUS range. Dashed lines indicate the portpower switch output will go to zero (e.g., Trip) whenILIM is exceeded. Note that operation at all possiblevalues of ILIM are shown in Figure 6-1 for illustrativepurposes only; in actual operation only one ILIM can beactive at any time.

FIGURE 6-1: Current Limiting in Trip Mode.

6.1.4.2 Constant Current Limiting (Variable Slope)

Constant current limiting is used when the currentdrawn is greater than ILIM (and ILIM < 1.6A). In CCmode, the port power switch allows the attachedportable device to reduce VBUS output voltage to lessthan the input VS voltage while maintaining currentdelivery. The V/I slope depends on the user set ILIMvalue. This slope is held constant for a given ILIMvalue.

This mode is specifically provided for devices that relyon resistive means to reduce VBUS voltage for directbattery charging or to allow portable devices a meansto “test” charger capacity. See Figure 6-2.

FIGURE 6-2: Constant Current Example.

Figure 6-3 shows operation of current limits whileusing CC mode. Unlike Trip mode, once IBUS currentexceeds ILIM, operation continues at a reduced voltageand increased current. Note that the shaded area rep-resenting the USB 2.0 specified VBUS range is nowrestricted to an upper current limit of IBUS_R2MIN. Notethat the UCS2113 will heat up along each load line asvoltage decreases. If the internal temperature exceedsthe TTSD_LOW threshold, the corresponding powerswitch operating in constant current mode will open. Ifthe internal temperature exceeds the TTSD_HIGHthreshold, both power switches will open, regardlessof whether the power switch channels are in currentlimit. Also note that when the VBUS voltage is broughtlow enough (below VBUS_MIN), the port power switchwill open.

FIGURE 6-3: Current Limiting in CC Mode.

6.2 USB Port Power ProfilesThe UCS2113 combines the qualities of traditionalUSB port power switches with USB port power profilesset forth in the USB-IF BC1.2 specification. USB portpower profiles consist of distinct voltage-currentoperation regions defined by “keep-out” and“operation” regions.

While operating in the CC mode of operation, theUCS2113 provides voltage-current output operatingprofiles that are specified by two keep-out regions.

If the current reaches the IBUS_R2MIN setting for longerthan tMASK, the UCS2113 enters the Error state and anOvercurrent event is flagged.

If the VBUS voltage ever goes below the no operationlower-voltage keep-out (VBUS_MIN) value for longerthan tMASK, the port power switch is disabled and a

5

4

3

2

1

0.53 1.07 1.6 2.67 3.2

5.25

4.75

IBUS (Amps)

VB

US

(Vol

ts)

Operating Current

0

00.96 1.28

1.281.070.960.53 1.6 3.22.13 2.67

= ILIM’s

2.13

Power Switch Voltage and Current Output go to Zero when ILIM is

Exceeded

Trip action (ILIM = 0.53 A)

Trip action (ILIM = 3.2 A)

ILIM (Amps)

Control Loop Temp

VS

GND

ILIM

Power Switch

DC5V

Battery Charger

IC

VBAT

RSense

IBUS

Portable Device

VBUS

UCS2113

keep-out violation is flagged (by setting theMIN_KEEP_OUT status bit). This will cause the deviceto enter the Error state.

Figure 6-4 illustrates the relationship between theseUSB port power profile parameters.

6.2.1 OPERATION WITHIN A USB PORT POWER PROFILE

An attached device may be constrained to operatewithin the boundaries of a USB port power profile bysetting the value of ILIM less than the USB port powerprofile IBUS_R2MIN value. In this case, the port powerswitch will be in Trip mode up until ILIM is exceeded. Atwhich point, the switch will transition into CC mode. Ifthe attached device reduces the output voltage to lessthan VBUS_MIN, the switch will trip and terminatecharging.

FIGURE 6-4: ILIM < IBUS_R2MIN Example.

6.2.2 OPERATION OUTSIDE OF A USB PORT POWER PROFILE

An attached device may be allowed to operate outsideof the boundaries of a USB port power profile bysetting the value of ILIM greater than the USB portpower profile IBUS_R2MIN value. This is the defaultoperation for all portable devices. In this case, theUSB port power switch will operate in Trip mode untilthe bus current reaches the ILIM value. Once the ILIMvalue has been exceeded, the port power switch willopen and terminate charging. Figure 6-5 illustrates anexample of current limiting in this configuration.

FIGURE 6-5: ILIM > IBUS_R2MIN Example.

Note: The CC mode of operation is possible onlyup to 1.6A. As long as the value of ILIM isless than the fixed port power profileIBUS_R2MIN value, CC mode is possible.Otherwise, the USB port power switch willoperate in Trip mode operation.

5

4

3

2

1

0.53 1.6 2.67 3.2

5.25

4.75

00

Port Power Profile Operating Region

0.96 1.28

1.280.960.53 1.6

2.13

2.13 2.67 3.2

VBUS_MIN = 2.0 V

IBUS (Amps)

VB

US

(Vol

ts)

ILIM (Amps)

(Trip)

ILIM = 1.6A

IBUS_R2MIN = 1.6A

5

4

3

2

1

0.53 1.6 2.67 3.2

5.25

4.75

00

Port Power Profile Operating Region

0.96 1.28

1.280.960.53 1.6

2.13

2.13 2.67 3.2

VBUS_MIN = 2.0 V

IBUS (Amps)

VB

US

(Vol

ts)

ILIM (Amps)

(Trip)

ILIM = 2.67 A

IBUS_R2MIN = 1. A


UCS2113

6.3 Thermal ProtectionThe UCS2113 utilizes two-stage internal thermalmanagement. The first is triggered when the dietemperature exceeds TTSD_LOW threshold and thesecond is triggered when the die temperature exceedsTTSD_HIGH threshold.

6.3.0.1 THE FIRST THERMAL SHUTDOWN STAGE (TTSD_LOW)

The first stage turns off the individual power switchchannel when the die temperature exceeds TTSD_LOWthreshold and a power switch operates in constantcurrent mode. It also causes the correspondingchannel to enter in error state and the correspondingALERT# pin will be asserted.When an over-current condition appears, the powerswitch operates in constant current mode for theduration of tMASK time. Because of the increasedvoltage drop across the switch, the die temperatureincreases. If the die temperature exceeds TTSD_LOWthreshold before the expiration of the tMASK time, thenthe power switch will open immediately.If the TTSD_LOW threshold has been exceeded, but thedie temperature has not decreased below theTTSD_LOW recovery threshold, then the power switchcannot be closed when commanded by the PWR_EN1or PWR_EN2 controls in the following situations:• PWR_EN1 and/or PWR_EN2 controls transition

from inactive to active.• it is a power up situation and PWR_EN1 and/or

PWR_EN2 pins are active.In these situations, the corresponding channel willenter in error state and the corresponding ALERT# pinwill be asserted.The first thermal shutdown stage allows the two portsto work independently, by preventing the dietemperature to increase during over-current conditionsand to exceed the maximum allowable temperature(TTSD_HIGH).The error state will persist and the power switches cannot be closed until the temperature is belowTTSD_LOW - TTSD_LOW_HYST.

6.3.0.2 THE SECOND THERMAL SHUTDOWN STAGE (TTSD_HIGH)

The second thermal protection stage turns off bothpower switches when the die temperature exceedsTTSD_HIGH threshold, regardless of whether the powerswitch channels are in current limit. It also causes bothchannels to enter in error state and both ALERT#1 andALERT#2 pins to be asserted.The error state will persist and the power switchescannot be closed until the temperature is belowTTSD_HIGH - TTSD_HIGH_HYST.

6.4 VBUS DischargeWhen the EN_VBUS_DISCHG bit from GeneralConfiguration 2 Register is set (by default it is not set),the UCS2113 will discharge VBUS through an internal100 resistor when at least one of the followingconditions occur: • The PWR_EN control is disabled (triggered on the

inactive edge of the PWR_EN control).• The VS voltage drops below a specified threshold

(VS_UVLO) that causes the port power switch to be disabled.

• When commanded into the Sleep power state.• Upon recovery from the Error state. • When commanded via the SMBus in the Active

state.

When the automatic VBUS discharge circuitry isactivated, the UCS2113 will confirm that VBUS wasdischarged at the end of the tDISCHARGE time. If theVBUS voltage is not below the VTEST level, a dischargeerror will be flagged (by setting the DISCH_ERR(1/2)status bit) and the UCS2113 will enter the Error state.

When the EN_VBUS_DISCHG bit from GeneralConfiguration 2 Register is not set (default setting), theautomatic VBUS discharges described above aredisabled. In this case, the SMBus master must set andclear bits DISCHG_LOAD1 and DISCHG_LOAD2 fromthe Current Limit Behavior Registers, to discharge theVBUS1 and VBUS2. Setting the DISCHG_LOAD1 andDISCHG_LOAD2 bits connects the internal 100resistor to discharge the corresponding VBUS path.This functionality doesn't use any timers. Thedischarge time is controlled by the SMBus master,which must clear this bit when its internal timer expires.


UCS2113

6.5 Charge Rationing InteractionsWhen charge rationing is active, regardless of thespecified behavior, the UCS2113 will function normallyuntil the charge rationing threshold is reached. Notethat charge rationing is only active when the UCS2113is in the Active state. Changing the charge rationingbehavior will have no effect on the charge rationingdata registers. If the behavior is changed prior toreaching the charge rationing threshold, this change

will occur and be transparent to the user. When thecharge rationing threshold is reached, the UCS2113will take action as shown in Table 6-2. If the behavioris changed after the charge rationing threshold hasbeen reached, the UCS2113 will immediately adoptthe newly programmed behavior, clearing the ALERT#pin and restoring switch operation respectively (seeTable 6-4).

TABLE 6-2: CHARGE RATIONING BEHAVIOR RATION_BEH(1 or 2) Behavior Actions Taken Notes

1 00 0 Report ALERT# pin asserted.0 1 Report and

Disconnect (default)

1. ALERT# pin asserted2. Port power switch discon-

nected

All bus monitoring is still active. Toggling the PWR_EN control will cause the device to change power states as defined by the registers; however, the port power switch will remain off until the rationing circuitry is reset.

1 0 Disconnect and

Go to Sleep

1. Port power switch discon-nected

2. Device will enter the Sleepstate

All VBUS and VS monitoring will be stopped. Toggling the PWR_EN control will have no effect on the power state until the rationing circuitry is reset.

1 1 Ignore Take no further action

TABLE 6-3: CHARGE RATIONING RESET BEHAVIORBehavior Reset Actions

Report 1. Reset the Total Accumulated Charge registers2. Clear the RATION status bit3. Release the ALERT# pin

Report and Disconnect 1. Reset the Total Accumulated Charge registers2. Clear the RATION status bit3. Release the ALERT# pin4. Check the PWR_EN controls and enter the indicated power state if the controls

changedDisconnect and Go to Sleep

1. Reset the Total Accumulated Charge registers2. Clear the RATION status bit3. Check the PWR_EN controls and enter the indicated power state if the controls

changedIgnore 1. Reset the Total Accumulated Charge registers

2. Clear the RATION status bitTABLE 6-4: EFFECTS OF CHANGING RATIONING BEHAVIOR AFTER THRESHOLD REACHED Previous Behavior New Behavior Actions Taken

Ignore Report Assert ALERT# pinReport and Disconnect

1. Assert ALERT# pin2. Open port power switch. See the Report and Disconnect (default) in

Table 6-2Disconnect and

Go to Sleep1. Open port power switch2. Enter the Sleep state. See the Disconnect and Go to Sleep in Table 6-2


UCS2113

If the RATION_EN control is set to ‘0’ prior to reachingthe charge rationing threshold, rationing will bedisabled and the Total Accumulated Charge registerswill be cleared. If the RATION_EN control is set to ‘0’after the charge rationing threshold has been reached,the following additional steps occur:

1. RATION status bit will be cleared.2. The ALERT# pin will be released if asserted by

the rationing circuitry and no other conditionsare present.

3. The PWR_EN controls are checked todetermine the power state.

Setting the RATION_RST control to ‘1’ willautomatically reset the Total Accumulated Chargeregisters to 00_00h. If this is done prior to reaching thecharge rationing threshold, the data will continue to beaccumulated restarting from 00_00h. If this is doneafter the charge rationing threshold is reached, theUCS2113 will take action as shown in Table 6-3.

Report Ignore Release ALERT# pin.Report and Disconnect

Open port power switch. See the Report and Disconnect (default) in Table 6-2.

Disconnect and Go to Sleep

1. Release the ALERT# pin2. Open the port power switch3. Enter the Sleep state. See the Disconnect and Go to Sleep in Table 6-2.

Report and Disconnect

Ignore 1. Release the ALERT# pin2. Check the PWR_EN controls and enter the indicated power state if the

controls changedReport Check the PWR_EN controls and enter the indicated power state if the controls

changedDisconnect and

Go to Sleep1. Release the ALERT# pin2. Enter the Sleep state. See the Disconnect and Go to Sleep in Table 6-2.

Disconnect and Go to Sleep

Ignore Check the PWR_EN controls and enter the indicated power state if the controlschanged

Report 1. Assert the ALERT# pin2. Check the PWR_EN controls and enter the indicated power state if the

controls changedReport and Disconnect

1. Assert the ALERT# pin2. Check the PWR_EN controls to determine the power state, then enter that

state, except that the port power switch will not be closed

TABLE 6-4: EFFECTS OF CHANGING RATIONING BEHAVIOR AFTER THRESHOLD REACHED Previous Behavior New Behavior Actions Taken


UCS2113

6.6 Fault Handling MechanismThe UCS2113 has two modes for handling faults:

• Latch (latch-upon-fault)• Auto-recovery (automatically attempt to restore

the Active power state after a fault occurs).

If the SMBus is actively utilized, Auto-Recovery FaultHandling is the default error handler as determined bythe LATCH_SET bit. Faults include overcurrent,overvoltage (on VS), undervoltage (on VBUS),back-voltage (VBUS to VS or VBUS to VDD), dischargeerror, and maximum allowable internal die temperature(TTSD_HIGH) exceeded. Fault conditions also includethe situations when TTSD_LOW die temperature hasbeen exceeded and any of the following conditions aremet:

• a power switch operates in constant current mode• PWR_EN1 and/or PWR_EN2 controls transition

from inactive to active.• it is a power up situation and PWR_EN1 and/or

PWR_EN2 pins are active.

Faults do not include:

• keep-out violations except VBUS_MIN.• TTSD_LOW die temperature has been exceeded

and any of the following conditions are met:- the power switch is closed at the time when

TTSD_LOW is reached and it is not in constant current mode.

- the power switch remains open (PWR_EN1 and/or PWR_EN2 controls are not active).

6.6.1 AUTO-RECOVERY FAULT HANDLING

When the LATCH_SET bit is low, Auto-Recovery FaultHandling is used. When an error condition is detected,the UCS2113 will immediately enter the Error stateand assert the ALERT# pin. Independently from thehost controller, the UCS2113 will wait a preset time(tCYCLE), check error conditions (tTST), and restoreActive operation if the error condition(s) no longerexist. If all other conditions that may cause theALERT# pin to be asserted have been removed, theALERT# pin will be released. Short-CircuitAuto-Recovery example in Figure 6-6.

FIGURE 6-6: Error Recovery.

6.6.2 LATCHED FAULT HANDLINGWhen the LATCH_SET bit is high, latch fault handlingis used. When an error condition is detected, theUCS2113 will enter the Error power state and assertthe ALERT# (1 or 2) pin. Upon command from the hostcontroller (by toggling the PWR_EN (1, or 2) pincontrol from enabled to disabled or by clearing theERR bit via SMBus), the UCS2113 will check errorconditions once and restore Active operation if errorconditions no longer exist. If an error condition stillexists, the host controller is required to issue thecommand again to check error conditions.

If the ALERT# pin is asserted and the interrupt statusregisters (addresses 03h or 04h) are not read, thecorresponding ALERT# pin remains asserted until thecorresponding PWR_EN pin is toggled.

If the ALERT# pin is asserted and the interrupt statusregisters are read, the ALERT# pin will deassert, butthe UCS will remain in error state until the ERR bit iscleared via SMBus or the PWR_EN pin is toggled.

tTST

VBUS

IBUS

SHORTapplied.

ITEST

tDISCHARGE

ITEST

VTEST

Short Detected. VBUSdischarged. Enter

Error state.

Check short condition. Short

still present. Return to Error

State.

Wait tCYCLE. Wait tCYCLE.Check short

condition. Short removed. Return to normal

operation.

tCYCLE tCYCLEtTST


UCS2113

NOTES:


UCS2113

7.0 SYSTEM MANAGEMENT BUS PROTOCOL

In SMBus mode, the UCS2113 communicates with ahost controller, such as a Microchip PIC®microcontroller or hub, through the SMBus. TheSMBus is a two-wire serial communication protocolbetween a computer host and its peripheral devices. Adetailed timing diagram is shown in Figure 1-1.Stretching of the SMCLK signal is supported; however,the UCS2113 will not stretch the clock signal.

7.1 SMBus Start BitThe SMBus Start bit is defined as a transition of theSMBus Data line from a logic ‘1’ state to a logic ‘0’state while the SMBus Clock line is in a logic ‘1’ state.

7.2 SMBus Address and RD/WR BitThe SMBus Address Byte consists of the 7-bit clientaddress followed by the RD/WR indicator bit. If thisRD/WR bit is a logic ‘0’, the SMBus Host is writingdata to the client device. If this RD/WR bit is a logic ‘1’,the SMBus Host is reading data from the client device.

The UCS2113 with the order code UCS2113-1-V/G4has the SMBus address 57h - 1010_111(r/w).

Customers should contact their distributor,representatives or field application engineer (FAE) foradditional SMBus addresses. Local sales offices arealso available to help customers. A list of sales officesand locations is included in the back of this document.

7.3 SMBus Data BytesAll SMBus Data bytes are sent most significant bit firstand composed of 8 bits of information.

7.4 SMBus ACK and NACK BitsThe SMBus client will acknowledge all data bytes thatit receives. This is done by the client device pulling theSMBus Data line low after the 8th bit of each byte thatis transmitted. This applies to both the Write Byte andBlock Write protocols.

The Host will NACK (not acknowledge) the last data byteto be received from the client by holding the SMBus dataline high after the 8th data bit has been sent. For theBlock Read protocol, the Host will ACK (acknowledge)each data byte that it receives except the last data byte.

7.5 SMBus Stop Bit

The SMBus Stop bit is defined as a transition of theSMBus Data line from a logic ‘0’ state to a logic ‘1’state while the SMBus clock line is in a logic ‘1’ state.When the UCS2113 detects an SMBus Stop bit and ithas been communicating with the SMBus protocol, itwill reset its client interface and prepare to receivefurther communications.

7.6 SMBus Time-outThe UCS2113 includes an SMBus time-out feature. Ifthe clock is held at logic ‘0’ for tTIMEOUT, the devicecan time out and reset the SMBus interface. TheSMBus interface can also reset if both the clock anddata lines are held at a logic ‘1’ for tIDLE_RESET.Communication is restored with a start condition.

The time-out function defaults to disabled. It can beenabled by clearing the DIS_TO bit in the GeneralConfiguration 3 register (see Register 8-9).

7.7 SMBus and I2C ComplianceThe major difference between SMBus and I2C devicesis highlighted here. For complete complianceinformation, refer to the SMBus 2.0 specification andApplication Note 14.0.

• UCS2113 supports I2C fast mode at 400 kHz. This covers the SMBus maximum time of 100 kHz.

• The minimum frequency for SMBus communications is 10 kHz.

• The client protocol will reset if the clock is held low longer than 30 ms. This time out functionality is disabled by default in the UCS2113 and can be enabled by clearing the DIS_TO bit. I2C does not have a time out.

• Except when operating in Sleep, the client protocol will reset if both the clock and the data line are logic ‘1’ for longer than 200 µs (idle condition). This function is disabled by default in the UCS2113 and can be enabled by clearing the DIS_TO bit. I2C does not have an idle condition.

• I2C devices do not support the Alert Response Address functionality (which is optional for SMBus).

• I2C devices support block read and write differently. I2C protocol allows for unlimited number of bytes to be sent in either direction. The SMBus protocol requires that an additional data byte indicating number of bytes to read/write is transmitted. The UCS2113 supports I2C formatting only.

7.8 SMBus ProtocolsThe UCS2113 is SMBus 2.0-compatible and supportsSend Byte, Read Byte, Block Read, Receive Byte asvalid protocols as shown below. The UCS2113 alsosupports the I2C block read and block write protocols.The device supports Write Byte, Read Byte, and BlockRead/Block Write. All of the below protocols use theconvention in Table 7-1.

TABLE 7-1: SMBUS PROTOCOLData Sent to Device Data Sent to the Host

Data sent Data sent


UCS2113

7.9 SMBus Write ByteThe Write Byte is used to write one byte of data to aspecific register as shown in Table 7-2.

7.10 SMBus Read ByteThe Read Byte protocol is used to read one byte ofdata from the registers as shown in Table 7-3.

7.11 Block Write The Block Write is used to write multiple data bytes toa group of contiguous registers, as shown in Table 7-4.It is an extension of the Write Byte Protocol.

7.12 Block Read The Block Read is used to read multiple data bytesfrom a group of contiguous registers, as shown inTable 7-5. It is an extension of the Read Byte Protocol.

TABLE 7-2: WRITE BYTE PROTOCOL

START Slave Address WR ACK Reg. Addr. ACK Register Data ACK STOP

1 → 0 YYYY_YYY 0 0 XXh 0 XXh 0 0 → 1

TABLE 7-3: READ BYTE PROTOCOLSTART Slave Address WR ACK Register Address ACK

1→0 YYYY_YYY 0 0 XXh 0

START Slave Address RD ACK Register Data NACK STOP1 →0 YYYY_YYY 1 0 XXh 1 0 → 1

Note: The Block Write and Block Read protocolsrequire that the address pointer be auto-matically incremented. For a write com-mand, the address pointer will beautomatically incremented when the ACKis sent to the host. There are no over orunder bound limit checking and theaddress pointer will wrap around from FFhto 00h if necessary

TABLE 7-4: BLOCK WRITE PROTOCOL

START Slave Address WR ACK Register Address ACKRepeat N Times

STOPRegister Data ACK

1 → 0 YYYY_YYY 0 0 XXh 0 XXh 0 0 → 1

TABLE 7-5: BLOCK READ PROTOCOL

START Slave Address WR ACK Register Address ACK

1→0 YYYY_YYY 0 0 XXh 0

START Slave Address RD ACKRepeat N Times

Register Data NACK STOPRegister Data ACK

1→0 YYYY_YYY 1 0 XXh 0 XXh 1 0 → 1


UCS2113

7.13 SMBus Send ByteThe Send Byte protocol is used to set the internaladdress register pointer to the correct address location.No data is transferred during the Send Byte protocol asshown in Table 7-6.

7.14 SMBus Receive ByteThe Receive Byte protocol is used to read data from aregister when the internal register address pointer isknown to be at the right location (e.g. set via SendByte). This is used for consecutive reads of the sameregister as shown in Table 7-7.

7.14.1 STAND-ALONE OPERATING MODEStand-Alone mode allows the UCS2113 to operatewithout active SMBus/I2C communications.Stand-Alone mode can be enabled by connecting apull-down resistor greater or equal to 47 k on theCOMM_ILIM pin as shown in Table 5-3.The SMCLKpin should be tied to ground in this mode.

Note: The SMBus Send Byte command isexpected to be followed by the SMBusReceive Byte command. When twoSMbus Send Byte commands are sent ina row, the first command receives an ACKand will be processed by the UCS2113,but the second command receives aNACK and will be ignored.

TABLE 7-6: SEND BYTE PROTOCOLSTART Slave Address WR ACK Register Address ACK STOP

1→0 YYYY_YYY 0 0 XXh 0 0 → 1

TABLE 7-7: RECEIVE BYTE PROTOCOLSTART Slave Address RD ACK Register Data NACK STOP

1→0 YYYY_YYY 1 0 XXh 1 0 → 1


UCS2113

NOTES:


UCS2113

8.0 REGISTER DESCRIPTIONThe registers shown in Table 8-1 are accessiblethrough the SMBus or I2C. An entry of ‘—’ indicatesthat the bit is not used. Writing to these bits will have noeffect and reading these bits will return ‘0’. Writing to areserved bit may cause unexpected results andreading from a reserved bit will return either ‘1’ or ‘0’ asindicated in the bit description. While in the Sleep state,the UCS2113 will retain configuration and chargerationing data as indicated in the text. If a register doesnot indicate that data will be retained in the Sleeppower state, this information will be lost when theUCS2113 enters the Sleep power state.

TABLE 8-1: REGISTER SET IN HEXADECIMAL ORDERRegister Address Register Name R/W Function

Default Value

Page No.

00h Port 1 Current Measurement R Stores the current measurement for Port 1 00h 3801h Port 2 Current Measurement R Stores the current measurement for Port 2 00h 3802h Port Status R Indicates Port and general status 00h 3903h Interrupt Status1 See Text Indicates why ALERT# pin asserted for Port 1 00h 4004h Interrupt Status2 See Text Indicates why ALERT# pin asserted for Port 2 00h 420Fh General Status1 R/R-C Indicates General Status for Port 1 00h 4410h General Status2 R/R-C Indicates General Status for Port 2 00h 4511h General Configuration1 R/W Controls basic functionality for Port 1 06h 4612h General Configuration2 R/W Controls basic functionality for Port 2 02h 4713h General Configuration3 R/W Controls other functionality 60h 4814h Current Limit R/W Controls/Displays MAX Current Limit per port 00h 4915h Auto-Recovery Configuration R/W Controls the Auto-Recovery functionality 2Ah 5016h Port 1 Total Accumulated

Charge High ByteR Stores the total accumulated charge

delivered high byte, Port 100h 51

17h Port 1 Total Accumulated Charge Middle High Byte

R Stores the total accumulated charge delivered middle high byte, Port 1

00h 51

18h Port 1 Total Accumulated Charge Middle Low Byte

R Stores the total accumulated charge delivered middle low byte, Port 1

00h 51

19h Port 1 Total Accumulated Charge Low Byte

R Stores the total accumulated charge delivered low byte, Port 1

00h 51

1Ah Port 2 Total Accumulated Charge High Byte

R Stores the total accumulated charge delivered high byte, Port 2

00h 52

1Bh Port 2 Total Accumulated Charge Middle High Byte

R Stores the total accumulated charge delivered middle high byte, Port 2

00h 52

1Ch Port 2 Total Accumulated Charge Middle Low Byte

R Stores the total accumulated charge delivered middle low byte, Port 2

00h 52

1Dh Port 2 Total Accumulated Charge Low Byte

R Stores the total accumulated charge delivered low byte, Port 2

00h 52

1Eh Port 1 Charge Rationing Threshold High Byte

R/W Sets the maximum allowed charge that will be delivered to Port 1

FFh 53

1Fh Port 1 Charge Rationing Threshold Low Byte


FFh 53

20h Port 2 Charge Rationing Threshold High Byte


FFh 53


UCS2113

8.1 Current Measurement RegisterThe Current Measurement register stores themeasured current value delivered to the portabledevice (IBUS). This value is updated continuously whilethe device is in the Active power state.

21h Port 2 Charge Rationing Threshold Low Byte


FFh 53

22h Ration Configuration R/W Controls Charge Ration Functionality 11h 5423h Port 1 Current Limit Behavior R/W Controls the Current Limiting Behavior (CC

Mode Region 2) for Port 196h 55

24h Port 2 Current Limit Behavior R/W Controls the Current Limiting Behavior (CC Mode Region 2) for Port 2

96h 55

FDh Product ID R Stores a fixed value that identifies each product

E1h 56

FEh Manufacturer ID R Stores a fixed value that identifies Microchip 5Dh 56FFh Revision R Stores a fixed value that represents the

revision number81h 57

TABLE 8-1: REGISTER SET IN HEXADECIMAL ORDER (CONTINUED)Register Address Register Name R/W Function

Default Value

Page No.

REGISTER 8-1: PORTS 1 AND 2 CURRENT MEASUREMENT REGISTERS (ADDRESSES 00H, 01H)

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0CM(x)

bit 7 bit 0

Legend:R = Readable bit W = Writable bit U = Unimplemented bit-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 CM(x): Port X Current Measurement, where x=1 or 2 (address 00h for Port 1 and address 01h for Port 2).

Note 1: The bit weights are in mA,1 LSB = 13.3 mA (maximum value is 255 LSB corresponding to 3.4A). 2: This data will be cleared when the device enters the Sleep state. This data will also be cleared whenever

the port power switch is turned off (or any time that VBUS is discharged).


UCS2113

8.2 Status RegistersThe Status registers store bits that indicate the state ofthe ALERT# pins and if the ports operate in ConstantCurrent Mode.

REGISTER 8-2: PORT STATUS REGISTER (ADDRESS 02H)

R-0 R-0 R-0 R-0 U-0 U-0 R-x R-xALERT2_PIN ALERT1_PIN CC_MODE2 CC_MODE1 — — — —bit 7 bit 0

Legend:R = Readable bit W = Writable bit U = Unimplemented bit-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 ALERT2_PIN: Reflects the status of the ALERT#2 pin. This bit is set and cleared as the ALERT#2 pin changes states.1 = ALERT#2 Pin asserted (logic low)0 = ALERT#2 Pin not asserted

bit 6 ALERT1_PIN: Reflects the status of the ALERT#1 pin. This bit is set and cleared as the ALERT#1 pin changes states.1 = ALERT#1 Pin asserted (logic low)0 = ALERT#1 Pin not asserted

bit 5 CC_MODE2: Port 2 Constant Current Mode State1 = Port 2 in Constant Current mode0 = Port 2 operating normally

bit 4 CC_MODE1: Port 1 Constant Current Mode State1 = Port 1 in Constant Current mode0 = Port 1 operating normally

bit 3-0 Unimplemented


UCS2113

REGISTER 8-3: INTERRUPT STATUS 1 REGISTER (ADDRESS 03H)

R/W-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0ERR1 DISCH_ERR1 RESET KEEP_OUT1 TSD_HIGH OV_VOLT BACK_V1 OV_LIM1

bit 7 bit 0

Legend:R = Readable bit W = Writable bit U = Unimplemented bit C = Clear on Read-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 ERR1: Error Port 1 - Indicates that an error was detected on the VBUS1 pin and the device has entered the Error state. Writing this bit to ‘0’ will clear the Error state and allows the device to be returned to the Active state. When written to ‘0’, all error conditions are checked. If all error conditions have been removed, the UCS2113 returns to the Active state. This bit is set automatically by the UCS2113 when the Error state is entered. If any other bit is set in the Interrupt Status register (03h), the device will not leave the Error state.This bit is cleared automatically by the UCS2113 if the Auto-recovery fault handling functionality is active and no error conditions are detected. Likewise, this bit is cleared when the PWR_EN1 control is disabled (Note 1).1 = Port 1 in Error State0 = Port 1 in Active State (no errors detected)

bit 6 DISCH_ERR1: Discharge Error Port 1 - Indicates the device was unable to discharge Port1. This bit will be cleared when read if the error condition has been removed or if the ERR bit is cleared. This bit will cause the ALERT#1 pin to be asserted and the device to enter the Error state.1 = UCS2113 was unable to Discharge VBUS10 = No VBUS1 discharge error

bit 5 RESET: Indicates that the UCS2113 has just been reset and should be reprogrammed. This bit will be set at power-up. This bit is cleared when read or when the PWR_EN control is toggled. The ALERT# pins are not asserted when this bit is set. This data is retained in the Sleep state.1 = UCS2113 has just been reset0 = Reset did not occur

bit 4 KEEP_OUT1: Port 1 Minimum Keep-Out region - Indicates that the V-I output on the VBUS1 pin has dropped below VBUS_MIN. This bit will be cleared when read if the error condition has been removed or if the ERR1 bit is cleared. This bit will cause the ALERT#1 pin to be asserted and the device to enter the Error state.1 = VBUS1 < VBUS_MIN0 = VBUS1 > VBUS_MIN

bit 3 TSD_HIGH: Indicates that the internal temperature has exceeded TTSD_HIGH threshold and the device has entered the Error state. This bit will be cleared when read if the error condition has been removed or if the ERR1 bit is cleared. This bit will cause the ALERT#1and ALERT#2 pins to be asserted and the device to enter the Error state.1 = Internal die temperature has exceeded TTSD_HIGH0 = Internal die temperature has not exceeded TTSD_HIGH

bit 2 OV_VOLT: VS Overvoltage indicates that the VS voltage has exceeded the VS_OV threshold, and the device has entered the Error state. This bit will be cleared when read if the error condition has been removed or if the ERR1 bit is cleared. This bit will cause the ALERT#1 and ALERT#2 pins to be asserted and the device to enter the Error state.1 = VS > VS_OV0 = VS < VS_OV


UCS2113

bit 1 BACK_V1: Back-Bias Voltage Port 1 - Indicates that the VBUS1 voltage has exceeded the VS or VDD voltages by more than 150 mV. This bit will be cleared when read if the error condition has been removed or if the ERR1 bit is cleared. This bit will cause the ALERT#1 pin to be asserted and the device to enter the Error state.1 = VBUS1 > VS, or VBUS1 > VDD by more than 150 mV.0 = VBUS1 voltage has not exceeded the VS and VDD voltages by more than 150 mV.

bit 0 OV_LIM1: Over Current Limit Port 1 - Indicates that the IBUS current has exceeded both the ILIM thresh-old and the IBUS_R2MIN threshold settings for VBUS1. This bit will be cleared when read if the error con-dition has been removed or if the ERR1 bit is cleared. This bit will cause the ALERT#1 pin to be asserted and the device to enter the Error state.1 = Current Limit for Port 1 exceeded0 = Current Limit for Port 1 not exceeded

Note 1: Note that the ERR1 bit does not necessarily reflect the ALERT#1 pin status. The ALERT#1 pin may be cleared or asserted without the ERR1 bit changing states.

REGISTER 8-3: INTERRUPT STATUS 1 REGISTER (ADDRESS 03H) (CONTINUED)


UCS2113

REGISTER 8-4: INTERRUPT STATUS 2 REGISTER (ADDRESS 04H)

R/W-0 R/C-0 R-0 R/C-0 R/C-0 U-0 R/C-0 R/C-0ERR2 DISCH_ERR2 VS_LOW KEEP_OUT2 TSD_LOW — BACK_V2 OV_LIM2

bit 7 bit 0

Legend:R = Readable bit W = Writable bit U = Unimplemented bit C = Clear on Read-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 ERR2: Error Port 2 - Indicates that an error was detected on the VBUS1 pin and the device has entered the Error state. Writing this bit to a ‘0’ will clear the Error state and allows the device to be returned to the Active state. When written to ‘0’, all error conditions are checked. If all error conditions have been removed, the UCS2113 returns to the Active state. This bit is set automatically by the UCS2113 when the Error state is entered. If any other bit is set in the Interrupt Status register (04h), the device will not leave the Error state. This bit is cleared automatically by the UCS2113 if the auto-recovery fault handling functionality is active and no error conditions are detected. Likewise, this bit is cleared when the PWR_EN2 control is disabled (Note 1).1 = Port 2 in Error State0 = Port 2 in Active State (no errors detected)

bit 6 DISCH_ERR2: Discharge Error Port 2 - Indicates the device was unable to discharge Port2. This bit will be cleared when read if the error condition has been removed or if the ERR bit is cleared. This bit will cause the ALERT#2 pin to be asserted and the device to enter the Error state.1 = Device was unable to Discharge VBUS20 = No VBUS2 discharge error

bit 5 VS_LOW: Indicates that the VS voltage has fallen below the VS_UVLO threshold and both VBUS1 and VBUS2 port power switches are held off. This bit is cleared automatically when the VS voltage is above the VS_UVLO threshold.1 = VS voltage has fallen below the VS_UVLO0 = VS voltage is above VS_UVLO

bit 4 KEEP_OUT2: Port 2 Minimum Keep-out region - Indicates that the V-I output on the VBUS2 pin has dropped below VBUS_MIN. This bit will be cleared when read if the error condition has been removed or if the ERR2 bit is cleared. This bit will cause the ALERT#2 pin to be asserted and the device to enter the Error state.1 = VBUS2 < VBUS_MIN0 = VBUS2 > VBUS_MIN

bit 3 TSD_LOW: Indicates that the die temperature has exceeded the TTSD_LOW threshold and it is still abovethe TTSD_LOW - TTSD_LOW_HYST. This bit is cleared automatically when the die temperature is belowthe TTSD_LOW -TTSD_LOW_HYST. This bit will not cause the corresponding ALERT#1 and/orALERT#2 pins to be asserted and ERR1 and/or ERR2 bits to be set unless:

• a power switch operates in constant current mode• PWR_EN1 and/or PWR_EN2 controls transition from inactive to active• it is a power up situation and PWR_EN1 and/or PWR_EN2 pins are active.1 = Internal die temperature has exceeded TTSD_LOW 0 = Internal die temperature has not exceeded TTSD_LOW

bit 2 Unimplemented: Read as '0'bit 1 BACK_V2: Back-Bias Voltage Port 2 - Indicates that the VBUS2 voltage has exceeded the VS or VDD

voltages by more than 150 mV. This bit will be cleared when read if the error condition has been removed or if the ERR2 bit is cleared. This bit will cause the ALERT#2 pin to be asserted and the device to enter the Error state.1 = VBUS2 > VS, or VBUS2 > VDD by more than 150 mV0 = VBUS2 voltage has not exceeded the VS and VDD voltages by more than 150 mV


UCS2113

bit 0 OV_LIM2: Overcurrent Limit Port 2 - Indicates that the IBUS current has exceeded both the ILIM threshold and the IBUS_R2MIN threshold settings for VBUS2. This bit will be cleared when read if the error condition has been removed or if the ERR2 bit is cleared. This bit will cause the ALERT#2 pin to be asserted and the device to enter the Error state.1 = Current Limit for Port 2 exceeded0 = Current Limit for Port 2 not exceeded

Note 1: Note t

Date post:	05-Feb-2021
Category:	Documents
Upload:	others
View:	0 times
Download:	0 times

UCS2113 Data Sheet - Microchip Technologyww1.microchip.com/downloads/en/DeviceDoc/20005680A.pdf ·...

Documents