VERA OVERVIEW VALYDATE VERA IS A POWERFUL AND DETAILED SCHEMATIC REVIEWER. VERA FULLY INSPECTS 100% OF THE NETS ON A SCHEMATIC USING PRE-DEFINED CHECKS AND AN EXTENSIVE INTELLIGENT MODEL COMPONENT LIBRARY. Powered by Valydate’s patented verification engine, VERA saves design teams hundreds of hours of visual inspection and lab debug time by automating 100+ proprietary checks for each net within a schematic. These checks (listed on reverse) execute rapidly prior to your schematic freeze milestone, such that layout may commence with highest confidence of 1st pass success. Schematic Integrity Analysis is performed in parallel with design schematic capture. It can also be performed on electronic designs after they have been released into the market to improve the quality of the electronic design, to increase yield and to decrease product returns. KEY FEATURES ● Interoperability with all major schematic capture tools ● Multi-board interconnect analysis ● Full inspection of 100% of nets in a schematic ● 100+ built-in checks ● Intelligent results post-processing ● Extensive intelligent model library included with VERA ● Easy setup and intuitive operation ● Ability to create custom device models ● Automated custom FPGA model importation LVCMOS33 DRIVING SSTL15 RECEIVERS ON DAUGHTERBOARD1 PULLDOWN RESISTOR VALUE 100-OHM IS LESS THAN EXPECTED VALUE OF 240-OHM DIFFERENTIAL CONNECTION HAS POLARITY REVERSED BUS SIGNIFICANCE MISMATCH EXTERNAL RESISTORS VALUE (500-OHM)HIGHER THAN EXPECTED VALUE OF 50-OHM VTTA (0.9V) GREATER THAN EXPECTED VALUE OF 0.75V SSTL15_VREF (1.35V) GREATER THAN EXPECTED VALUE OF 0.75V GND PINS NOT CONNECTED TO GROUND SOURCE
Transcript
VERA OVERVIEWVALYDATE VERA IS A POWERFUL AND DETAILED SCHEMATIC REVIEWER. VERA FULLY INSPECTS 100% OF THE NETS ON A SCHEMATIC USING PRE-DEFINED CHECKS AND AN EXTENSIVE INTELLIGENT MODEL COMPONENT LIBRARY.
Powered by Valydate’s patented verification engine, VERA saves design teams hundreds of hours of visual inspection and lab debug time by automating 100+ proprietary checks for each net within a schematic. These checks (listed on reverse) execute rapidly prior to your schematic freeze milestone, such that layout may commence with highest confidence of 1st pass success.
Schematic Integrity Analysis is performed in parallel with design schematic capture. It can also be performed on electronic designs after they have been released into the market to improve the quality of the electronic design, to increase yield and to decrease product returns.
KEY FEATURES● Interoperability with all major schematic capture tools● Multi-board interconnect analysis● Full inspection of 100% of nets in a schematic● 100+ built-in checks● Intelligent results post-processing
● Extensive intelligent model library included with VERA● Easy setup and intuitive operation● Ability to create custom device models● Automated custom FPGA model importation
WARNING: INSUFFICIENT BULK
CAPACITANCE ON NET VCCC
WARNING: INSUFFICIENT DE-COUPLING
CAPACITANCE ON NET VCCB
DIFFERENTIAL IOS (ON DAUGHTERBOARD1)
CONNECTED TO SINGLE-ENDED IOS (ON MEZZANINE2)
OPEN-DRAIN PINS WITH NO EXTERNAL
PULLUPS ON BOARD
INCOMPATIBLE THRESHOLDS WITH
LVPECL DRIVING LVDS RECEIVER
LVCMOS33 DRIVING SSTL15 RECEIVERS
ON DAUGHTERBOARD1
PULLDOWN RESISTOR VALUE 100-OHM IS
LESS THAN EXPECTED VALUE OF 240-OHM
DIFFERENTIAL CONNECTION HAS
POLARITY REVERSED
BUS SIGNIFICANCE MISMATCH
EXTERNAL RESISTORS VALUE (500-OHM)HIGHER
THAN EXPECTED VALUE OF 50-OHM
CAPACITOR POLARITY REVERSED
VTTA (0.9V) GREATER THAN
EXPECTED VALUE OF 0.75V
SSTL15_VREF (1.35V) GREATER THAN
EXPECTED VALUE OF 0.75V
GND PINS NOT CONNECTED
TO GROUND SOURCE
KEY BENEFITSVERA SYSTEMICALLY IMPROVES THE BUSINESS PERFORMANCE OF ELECTRONIC DESIGN TEAMS. THIS SOLUTION FOCUSES ON THE EARLIEST POSSIBLE OPTIMIZATION OF DESIGN QUALITY, WHICH LEADS TO:
● Reduced hardware spins which lead to faster time-to-market● Reduction in development, testing and warranty costs● Faster integration to high yield manufacturing● Improved yield and decreased field returns● Superior product quality
● Pin Voltage Parametric Verification for maximum, minimum and logic thresholds● Bus flip errors (MSB to LSB, TX and RX errors)● Full Multi-Board and Backplane Interface Verification● Pin Function Compatibility Tests● Symbol Mismatch (to Datasheet)● Driver/Receiver Technology Matching● Diode Orientation Verification● Driver/Receiver Function Matching● Power/Ground/Open Collector/Drain Shorts ● Capacitor Decoupling Sufficiency Checks● Capacitor Voltage Derating (to client rules)● Redundant Resistors (on a net detection)● Open Collector/Drain Verification
SELECT EXAMPLES OF SCHEMATIC CHECKS PERFORMED● Poor Design Practice Checks (ie: using pull-ups, pull downs when needed...) ● Power/Ground Plane Connection Verification● Component Power Checks● Multiple or Missing Power Supplies (on a net)● Differential Pin Verification● Unconnected Nets or Bus Detection● Off-Board Nets Detection● Overloaded Pins Identification● Unconnected Mandatory Pins Identification● Nets Missing Driver● Nets Missing ReceiverAnd many more…
