High Speed Digital Systems LabSpring 2008

Students: Jenia Kuksin Alexander Milys

Instructor: Yossi Hipsh

Characterization Characterization PresentationPresentation

Spring 2008Spring 2008

Table of Contents

Project Overview Main Goal Experiment Array Experiments Requirement from students. Scope of Experiments System in more details Examples from final “Student Workbook” Time Schedule Conclusions(Expectations)

Project Overview

Defining and building equipment for high speed phenomena experiment, which allow students to understand all phenomenon and master in this field.

Equipment will contain ultra high speed driver and array of transmission lines onboard.

There will be 88 different experiment which can be chose.

Main GoalMain Goal

Building a new evaluation system for the HSDSL laboratory.

Learning System Integration Techniques.

Understanding High Speed Signal Phenomena.

Learning techniques for very high speed hardware implementation.

Learn a PCB design process.

Instructor

Student

ControllerController

Switching SystemSwitching System

Transmission Lines Array

Experiment Environment

System in more details

PulserPulser

S00narrow pulse1wide pulse

SignalSplitterSignalSplitter

S1Will be OE for splitters

TransmissionLines

36 lines

TransmissionLines

36 lines

TerminationZ(Load)

TerminationZ(Load)Z(Source)Z(Source)

AnalogSwitchesAnalog

SwitchesAnalog

SwitchesAnalog

Switches

S2ConnectsOne channel from 36To scope

S3ConnectsOne channel from 36To scope

36 36361

S5Control for MCP195 (jitter)

ControllerController

Reflection Phenomena Reflection is a well-studied transmission line effect. In high-speed system, reflection noise increases time delay and produces overshoot, undershoot and ringing.The root cause of reflection noise is the impedance discontinuity along the signal transmission path.

CrosstalkDue to electromagnetic coupling between signal traces and vias.

JitterJitter refers to deviation in time between edges of individual signals that are periodic.

SkewSkew is the difference between two or more signals in their delay at a specified voltage threshold.

Scope of Experiments

Match to MatchZo

ZoZo

Electric field

ZoZ ∞Zo

Electric field

ZoZ=0Zo

Electric field

ZoZ ≠ZoZo

Electric field

Match to Open

Match to Short

Match to Mismatch

Reflection PhenomenaReflection Phenomena

Zin≠Zo

Z ∞Zo

Electric field

Zin≠Zo

Z=0ZoElectric field

Zin≠Zo

Zout ≠ZoZo

Electric field

Zin

CZo

Electric field

Mismatch to Open

Mismatch to Mismatch

Mismatch to Short

Match to Capasitor

Reflection PhenomenaReflection Phenomena

Zin

LZo

Electric field

Match to Inductance

Reflection PhenomenaReflection Phenomena

Zo

ZoZo

Electric field

ZoZo L1M2

Crosstalk, caused by EM coupling between multiple transmission lines running parallel, is also a well-studied subject in Electromagnetic. It can cause noise pick up on the adjacent quiet signal lines that may lead to false logic switching. Crosstalk will also impact the timing on the active lines if multiple lines are switching simultaneously.

CrosstalkCrosstalk

SkewSkew

MC10EP195

Digital Control

Delay

JitterJitter

Jitter implementation

DigitallyControlled

Delay

DigitallyControlled

Delay

Signal input Signal output

ControllerController

LUTLUT

MC10EP195 (ECL standard) device perform time delay for a signal.Devise can be programmed to provide time delays for the signal in a range of 2.2ns-12.2ns with 10ps resolution.LUT will contain data for multiple gitter implementation (sinus, Gaussian…)

Outer project(Mony Group)

MC10EP195

Transmission Line 1

RS

RL

Transmission Line 2

RS

RL

Transmission Line 3

RS

RL

Transmission Line 4

RS

RL

1 2

3

4

1

2

3

4

Sw_source

Splitter

Transmission Line 36

RS

RL

Switch IN Switch OUT

54

54

12 nsec

0.5 nsec

Digital Controlled Delay

Controller

SW_source

SW_OUT

SW_IN

SW_195

Puser

Puser

System in more details

Pulse Generator

Specifications definitionOUTPUTS Short pulse width: 0.5 to 1 nSec Long pulse width: 10 to 13 nSec Rise/fall Time : ~250 pSec Pulses repetition: 0.1-1 µSec (1-10 MHz)INPUTS Function selection:

Control of the pulse width: 10pSec steps

Programmable

Fast Pulse

ModuleFunction selection

Short pulse (delta)

Long pulse (step)

Pulse Generator - Block diagram

SplitterMPC94551Oscillator

10MHzC01025

3.3V / 5V ECL 2-InputDifferential AND/NAND

Controller

3.3V ECL Programmable

Delay Chip

3.3V ECL Programmable

Delay Chip

One Shot

MC74LCX74DG

CMOS5V/3.3V

CMOS3.3V

MC100EP195

MC100EP195

MC100EP05

11

11

3

TranslatorMC100EPT20

TranslatorMC100EPT20

Splitter

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

1

5

4

3

2

6

10

9

8

7

14

13

12

11

16

15

R=50

R=50

18

17

Zload

L

Zo

R=15

R=15

R=15

R=15

R=15

R=15

R=15

R=15

R=15

19

23

22

21

20

24

27

26

25

Zload

L

Zo

R=100

R=100

R=100

R=100

R=100

R=100

R=100

R=100

R=100

28

32

31

30

29

33

36

35

34

Zload

L

Zo

Driver_1 Driver_2 Driver_3

Driver_1, Driver_2, Driver_3 are components of a Splitter module.All transmission lines get their signals from a driver.As can be seen Splitter block is split to three sub blocks, and can be recognized by source impedance.

Splitter will duplicate the signal from the original “Fast Pulser” and connect it to all transmission lines.

Analog switch

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

Dev1

Dev2

Dev3

Dev4

Dev5

Dev6

Dev7

6

Dev1

6

Dev2,3,4,5,6,7

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

R=50

Dev1

Dev2

Dev3

Dev4

Dev5

Dev6

Dev7

6

Dev1

6

Dev2,3,4,5,6,7

Those are switches that will allow to choose a specific transmission line from the set. Switches will allow to connect a chosen experiment

to the Scope .

*Switches will chose one of 36 lines.

Sw_in Sw_out

Description of Experiment Set

Requirement from student

Student will be asked to measure voltage amplitude and time parameters of the signal which is shown on the scope.

Student has to capture screen from the scope and insert it to final report in Word document.

Digital Oscilloscope CharacterizationDigital Oscilloscope Characterization

Hardware Analog Bandwidth (-3 dB) ≥1.4 GHz1.4 GHz

Sample RateSample Rate ≥ 2.8 GS/s2.8 GS/s

Input ChannelsInput Channels 44

3/

0.35dB

rise fall

bandwithT

/ 250rise fallT ps

Experiment description, as Experiment description, as they will appear in final they will appear in final booklet for studentsbooklet for students..

1

2

3

Time SheduleTime Shedule

Conclusion

Final system will allow future students to get familiar with HSD signals, understand all phenomenon and master in this field.