UltraRAM Readback and Writeback v1.0 LogiCORE IP Product Guide

UltraRAM Readback andWriteback v1.0

LogiCORE IP Product GuideVivado Design Suite

PG356 (v1.0) August 6, 2021

https://www.xilinx.com

Table of ContentsChapter 1: Introduction.............................................................................................. 4

Features........................................................................................................................................4IP Facts..........................................................................................................................................5

Chapter 2: Overview......................................................................................................6Navigating Content by Design Process.................................................................................... 6Core Overview..............................................................................................................................6Applications..................................................................................................................................7Unsupported Features................................................................................................................8Licensing and Ordering.............................................................................................................. 8

Chapter 3: Product Specification........................................................................... 9Performance and Resource Use................................................................................................9Port Descriptions.......................................................................................................................10

Chapter 4: Designing with the Core................................................................... 16General Design Guidelines.......................................................................................................16Clocking...................................................................................................................................... 17Resets..........................................................................................................................................17Protocol Description................................................................................................................. 17

Chapter 5: Design Flow Steps.................................................................................22Customizing and Generating the Core...................................................................................22Constraining the Core...............................................................................................................24Simulation.................................................................................................................................. 25Synthesis and Implementation................................................................................................25

Chapter 6: Example Design..................................................................................... 26Implementing the Example Design........................................................................................ 26Simulating the Example Design.............................................................................................. 27

Chapter 7: Test Bench.................................................................................................28

PG356 (v1.0) August 6, 2021 www.xilinx.comUltraRAM Read and Write Back v1.0 2Send Feedback


https://www.xilinx.com/about/feedback/document-feedback.html?docType=Product_Guide&docId=PG356&Title=UltraRAM%20Readback%20and%20Writeback%20v1.0&releaseVersion=1.0&docPage=2

Demonstration Test Bench...................................................................................................... 28

Appendix A: Upgrading............................................................................................. 30

Appendix B: Debugging.............................................................................................31Finding Help on Xilinx.com...................................................................................................... 31Debug Tools............................................................................................................................... 32

Appendix C: Additional Resources and Legal Notices............................. 33Xilinx Resources.........................................................................................................................33Documentation Navigator and Design Hubs.........................................................................33References..................................................................................................................................33Revision History......................................................................................................................... 34Please Read: Important Legal Notices................................................................................... 34




Chapter 1

IntroductionThe Xilinx® UltraRAM is a high-density synchronous memory belonging to the 16 nm/UltraScale+™ family. Unlike block RAMs, UltraRAMs do not support readback and initializationfeatures. The UltraRAM Readback and Writeback IP core provides an optimized solution forreadback and writeback. It can be customized using the Vivado® IP customizers in the IP catalog.

FeaturesFollowing are the features of the UltraRAM Readback and Writeback IP:

• UltraRAM Port B is used for readback and writeback

• Separate Read Once Command supported on port A

• CDC Synchronizer can be Configurable depending on the source of input clocks

• Below commands are supported in readback and writeback.

○ Start (Location Selection)

○ Write Once

○ Write Batch

○ Read Once

○ Read Once on both the Ports

○ Configurable Read Batch

○ Configurable Restore

○ Exit

Chapter 1: Introduction




IP FactsLogiCORE™ IP Facts Table

Core Specifics

Supported Device Family1 UltraScale+™ families

Supported User Interfaces N/A

Resources N/A

Provided with Core

Design Files Encrypted RTL

Example Design Verilog

Test Bench Verilog

Constraints File Xilinx Constraints File

Simulation Model Verilog

Supported S/W Driver N/A

Tested Design Flows2

Design Entry Not Provided

Simulation For supported simulators, see the Xilinx Design Tools: Release Notes Guide.

Synthesis Not Provided

Support

Release Notes and Known Issues Master Answer Record: 75326

All Vivado IP Change Logs Master Vivado IP Change Logs: 72775

Xilinx Support web page

Notes:1. For a complete list of supported devices, see the Vivado® IP catalog.2. For the supported versions of third-party tools, see the Xilinx Design Tools: Release Notes Guide.

Chapter 1: Introduction


https://www.xilinx.com/cgi-bin/docs/rdoc?v=2021.1;t=vivado+install+guide

https://www.xilinx.com/support/answers/75326.html


https://www.xilinx.com/support

https://www.xilinx.com/cgi-bin/docs/rdoc?v=2021.1;t=vivado+install+guide



Chapter 2

Overview

Navigating Content by Design ProcessXilinx® documentation is organized around a set of standard design processes to help you findrelevant content for your current development task. All Versal™ ACAP design process DesignHubs can be found on the Xilinx.com website. This document covers the following designprocesses:

• Hardware, IP, and Platform Development: Creating the PL IP blocks for the hardwareplatform, creating PL kernels, functional simulation, and evaluating the Vivado® timing,resource use, and power closure. Also involves developing the hardware platform for systemintegration. Topics in this document that apply to this design process include:

• Port Descriptions

• Clocking

• Resets

• Customizing and Generating the Core

• Chapter 6: Example Design

Core OverviewThis product guide describes features of the Xilinx® UltraRAM Readback and WritebackLogiCORE™ IP and the functionality of the various commands in the design. In addition, the coreinterface and its customization options are defined in the following sections.

Chapter 2: Overview


https://www.xilinx.com/support/documentation-navigation/design-hubs.html

https://www.xilinx.com/support/documentation-navigation/design-hubs.html



Figure 1: Core Overview

URAM Readback

Cascade Inputs

Port A Outputs

Port B Outputs

Cascade Outputs

CCLK

VLD

DI

ConfigurationInterface

Port B Inputs

Sleep

CLK

Port A Inputs

URAM_LOCATION

X23250-121420

The IP primitive (URAM288_RDB) that implements the readback and writeback for UltraRAM isshown in the core overview diagram. There are additional input ports apart from the originalUltraRAM primitive, DI [31:0], VLD and CCLK, which are connected directly to theUSR_ACCESSE2 primitive. The URAM_LOCATION port provides the location/number for theUltraRAM and this can be checked while enabling WB/RB access. To provide the status of the IP,other configuration signals (CFGMODE and CFGBUSY) are generated in the IP. The UltraRAMReadback and Writeback LogiCORE IP core includes an instance of the URAM288 block and usesPort B for readback and writeback functions. The MUXes are configured to select the user logicto use Port B.

The readback/writeback logic is independent of the configuration interface used and operates atthe configuration clock frequency.

ApplicationsThe UltraRAM Readback and Writeback LogiCORE™ IP core is used in applications such asemulation platforms.

Chapter 2: Overview

PG356 (v1.0) August 6, 2021 www.xilinx.comUltraRAM Read and Write Back v1.0 7

CFGMODE

CFGBUSY

Send Feedback



Unsupported FeaturesThe following features are not supported in the core:

• Cascade mode

• Sleep mode

• Error correction code (ECC)

• OREG/IREG pipeline registers

Licensing and OrderingThis Xilinx® LogiCORE™ IP module is provided at no additional cost with the Xilinx Vivado®

Design Suite under the terms of the Xilinx End User License.

For more information about this core, visit the UltraRAM Readback and Writeback LogiCORE IP product web page.

Information about other Xilinx® LogiCORE™ IP modules is available at the Xilinx IntellectualProperty page. For information about pricing and availability of other Xilinx LogiCORE IP modulesand tools, contact your local Xilinx sales representative.

Chapter 2: Overview


https://www.xilinx.com/cgi-bin/docs/rdoc?t=eula

https://www.xilinx.com/products/intellectual-property/uram-rdb.html

https://www.xilinx.com/products/intellectual-property.html

https://www.xilinx.com/products/intellectual-property.html

https://www.xilinx.com/about/contact.html



Chapter 3

Product SpecificationThe functional block diagram of the core is shown in the following figure.

Figure 2: Core Block Diagram

URAM RDB MUX Module

URAM288

MUX

MUX

CLK

PORT A

PORT B

CCLK

CFGMODE

DATA, VLD

ConfigurationInterface

Config_sel_a

Config_sel_b

DOUTA

URAM Readback FSM

DOUTB

New Data Restore B

Restore Data B

UserInterface

FSM

Flop Stage2

Flop Stage1

Pulse Sync

Last Read Addr Port B

CFGBUSY

X23249-010621

Performance and Resource UsePerformance and resource utilization for the UltraRAM Readback and Writeback LogiCORE™ IPvaries depending on the configuration and features selected during core customization. Thefollowing table lists the performance and resource values for the default configuration.

Chapter 3: Product Specification




Table 1: Performance and Resource Use

ConfigurationResources Performance

LUTs FFs URAMs Max. Frequency(MHz)

Default Configuration 360 497 1 350

Port DescriptionsThe core interfaces are shown in the following figure.





Figure 3: Core Ports

URAM Readback IP

DIN_A

ADDR_A

EN_A

RDB_WR_A

BWE_A

INJECT_SBITERR_A

INJECT_DBITERR_A

OREG_CE_A

OREG_ECC_CE_A

RST_A

CLK

SLEEP

DIN_B

ADDR_B

EN_B

RDB_WR_B

BWE_B

INJECT_SBITERR_B

INJECT_DBITERR_B

OREG_CE_B

OREG_ECC_CE_B

RST_B

CCLK

VLD

DI

DOUT_A

SBITERR_A

DBITERR_A

RDACCESS_A

DOUT_B

SBITERR_B

DBITERR_B

RDACCESS_B

CAS_OUT_RDACCESS_B

CAS_OUT_DBITERR_B

CAS_OUT_SBITERR_B

CAS_OUT_BW

E_B

CAS_OUT_RDB_W

R_B

CAS_OUT_EN

_B

CAS_OUT_ADDR_B

CAS_OUT_DO

UT_B

CAS_OUT_DIN

_B

CAS_OUT_RDACCESS_A

CAS_OUT_DBITERR_A

CAS_OUT_SBITERR_A

CAS_OUT_BW

E_A

CAS_OUT_RDB_W

R_A

CAS_OUT_EN

_A

CAS_OUT_ADDR_A

CAS_OUT_DO

UT_A

CAS_OUT_DIN

_ACAS_IN

_DIN_A

CAS_IN_DO

UT_A

CAS_OUT_ADDR_A

CAS_IN_EN

_A

CAS_IN_RDB_W

R_A

CAS_IN_BW

E_A

CAS_IN_SBITERR_A

CAS_IN_DBITERR_A

CAS_IN_RDACCESS_A

CAS_IN_DIN

_B

CAS_IN_DO

UT_B

CAS_OUT_ADDR_B

CAS_IN_EN

_B

CAS_IN_RDB_W

R_B

CAS_IN_BW

E_B

CAS_IN_SBITERR_B

CAS_IN_DBITERR_B

CAS_IN_RDACCESS_B

URAM_LOCATION

CFGMODE

CFGBUSY

X23246-121420





Interface Ports (No Cascade)Table 2: Interface Ports (No Cascade)

Port Name I/O Width DescriptionCLK I 1 UltraRAM clock source

SLEEP I 1 Dynamic power gating control

Port A Interface

ADDR_A I 23 Port A address. ADDR_A[22:12] are only used incascade mode.

EN_A I 1 Port A enable. Enables or disables the read/writeaccess to the block RAM memory core.

RDB_WR_A I 1 Port A read or write mode input select. Read (BAR)is active-Low (0 = read and 1 = write).

BWE_A I 9 Port A byte write enable.

DIN_A I 72 Port A write data in.

INJECT_SBITERR_A I 1 Port A single-bit error injection during write.

INJECT_DBITERR_A I 1 Port A double-bit error injection during write.

OREG_CE_A I 1 Port A SRAM array core block read output pipelineregister CLK enable.

OREG_ECC_CE_A I 1 Port A ECC decoder output pipeline register CLKenable.

RST_A I 1 Asynchronous or synchronous reset for port Aoutput registers. Reset has priority over CE.

DOUT_A O 72 Port A read data out.

RDACCESS_A O 1 Port A read status output.

SBITERR_A O 1 Port A single-bit error output status.

DBITERR_A O 1 Port A double-bit error output status.

Port B Interface

ADDR_B I 23 Port B address. ADDR_B[22:12] are only used incascade mode.

EN_B I 1 Port B enable. Enables or disables the read/writeaccess to the block RAM memory core.

BWE_B I 9 Port B byte write enable.

DIN_B I 72 Port B write data in.

INJECT_SBITERR_B I 1 Port B single-bit error injection during write.

INJECT_DBITERR_B I 1 Port B double-bit error injection during write.

OREG_CE_B I 1 Port B SRAM array core block read output pipelineregister CLK enable.

OREG_ECC_CE_B I 1 Port B ECC decoder output pipeline register CLKenable.

RST_B I 1 Asynchronous or synchronous reset for port Boutput registers. Reset has priority over CE.

DOUT_B O 72 Port B read data out.

RDACCESS_B O 1 Port B read status output.

SBITERR_B O 1 Port B single-bit error output status.





Table 2: Interface Ports (No Cascade) (cont'd)

Port Name I/O Width DescriptionDBITERR_B O 1 Port B double-bit error output status.

Additional PortsTable 3: Additional Ports

Port Name I/O Width DescriptionConfiguration Interface

CCLK I 1 Configuration Clock. Entire read/writeback works onthis clock.

DI I 32 Configuration Data Interface

VLD I 1 Configuration valid to indicate the valid data on DI.

URAM_LOCATION I 22 Location of the URAM instance ID.In the start command if

Sync_Word = AA, IP enabled for WB/RB access.Sync_Word = AC, IP enabled for WB/RB accessonly if Location Instance ID matches withURAM_LOCATION

CFGMODE O 1 Configuration Mode enable. Indicates the IP isenabled for WB/RB access.

CFGBUSY O 1 Configuration Busy. Indicates that the IP is busy inprocessing WB/RB commands when theConfiguration mode is enabled.

Interface Ports (Cascade)Table 4: Interface Ports (Cascade)

Port Name I/O Width DescriptionPort A Cascade Interface

CAS_IN_ADDR_A I 23 Port A input address input. In cascade mode,connect this port to CAS_OUT_ADDR_A.

CAS_IN_EN_A I 1 Port A input enable input. In cascade mode connectthis port to CAS_OUT_EN_A.

CAS_IN_BWE_A I 9 Port A input write mode port byte write enable. Incascade mode, connect this port toCAS_OUT_BWE_A.

CAS_IN_RDB_WR_A I 1 Port A input read/write mode select. In cascademode, connect this port to CAS_OUT_RDB_WR_A.

CAS_IN_DIN_A I 72 Port A input write mode. In cascade mode, connectthis port to CAS_OUT_DIN_A.

CAS_IN_DOUT_A I 72 Port A input read mode data output. In cascademode, connect this port to CAS_OUT_DOUT_A.

CAS_IN_RDACCESS_A I 1 Port A input read mode read status. In cascademode, connect this port to CAS_OUT_RDACCESS_A.





Table 4: Interface Ports (Cascade) (cont'd)

Port Name I/O Width DescriptionCAS_IN_SBITERR_A I 1 Port A input read mode single-bit error flag input. In

cascade mode, connect this port toCAS_OUT_SBITERR_A.

CAS_IN_DBITERR_A I 1 Port A input read mode double-bit error flag input.In cascade mode, connect this port toCAS_OUT_SBITERR_A.

CAS_OUT_ADDR_A O 23 Port A output address. In cascade mode, connectthis port to CAS_IN_ADDR_A.

CAS_OUT_EN_A O 1 Port A output enable. In cascade mode, connect thisport to CAS_IN_EN_A.

CAS_OUT_RDB_WR_A O 1 Port A output read/write mode select. In cascademode, connect this port to CAS_IN_RDB_WR_A.

CAS_OUT_BWE_A O 9 Port A output write mode byte write enable. Incascade mode, connect this port to CAS_IN_BWE_A.

CAS_OUT_DIN_A O 72 Port A output write mode data. In cascade mode,connect this port to CAS_IN_DIN_A.

CAS_OUT_DOUT_A O 72 Port A output read mode data. In cascade mode,connect this port to CAS_IN_DOUT_A.

CAS_OUT_RDACCESS_A O 1 Port A output read mode read status flag. Incascade mode, connect this port toCAS_IN_RDACCESS_A.

CAS_OUT_SBITERR_A O 1 Port A output read single-bit error flag. In cascademode, connect this port to CAS_IN_SBITERR_A.

CAS_OUT_DBITERR_A O 1 Port A output read mode double-bit error flag. Incascade mode, connect this port toCAS_IN_DBITERR_A.

Port B Cascade Interface

CAS_IN_ADDR_B I 23 Port B input address input. In cascade mode,connect this port to CAS_OUT_ADDR_B.

CAS_IN_EN_B I 1 Port B input enable input. In cascade mode, connectthis port to CAS_OUT_EN_B.

CAS_IN_BWE_B I 9 Port B input write mode port byte write enable. Incascade mode, connect this port toCAS_OUT_BWE_B.

CAS_IN_RDB_WR_B I 1 Port B input read/write mode select. In cascademode, connect this port to CAS_OUT_RDB_WR_B.

CAS_IN_DIN_B I 72 Port B input write mode. In cascade mode, connectthis port to CAS_OUT_DIN_B.

CAS_IN_DOUT_B I 72 Port B input read mode data output. In cascademode, connect this port to CAS_OUT_DOUT_B.

CAS_IN_RDACCESS_B I 1 Port B input read mode read status. In cascademode, connect this port to CAS_OUT_RDACCESS_B.

CAS_IN_SBITERR_B I 1 Port B input read mode single-bit error flag input. Incascade mode, connect this port toCAS_OUT_SBITERR_B.

CAS_IN_DBITERR_B I 1 Port B input read mode double-bit error flag input.In cascade mode, connect this port toCAS_OUT_DBITERR_B.

CAS_OUT_ADDR_B O 23 Port B output address. In cascade mode, connectthis port to CAS_IN_ADDR_B.





Table 4: Interface Ports (Cascade) (cont'd)

Port Name I/O Width DescriptionCAS_OUT_EN_B O 1 Port A output enable. In cascade mode, connect this

port to CAS_IN_EN_B.

CAS_OUT_BWE_B O 9 Port B output write mode byte write enable. Incascade mode, connect this port to CAS_IN_BWE_B.

CAS_OUT_RDB_WR_B O 1 Port B output read/write mode select. In cascademode, connect this port to CAS_IN_RDB_WR_B.

CAS_OUT_DIN_B O 72 Port B output write mode data. In cascade mode,connect this port to CAS_IN_DIN_B.

CAS_OUT_DOUT_B O 72 Port B output read mode data. In cascade mode,connect this port to CAS_IN_DOUT_B.

CAS_OUT_RDACCESS_B O 1 Port B output read mode read status flag. Incascade mode, connect this port toCAS_IN_RDACCESS_B.

CAS_OUT_SBITERR_B O 1 Port B output read single-bit error flag. In cascademode, connect this port to CAS_IN_SBITERR_B.

CAS_OUT_DBITERR_B O 1 Port B output read mode double-bit error flag. Incascade mode, connect this port toCAS_IN_DBITERR_B.





Chapter 4

Designing with the CoreThis section includes guidelines and additional information to facilitate designing with the core.

General Design GuidelinesThe basic blocks in UltraRAM Readback and Writeback LogiCORE™ IP are URAM288 (UltraRAMPrimitive), URAM RDB_WRB_FSM, and URAM RDB_MUX.

Use the Example DesignEach instance of the uram_rd_back core created by the Vivado design tool is delivered with anexample design that can be implemented in a device and then simulated. This design can be usedas a starting point for your own design or can be used to sanity-check your application in theevent of difficulty. See the Example Design content for information about using and customizingthe example designs for the core.

Related Information

Example Design

Registering SignalsTo simplify timing and increase system performance in a programmable device design, keep allinputs and outputs registered between the user application and the core. This means that allinputs and outputs from the user application should come from, or connect to, a flip-flop. Whileregistering signals might not be possible for all paths, it simplifies timing analysis and makes iteasier for the Xilinx® tools to place and route the design.

Recognize Timing Critical SignalsThe constraints provided with the example design identify the critical signals and timingconstraints that should be applied.

Chapter 4: Designing with the Core




Make Only Allowed ModificationsYou should not modify the core. Any modifications can have adverse effects on system timingand protocol compliance. Supported user configurations of the core can only be made byselecting the options in the customization IP dialog box when the core is generated.

ClockingThe IP core operates with two clocks, CLK and CCLK. By default, UltraRAM memory is accessedusing the user clock (CLK). While accessing memory contents from backdoor, the configurationclock, (CCLK) is used.

ResetsThe IP core uses reset for both the ports of UltraRAM, namely RST_A and RST_B. Writeback orReadback is implemented to use on Port B of URAM primitive where RST_B can be used as resetfor Configuration Access.

Protocol Description

URAM288 (UltraRAM Primitive)The UltraRAM URAM288 primitive is the basic building block for all UltraRAM configurations.The URAM288 primitive supports all possible configurations including cascade and ECC. TheURAM288 primitive is shown in the following figure.





Figure 4: UltraRAM URAM288 Primitive

DIN_A

ADDR_A

EN_A

RDB_WR_A

BWE_A

INJECT_SBITERR_A

INJECT_DBITERR_A

OREG_CE_A

OREG_ECC_CE_A

RST_A

SLEEP

CLK

DIN_B

ADDR_B

EN_B

RDB_WR_B

BWE_B

INJECT_SBITERR_B

INJECT_DBITERR_B

OREG_CE_B

OREG_ECC_CE_B

RST_B

72

23

9DOUT_A

SBITERR_A

DBITERR_A

RDACCESS_A

DOUT_B

SBITERR_B

DBITERR_B

RDACCESS_B

72

72

72

23

9

CAS_OUT_DIN

_A

CAS_OUT_DO

UT_A

CAS_OUT_ADDR_A

CAS_OUT_EN

_A

CAS_OUT_RDB_W

R_A

CAS_OUT_BW

E_A

CAS_OUT_SBITERR_A

CAS_OUT_DBITERR_A

CAS_OUT_RDACCESS_A

CAS_OUT_DIN

_B

CAS_OUT_DO

UT_B

CAS_OUT_ADDR_B

CAS_OUT_EN

_B

CAS_OUT_RDB_W

R_B

CAS_OUT_BW

E_B

CAS_OUT_SBITERR_B

CAS_OUT_DBITERR_B

CAS_OUT_RDACCESS_B

72 72 23

72 72

CAS_IN_DIN

_A

CAS_IN_DO

UT_A

CAS_IN_ADDR_A

CAS_IN_EN

_A

CAS_IN_RDB_W

R_A

CAS_IN_BW

E_A

CAS_IN_SBITERR_A

CAS_IN_DBITERR_A

CAS_IN_RDACCESS_A

CAS_IN_DIN

_B

CAS_IN_DO

UT_B

CAS_IN_ADDR_B

CAS_IN_EN

_B

CAS_IN_RDB_W

R_B

CAS_IN_BW

E_B

CAS_IN_SBITERR_B

CAS_IN_DBITERR_B

CAS_IN_RDACCESS_B

7272 239 9

9 923 2372 72

X23367-101519





URAM RDB MUXThe URAM RDB MUX is used to select the URAM288 primitive inputs between user inputs andthe configuration inputs generated from the URAM RDB FSM. When accessing the memory fromthe configuration interface, both user ports are disabled from accessing the memory.

UltraRAM Readback Writeback FSMThe main block of the IP is the UltraRAM readback writeback finite state machine (FSM) whichcontrols the readback and writeback operations to the UltraRAM. This block is in the separateclock domain and completely independent from the user logic. It operates with the configurationclock (CCLK) which is separate from the user clock (CLK).

Based on the data value on data input (DI) interface, all the communication between the debughost and/or USER_ACCESS primitive and to the IP is performed through one of four differenttypes of frames as described below:

• Location frame (Type 10): This frame is sent by the debug hosts to select a specific UltraRAMbased on its XY location. All successive frames after the location frame targets the sameURAM until the exit command is sent. Location Frame is also called start frame.This is thestarting frame to the IP to enable IP for WB/RB access.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TYP SYNC_WORD URAM_LOC_XY

• SYNC_WORD: Sync_Word = 0xAA, IP enabled for WB/RB access. Sync_Word = AC, IPenabled for WB/RB access only if Location Frame (URAM_LOC_XY) matches withURAM_LOCATION input port.

• URAM_LOC_XY: URAM location number.

• Command frame (Type 11): This frame specifies one of the below commands and theUltraRAM address at which readback or writeback needs to be performed.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TYP CMD URAM_ADDR

11 0x6A, (0x7A-0x7F) (23-bit address)

• URAM_ADDR: Address (Starting Address) of the URAM location to access.

• CMD: Specifies type of the command.

CMD Type6A Read Once Port A

7A Read Once Port B

7B Read Batch Port B





CMD Type7C Write Once Port B

7D Write Batch Port B

7E Restore Port B

7F Exit

37* Read Once to Both the Ports

Note: The type of command identified by bits [29:23] from command frame for all commands exceptRead Once to both ports. Read once to Both the ports command identified by only [29:24] bits fromcommand frame and [23:0] bits used to select the address on each port ([23:12] bits to Port B addressand [11:0] bits to Port A address)

• Data frame (Type 00): This frame is typically sent after the command frame and specifies thedata to be written (in the case of Write Once or Write Batch Command).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TYP DATA

Note: The UltraRAM primitive supports 72-bit data. The FSM waits until the complete data is receivedfrom the configuration interface, that is, an UltraRAM data width of 72 bits (DI is for 32-bit out ofwhich 30 bits are actual data) is received. To write 72 bits (one write) to the memory, three datacommands from the configuration interface are needed so that a complete row of a memory can beaccessed. Inputs required for one write to the UltraRAM are generated by the UltraRAM readback FSMmodule after receiving the complete data (72- bit).

• Data End frame (Type 01): This frame is the last frame sent during a command sequence. Forexample, Number of Reads during Read Batch Command and the Write Sequence End duringWrite Batch Command.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TYP DATA END

Table 5: Readback/Writeback Commands and Latency

S.No Command Name Execution Latency in IP (No.of Clocks) Description

1 Start 2 Sync_Word = AA, IP enabled for WB/RB accessSync_Word = AC, IP enabled for WB/RB accessonly if Location Frame matches

2 Write Once 3 Clock Cycles from Last data Overall Command Execution: 6 Clock Cycles (ifall data commands are continuous)

3 Write Batch 3 Clock Cycles from data end Overall Command Execution: 4 + No. of Datacommands (if all data commands arecontinuous)

4 Read Once 3 Read Once Supported for both the ports (PortA/B)

5 Read Batch 4 + (N-1)*D N = Number of ReadsD = Delay between each read





Table 5: Readback/Writeback Commands and Latency (cont'd)

S.No Command Name Execution Latency in IP (No.of Clocks) Description

6 Restore 15 Restore command will perform "Read, Write,Read, Write" to the same URAM location (lastread address from Port B user interface)

7 Exit 3

8 Read Once on BothPorts

3 Read Once on both the ports with differentaddresses.

Notes:1. WB/RB access can be started with the Start command and end with the Exit command. All other commands in

between Start and Exit can be accessed in any order.

Restore Command Description

IP has the ability to store the last read address and data from the Port B user interface to restorethe same values on Port B output interface when Restore command is executed from backdooraccess. The following shows the sequence:

1. First Read to get the new value present in the URAM and restore this new value

2. First Write is to write the Old read value (last read data from the Port B user interface)

3. Second Read to present the restored read value (from the user interface)

4. Then Second Write to write the new data value again

Multi-URAM Configuration

In the multi-URAM configuration, the IP can be used in multi-instance configurations by sharingthe configuration interface. All or few URAM instances can be accessed for write/read back atthe same time.

• Accessing All URAM Instances: All instances connected to configuration interface can beselected by sending a start command with Sync_Word AA. All other commands received by allURAM instances will respond similarly and all instances can exit upon receiving Exit command.

• Accessing One or Few URAM Instances: Individual instances can be selected through theStart command (with Sync_Word = AC and URAM_LOC_XY == URAM_LOCATION). Othercommands can be received and processed by the instances which are enabled. Exit commandwill exit the write/read back access for all instances.





Chapter 5

Design Flow StepsThis section describes customizing and generating the core, constraining the core, and thesimulation, synthesis, and implementation steps that are specific to this IP core. More detailedinformation about the standard Vivado® design flows and the IP integrator can be found in thefollowing Vivado Design Suite user guides:

• Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994)

• Vivado Design Suite User Guide: Designing with IP (UG896)

• Vivado Design Suite User Guide: Getting Started (UG910)

• Vivado Design Suite User Guide: Logic Simulation (UG900)

Customizing and Generating the CoreThis section includes information about using Xilinx® tools to customize and generate the core inthe Vivado® Design Suite.

If you are customizing and generating the core in the Vivado IP integrator, see the Vivado DesignSuite User Guide: Designing IP Subsystems using IP Integrator (UG994) for detailed information. IPintegrator might auto-compute certain configuration values when validating or generating thedesign. To check whether the values do change, see the description of the parameter in thischapter. To view the parameter value, run the validate_bd_design command in the Tclconsole.

You can customize the IP for use in your design by specifying values for the various parametersassociated with the IP core using the following steps:

1. Select the IP from the IP catalog.

2. Double-click the selected IP or select the Customize IP command from the toolbar or right-click menu.

For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) and the VivadoDesign Suite User Guide: Getting Started (UG910).

Figures in this chapter are illustrations of the Vivado IDE. The layout depicted here might varyfrom the current version.

Chapter 5: Design Flow Steps


https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug994-vivado-ip-subsystems.pdf

https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug896-vivado-ip.pdf

https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug910-vivado-getting-started.pdf

https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug900-vivado-logic-simulation.pdf

https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug994-vivado-ip-subsystems.pdf


https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug910-vivado-getting-started.pdf



UltraRAM Readback IP Basic OptionsThe following figure shows a single page which defines the component name and providesconfiguration options for UltraRAM.

Figure 5: UltraRAM Readback Writeback Customize IP Dialog Box

• Enable Restore: Enables restore command support when selected. Default Value is True.

• Disable CDC Logic: Disables CDC logic between Read Back FSM and URAM Primitive. DefaultValue is False.

• Enable Read Batch: Enables Read Batch command Support when selected. Default Value isTrue.

• URAM Primitive Input Register: When selected, adds register stage at URAM Primitive inputs.Default Value is False.

User ParametersThe following table shows the relationship between the fields in the Vivado® IDE and theuserparameters (which can be viewed in the Tcl Console).





Table 6: User Parameters

Vivado IDE Parameter/ValueCross Ref to TableNote User Parameter/Value Default Value

Enable Restore ENABLE_RESTORE TrueDisable CDC Logic DISABLE_CDC FalseEnable Read Batch ENABLE_READ_BATCH TrueURAM Primitive Input Register URAM_INPUT_REGISTER False

For a detailed description of all other user parameters, see the UltraRAM attributes section in theUltraScale Architecture Memory Resources User Guide (UG573).

Output GenerationFor details, see the Vivado Design Suite User Guide: Designing with IP (UG896).

Constraining the CoreRequired Constraints

This section is not applicable for this IP core.

Device, Package, and Speed Grade Selections


Clock Frequencies


Clock Management


Clock Placement


Banking




https://www.xilinx.com/cgi-bin/docs/ndoc?t=user_guides;d=ug573-ultrascale-memory-resources.pdf




Transceiver Placement


I/O Standard and Placement


SimulationFor comprehensive information about Vivado® simulation components, as well as informationabout using supported third-party tools, see the Vivado Design Suite User Guide: Logic Simulation(UG900).

Synthesis and ImplementationFor details about synthesis and implementation, see the Vivado Design Suite User Guide: Designingwith IP (UG896).



https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug900-vivado-logic-simulation.pdf




Chapter 6

Example DesignThe following figure shows the example design for the UltraRAM Readback and Writeback IP. Forinformation on the VCU118-based reference design, see AR 75326.

Figure 6: Core Example Design

UserInterface

IOBs

URAM Read Backup IP

Core

Example Design

X23248-120320

The example design comprises the following:

• An instance of the UltraRAM Readback and Writeback LogiCORE™ IP.

During simulation, the core is instantiated as a black box. It is replaced during implementationwith the structural netlist model generated by the Vivado® IP catalog IP customizer for timingsimulation or a behavioral model for the functional simulation.

• Global clock buffers for top-level port clock signals.

Implementing the Example DesignTo implement the example design, follow these steps:

1. After generating a core, right-click on the generated core and click Open IP Example Design.

2. In the example project tab, click the Run Synthesis and Run Implementation options toimplement the example design.

Chapter 6: Example Design





Simulating the Example DesignThe UltraRAM Readback and Writeback IP core provides a quick way to simulate and observethe behavior of the core by using the provided example design. There are five differentsimulation types:

• Behavioral

• Post-Synthesis Functional

• Post-Synthesis Timing

• Post-Implementation Functional

• Post-Implementation Timing

Chapter 6: Example Design




Chapter 7

Test BenchThis chapter contains information about the test bench provided in the Vivado® Design Suite.The following figure shows a block diagram of the subsystem test bench.

Figure 7: UltraRAM Readback Test Bench

Test Bench Top

ClockGenerator

Checker

DataGenerator

ProtocolController

DataChecker

UserInterface

IOBs

URAM Read Backup IP

Core

Example Design

Test Bench Wrapper

X23247-120320

Demonstration Test Bench

Test Bench FunctionalityThe demonstration test bench is a Verilog-HDL file that can be used to exercise the exampledesign and the core itself. The test bench consists of the following:

• Clock generators

• Data generator module

Chapter 7: Test Bench




• Data verifier module

• Module to control data generator and verifier

The demonstration test bench in a core performs the following tasks:

• Input clock signals are generated.

• A reset is applied to the example design.

• Pseudo random data is generated and given as input to the UltraRAM Readback andWriteback IP.

Commands that are supported by the IP are verified in the following sequence:

1. Normal Writes to Port A.

2. Normal Reads to Port A and compare with the write data from previous step in exampledesign checker (dverif).

3. Normal Writes to Port B.

4. Normal Reads to Port B and compare with the write data from previous step in exampledesign checker (dverif).

5. Writeback/Readback Sequence performed from example design to configuration interface(DI, VLD):

a. Start Command. CFG_MODE signal asserts from IP and it will be the select signal forBUFGMUX in example design.

b. Set of Write Once Commands to Port B.

c. Write Batch Command (Write Data to multiple URAM locations) to Port B.

d. Set of Read Once Commands to Port B. Read data from IP compared with the datawritten through Write Once Commands.

e. Set of Read Once Commands to Port A.

f. Set of Read Once Commands to both the ports using command ('h37)

g. Read Batch Command (Read to multiple locations of URAM) to Port B. Read data from IPcompared with the data written through Write Batch Command.

h. Restore Command to Port B.

i. Exit Command.

Messages and WarningsWhen the functional or timing simulation has completed successfully, the test bench displays thefollowing message. It is safe to ignore this message.

Failure: Test Completed Successfully

Chapter 7: Test Bench




Appendix A

UpgradingThis appendix is not applicable for the first release of the core.

Appendix A: Upgrading




Appendix B

DebuggingThis appendix includes details about resources available on the Xilinx® Support website anddebugging tools.

Finding Help on Xilinx.comTo help in the design and debug process when using the core, the Xilinx Support web pagecontains key resources such as product documentation, release notes, answer records,information about known issues, and links for obtaining further product support. The XilinxCommunity Forums are also available where members can learn, participate, share, and askquestions about Xilinx solutions.

DocumentationThis product guide is the main document associated with the core. This guide, along withdocumentation related to all products that aid in the design process, can be found on the XilinxSupport web page or by using the Xilinx® Documentation Navigator. Download the XilinxDocumentation Navigator from the Downloads page. For more information about this tool andthe features available, open the online help after installation.

Answer RecordsAnswer Records include information about commonly encountered problems, helpful informationon how to resolve these problems, and any known issues with a Xilinx product. Answer Recordsare created and maintained daily ensuring that users have access to the most accurateinformation available.

Answer Records for this core can be located by using the Search Support box on the main Xilinxsupport web page. To maximize your search results, use keywords such as:

• Product name

• Tool message(s)

• Summary of the issue encountered

Appendix B: Debugging


https://www.xilinx.com/support.html

https://forums.xilinx.com/




https://www.xilinx.com/support/download.html





A filter search is available after results are returned to further target the results.

Master Answer Record for the Core

AR 75326.

Technical SupportXilinx provides technical support on the Xilinx Community Forums for this LogiCORE™ IP productwhen used as described in the product documentation. Xilinx cannot guarantee timing,functionality, or support if you do any of the following:

• Implement the solution in devices that are not defined in the documentation.

• Customize the solution beyond that allowed in the product documentation.

• Change any section of the design labeled DO NOT MODIFY.

To ask questions, navigate to the Xilinx Community Forums.

Debug ToolsThere are many tools available to address uram_rd_back design issues. It is important to knowwhich tools are useful for debugging various situations.

Vivado Design Suite Debug FeatureThe Vivado® Design Suite debug feature inserts logic analyzer and virtual I/O cores directly intoyour design. The debug feature also allows you to set trigger conditions to capture applicationand integrated block port signals in hardware. Captured signals can then be analyzed. Thisfeature in the Vivado IDE is used for logic debugging and validation of a design running in Xilinx®

devices.

The Vivado logic analyzer is used to interact with the logic debug LogiCORE IP cores, including:

• ILA 2.0 (and later versions)

• VIO 2.0 (and later versions)

See the Vivado Design Suite User Guide: Programming and Debugging (UG908).

Appendix B: Debugging





https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug908-vivado-programming-debugging.pdf



Appendix C

Additional Resources and LegalNotices

Xilinx ResourcesFor support resources such as Answers, Documentation, Downloads, and Forums, see XilinxSupport.

Documentation Navigator and Design HubsXilinx® Documentation Navigator (DocNav) provides access to Xilinx documents, videos, andsupport resources, which you can filter and search to find information. To open DocNav:

• From the Vivado® IDE, select Help → Documentation and Tutorials.

• On Windows, select Start → All Programs → Xilinx Design Tools → DocNav.

• At the Linux command prompt, enter docnav.

Xilinx Design Hubs provide links to documentation organized by design tasks and other topics,which you can use to learn key concepts and address frequently asked questions. To access theDesign Hubs:

• In DocNav, click the Design Hubs View tab.

• On the Xilinx website, see the Design Hubs page.

Note: For more information on DocNav, see the Documentation Navigator page on the Xilinx website.

ReferencesThese documents provide supplemental material useful with this guide:

Appendix C: Additional Resources and Legal Notices




https://www.xilinx.com/cgi-bin/docs/ndoc?t=design+hubs

https://www.xilinx.com/cgi-bin/docs/rdoc?t=docnav



1. UltraScale Architecture Memory Resources User Guide (UG573)

2. UltraScale Architecture Libraries Guide (UG974)

3. UltraScale Architecture Clocking Resources User Guide (UG572)

Revision HistoryThe following table shows the revision history for this document.

Section Revision Summary08/06/2021 Version 1.0

Core Overview Updated figure with CFGMODE and CGFBUSY configurationsignals.

UltraRAM Readback Writeback FSM Updated CMD and Readback/Writeback Commands andLatency.

Chapter 5: Design Flow Steps • Updated UltraRAM Readback Writeback Customize IPDialog figure and added description.

• Updated User Parameters.

Test Bench Functionality Added 'h37 command.

Please Read: Important Legal NoticesThe information disclosed to you hereunder (the "Materials") is provided solely for the selectionand use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials aremade available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES ANDCONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TOWARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANYPARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, includingnegligence, or under any other theory of liability) for any loss or damage of any kind or naturerelated to, arising under, or in connection with, the Materials (including your use of theMaterials), including for any direct, indirect, special, incidental, or consequential loss or damage(including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of anyaction brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinxhad been advised of the possibility of the same. Xilinx assumes no obligation to correct anyerrors contained in the Materials or to notify you of updates to the Materials or to productspecifications. You may not reproduce, modify, distribute, or publicly display the Materialswithout prior written consent. Certain products are subject to the terms and conditions ofXilinx's limited warranty, please refer to Xilinx's Terms of Sale which can be viewed at https://


PG356 (v1.0) August 6, 2021 www.xilinx.comUltraRAM Read and Write Back v1.0 34

01/21/2021 Version 1.0

Initial release. N/A

Send Feedback

https://www.xilinx.com/cgi-bin/docs/ndoc?t=user_guides;d=ug573-ultrascale-memory-resources.pdf

https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug974-vivado-ultrascale-libraries.pdf

https://www.xilinx.com/cgi-bin/docs/ndoc?t=user_guides;d=ug572-ultrascale-clocking.pdf

https://www.xilinx.com/legal.htm#tos



www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms containedin a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe orfor use in any application requiring fail-safe performance; you assume sole risk and liability foruse of Xilinx products in such critical applications, please refer to Xilinx's Terms of Sale which canbe viewed at https://www.xilinx.com/legal.htm#tos.

AUTOMOTIVE APPLICATIONS DISCLAIMER

AUTOMOTIVE PRODUCTS (IDENTIFIED AS "XA" IN THE PART NUMBER) ARE NOTWARRANTED FOR USE IN THE DEPLOYMENT OF AIRBAGS OR FOR USE IN APPLICATIONSTHAT AFFECT CONTROL OF A VEHICLE ("SAFETY APPLICATION") UNLESS THERE IS ASAFETY CONCEPT OR REDUNDANCY FEATURE CONSISTENT WITH THE ISO 26262AUTOMOTIVE SAFETY STANDARD ("SAFETY DESIGN"). CUSTOMER SHALL, PRIOR TO USINGOR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE PRODUCTS, THOROUGHLY TESTSUCH SYSTEMS FOR SAFETY PURPOSES. USE OF PRODUCTS IN A SAFETY APPLICATIONWITHOUT A SAFETY DESIGN IS FULLY AT THE RISK OF CUSTOMER, SUBJECT ONLY TOAPPLICABLE LAWS AND REGULATIONS GOVERNING LIMITATIONS ON PRODUCTLIABILITY.

Copyright

© Copyright 2019–2021 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Artix, Kintex, Spartan, Versal,Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in theUnited States and other countries. All other trademarks are the property of their respectiveowners.







Date post:	17-Feb-2022
Category:	Documents
Upload:	others
View:	16 times
Download:	0 times

UltraRAM Readback and Writeback v1.0 LogiCORE IP Product Guide

Documents