UMC © 2014
UMC Provide Complete Solution for Design
Enablement, IP and Design Services
Enable Time to Market
IP
• Comprehensive IP portfolio
• IP customization to meet
special needs
Design Enablement
• PDK & DFM
• Design flow
• Customized support &
dedicated consultant
CPU Performance Opt. • POP / HPC solutions
• Hardening/consultant service
for product PPA
APR Service • In-house & design
service partners’ support
• On-site support
capability
2
UMC © 2014
Outline
• UMC Design Enablement and IP Solution
- Overview on UMC’s Offering
- Solution for IoT Application
- Solution for Automotive Applications
• UMC’s Value-added Design Services
• Summary
3
UMC © 2014
UMC PDK Supporting Platform
4
PDK
Process
Technology
Information
Netlisting Info &
Views
Pcells / Routing /
Connectivity /
Symbolic VIAs
Verification /
Parasitic
Extraction Rules
Cell View &
Symbols
Inside UMC
FDK Package (Foundry Design Kit)
Through MyUMC
Website Support
Schematic
Entry Tool
Virtuoso
Schematic Editor
/ Composer
ADS /
Laker ADP
Simulation
Tool
HSPICE
Spectre ADS
Layout
Editor
Virtuoso Layout
Editor Laker
Verification
Tool
DRC : Calibre
LVS : Calibre
RCX : QRC/
StarRC/XRC
ICV / PVS
UMC © 2014
UMC Supports Mainstream Digital Flow
• Support implementation guideline for advanced node on
55nm/40nm/28HLP/28HPC
5
UMC © 2014
6
Customer projects use UMC 28HLP technology plug-in
Technology
Scripts
Global
Scripts
Node
Configuration
Script Layers
Technology
Plug-ins
Flow Feature Status
RTL2PNR flow Completed
StarRC extraction Completed
ATPG Completed
STA - AOCVM Completed
ICV Standalone Completed
ICV in-design flow Completed
Redundant VIA
insertion
Completed
No-default rule for
CTS
Completed
In design Prime Rail Completed
DOMA cell insertion Completed
Metal Fill (ICV BEOL) Completed
ICV FEOL & DOMA Completed
Well TAP insertion Completed
Synthesis
& DFT
Design
Planning
PNR
Optimization
Chip
Finishing
Process node
configuration
Library QA
Optimized IP
design flows
UMC Support Synopsys Lynx Design Flow
6
Timing
Formal
Power
MV
Test
6
UMC © 2014
UMC DFM Solution
• Collaborate with leading EDA partners
• Shorten design cycles and iteration time
7
UMC © 2014
eNVM Interface IPs
Analog IPs
POP
Special I/O
Memory
Compilers
Standard
Cells
GP I/O
UMC’s Broad IP Ecosystem Partnership
8
Free Foundry Program - SC / MC / GPIO
We Support Flexible Business Models
Customization IPs - IP Partner Support
I/O • eSilicon
• Faraday
• Krivi
• UMC
Analog IPs • Cadence
• Synopsys
• TCI
Fundamental IPs • ARM
• Dolphin
• Faraday
• Synopsys
• UMC
eNVM • Cypress • eMemory • ISSI • Kilopass • Sidense • SST • Synopsys • UMC • YMC
Interface IP
• Cadence
• Synopsys
• Faraday
• Phisontech
UMC © 2014
Serves Broad Applications (Mobile, DTV, STB, Storage ...)
28/40nm Comprehensive IP Portfolio
Fundamental IP
(ARM/Synopsys/Faraday) - SC/IO (1.8_OD 3.3V)
- Memory Compiler
- POP/HPC
- eFuse/OTP
Analog IP
- ADC
- DAC
- PLL
- LDO
Interface IP
- USB 2.0/3.0
- PCIe 3
- DDR 4/3 Multi-PHY
- HDMI 1.4/2.0 Tx/Rx
- MIPI DPHY / MPHY
- HSIC
9
UMC © 2014
Outline
• UMC Design Enablement
- Overview on UMC’s Offering
- Solution for IoT Application
- Solution for Automotive Applications
• UMC’s Value-added Design Services
• Summary
10
UMC © 2014
IoT – the Next Wave of Opportunities
11
Question : What should be ready for seizing IoT opportunities?
• Smartphone leads post PC era growth
• IoT applications will drive the next wave
IoT
2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018
Nu
mb
ers
of D
evic
es In
Use
(in
mill
ion
)
0
2,000
4,000
6,000
8,000
10,000
12,000
14,000
16,000
18,000
20,000
Source: BI Intelligence, Gartner, IDC, UMC
Feature Phone: (-21%)
PC: (-8%)
LCD TV: (-5%)
Smartphone: 13%
YoY Growth Rate in 2015
Tablet: 9%
IoT
Tablets
Smartphones
PC (Desktop & Notebook)
UMC © 2014
Analysis for IoT Device
• Characteristic • Diversified
• Lightweight
• Power > Cost > Performance
• Capability • Data collection
• Security protection
• Execution
• Function • Sensing
• Connectivity
• Embedded Processor
Performance
Fu
ncti
on
12
UMC © 2014
• Very low active power
• Ultra low standby power
• Reduced processing time
• Very fast wake-up time
• Autonomous peripheral operation
• Refined power granularity
• Low energy sensor
• Multiple supply voltage
• Multiple Vth
• Power shut-down mode
• Low power IP
• Low power RTOS
Low Power Throughout All Design Stages
Arc
hite
ctu
re
Des
ign
Im
ple
me
nta
tion
P
roc
es
s
Te
ch
no
log
y
13
UMC © 2014
Foundry Differentiations
14
uLP Process - Low Vcc, Device Leakage
Tech. Fusion – eNVM, RF, HV, CIS, MEMS
Ultra Low Power IP – eFlash, Memory, SC, Analog, BLE
etc.
Easy-To-Test Methodology – eFlash, etc.
UMC © 2014
UMC IoT Technology Platform - Ultra Low Power Logic/MM/RF + eNVM Technology
40nm uLP SONOS/ESF3
55nm uLP SONOS/ESF3
110nm AE (Al) In House nFlash
12”
8”
28nm uLPP
180nm LL In House nFlash
15
UMC © 2014
Ultra Low Power IoT Fusion Solution
• Low Vcc domain
(down to 0.81V)
• uHVT device
• uLP SRAM cell
uLP
+RFCMOS
Platform Low Power IP
• Standard cell lib.
• Memory Compiler
(Retention < 0.6V)
• Analog IP
• BLE 4.1
• Low Power
eFlash Macro
• Customized
macro design
16
UMC © 2014
IoT Technology 3Q14 4Q14 1Q15 2Q15 3Q15 4Q15 1Q16 2Q16 3Q16 4Q16
UMC Optimized uLP Solutions
55uLP
0.9V/2.5V
+ SONOS
+ SST
SONOS Macro
T/O
SONOS Qual.
SST Macro
T/O
SST Qual.
IoT Technology 3Q14 4Q14 1Q15 2Q15 3Q15 4Q15 1Q16 2Q16 3Q16 4Q16
40uLP
0.9V/2.5V
+ SONOS
+ SST
Si Report
SONOS Qual.
SONOS Macro
T/O
SST Macro
T/O
SST Qual.
FDK, SC, Complier
Ready
17
Analog IP Interface IP
Ready (Reuse
55LP IP)
FDK, SC, Compiler
Ready
uLP Version Ready
Analog IP Interface IP
Ready (Reuse
40LP IP)
uLP Version Ready
Si Report
UMC © 2014
uLP Version Analog IP Provide Optimized Power Consumption
55uLP Analog IP Portfolio
Existing 55LP Analog IP 55uLP Analog IP
HFRC OSC Vcc : 1.08 ~ 1.32V Iactive < 530uA
LDO Regulator Vcc : 2.0 ~ 3.6V Vout : 1.2V ± 3% Iq : 65uA
Bandgap Vcc : 1.08 ~ 1.32V Vout : 0.8V ± 3.75% Iq : 60uA
HFRC OSC Vcc : 0.8 ~ 1.32V Iactive : ~ 80% less
LDO Regulator Vcc : 1.0 ~ 3.6V Vout : 0.9V ± 3% Iq : ~ 90% less
Bandgap Vcc : 1.0 ~ 3.6V Vout : 0.615V ± 2% Iq : ~ 90% less
LF Crys. OSC Vcc : 0.8 ~ 3.6V Iactive < 0.8uA
SAR ADC Vcc : 0.8 ~ 1.3V Resolution : 12bit Iactive < 60uA
18
UMC © 2014
40/55nm eFlash Macro Preliminary Spec
19
Macro Spec ESF3 (SST) SONOS (Cypress)
Application IoT IoT
Operation temp. -40C~125C -40C~110C
Voltage (Vcc/Vcc1) 0.9~1.2V 0.9~1.2V
Standby Current < 10uA @ 25C < 10uA @ 25C
Read Current < 2.4mA / 40MHz ~ 2.4mA / 40MHz
Access Time < 25ns
(< 60ns @ 0.9V)
< 25ns
(< 60ns @ 0.9V)
Endurance 100K 100K
Data Retention , 85C 10yrs 10yrs
UMC © 2014
Outline
• UMC Design Enablement
- Overview on UMC’s Offering
- Solution for IoT Application
- Solution for Automotive Applications
• UMC’s Value-added Design Services
• Summary
20
UMC © 2014
Hybrid or Electrical
Vehicle
Infotainment
Advanced Driver
Assistance System
(ADAS)
Fuel Efficiency
18.2 19.6
21.2
23.8
27.3 27.5
29.6
31.6
33.8
36.3
0
5
10
15
20
25
30
35
40
2011 2012 2013 2014 2015 2016 2017 2018 2019 2020
Automotive IC Revenue ($B USD)
$19.6B
(2012)
$36.3B
(2020)
Application CAGR
Computing 4.2%
Consumer 2.6%
Communication 4.0%
Automotive Provides Strongest Growth
Question : What should be ready for seizing auto opportunities?
21
UMC © 2014
Biz Continuity Mgt
Porting Solution
AEC Q-100 Qual
Turnkey Service
Auto Service Pkg
Certification
Foundry Strengthened Ecosystem
Liability
Capacity
Productivity
Reliability
Quality
Tier one/two customer
requirements
Foundry solutions
Platform Solution
22
UMC © 2014
UMC 55nm eFlash Platform Milestone
23
1Q15 3Q15 1Q16 4Q14 2Q15 4Q15 2Q16 3Q16 4Q16 1Q17
Customized Macro (T/O to Char.)
Process Frozen
Generic Macro (T/O to W/O)
1st lot Qual.
1st Qual. Lot (T/O to W/O)
Generic Macro Reliability Assessment
Generic Macro Characterization
UMC eFlash
Vehicle (55nm)
(Ta: -40oC~125oC)
Fully Comply with AEC Q100 Automotive Grade-1
UMC © 2014
24
4Mb Gen. Macro Assessment Condition Results
DC/AC Characteristic FT : -45oC, 25oC, 125oC and 150oC 0fail /3ea
CP 2/3 (High Temp Test) 150oC (Compared with 125oC) 0fail /69ea
EDR+HTSL (HTDR)
150oC, 1000hr/2000hrs/3000hrs, post
10K pre-cycling at worst temp
(FT : -40C, 25oC and 125oC)
0fail /80ea
Endurance Cycling Cycling sector write/erase cycles
at worst temp ~ 200K 0fail /80ea
• Functionality
• Cell 150oC Program/Erase Operation Pass
• Macro 150oC Functionality Pass
• Reliability Assessment
• Cycling 200K Pass
• Data Retention (post 10K pre-cycling)
• 3000hrs Pass
- Base on Generic Version Macro
55nm eFlash Automotive Grade 1 Assessment
UMC © 2014
55nm eFlash IP Plan (Automotive Grade 1)
• All IPs support 150oC automotive grade 1 requirement
• Fundamental IPs are ready for customer design in
• Standard cells with 7/9/12 Track
• Memory compilers
• SP SRAM & 1PRF with periphery HVT or RVT/HVT options
• VIaROM with periphery RVT or HVT options
• DPSRAM & 2PRF with periphery RVT/HVT
• IO
• 1.2V / 2.5V with HVT or RVT option
• Support UD_1.8V / 2.5V / OD_3.3V
• Most frequent used interface IP, USB2.0_OTG, also ready for
design in
25
UMC © 2014
For High Speed and Automotive Grade 1 Application
55nm eFlash Macro Spec (Automotive Grade 1)
26
Macro Spec. ESF3 LP Ver.
Application Auto
Operation temp. -40C~150C
Standby Current < 1uA @ 25C
Read Current (total) < 40mA / 110MHz
Access Time 9ns
Endurance 10K
Data Retention , 85C 10yrs
UMC © 2014
UMC Design Service
28
Design Service Team
• Backend APR Service
• Netlist-in or RTL-in
• On-site or in-house
• High-speed CPU/GPU
Cores Hardening service
• Dedicated Design Consultant
for Seamless Design Flow
Integration
High-speed
CPU/GPU
Hardening
Backend
APR
Service
Dedicated
Consultant
& FAE
Quad-core CA9
UMC © 2014
Service in mind, United at heart
UDS – UnitedDS Semi. (Shangdong) Co., Ltd.
• UMC group company, established
in 2014, April at Jinan high-tech
development zone, Shandong
• Provide APR & DFT service as 1st
stage development
• Leverage UMC manufacturing
technology and design experts to
provide customer with complete
support
29
UMC © 2014
Track Record of Our APR Service Team
• Reliable APR Design Service Team • 10+ successful joint tape-out and mass production
projects during 2013 ~ 2014
• Applications include Set-top box, DTV, Web CAM, High-speed
CPU core(dual/quad-core CA7 & CA9), Touchpad….
• Extensive process node experience (28/40/55/110nm)
• 10+ 55/40/28nm projects ongoing for 1H’15
• More are under development
30
UMC © 2014
CPU Performance Optimization
• CPU Optimization Solution • ARM POP : 40LP, 28HLP, 28HPC(under planning)
• Synopsys HPC : 40LP, 28HLP
• Faraday UHS : 28HPC
• CPU Core Hardening • UMC can support design implementation &
optimization
• Successfully demonstrated world class ARM CA-7 and CA-9 performance
• Achieved 1.6GHz (CA-7 @ 28HLP TT) and 1.8GHz(CA-9 @ 28HLP TT) performance
• Under development: 1.7GHz CA-53 @ 28HPC TT
31
UMC © 2014
IP Implementation & Optimization
32
• DDR PHY
• Special skew requirement
• Sign-off methodology
• SSO, Signal integrity
• GPU & DSP
• Well developed methodology
• Provide most optimized PPA
UMC © 2014
APR Service Team Success Story
Smartphone Chip
• UMC 28HLP 1P7M
• Cell count: 9M
• SRAM: 1060
• Hierarchical design
• Power shut off (PSO)
• Multi-Supply-Voltage
• Clock gating
• DVFS
Highly Integrated SoC @ UMC 28nm HLP Process
33
UMC © 2014
UMC Complete Design Support Solution
• Production Proven Design Enablement Platform • Complete solution for FDK, Design Flow, and DFM support
• Complete IP portfolio and ecosystem collaboration enable your easier
adoption
• Application driven IoT & Automotive design solution
• Comprehensive uLP platform with ultra low power IPs and eNVM solution,
providing most competitive IoT solution
• 55nm eFlash for Automotive grade 1 application development on track, with
complete IP offering
• Value Added Design Service • APR service through UMC in-house & Design Service Partners
• eFlash macro customization through UMC experienced engineering support
• Skilled engineers with advanced node success experiences for performance
optimization
35