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Unit 3 MMC

Mr. Asim Sayed

GHRCEM

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Protected-Mode Operation

The architecture of the Pentium's protectedmode is significantly different from that of realmode.

In real mode, addresses are generated by shifting16-bit segment registers to the left and adding a16-bit offset to create a 20bit physical address.

Segment registers are now called segmentselectors, and point to a structure called asegment descriptor.

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The segment descriptor contains addressing and

control information which is used to control how

a 32-bit linear address is generated.

These addresses may then be further translated

by a paging mechanism before emerging as aphysical address.

The number of additional registers are available inprotected mode.

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The five control registers -

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The Debug Registers-

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CRO contains many important control and status bits. Theirfunctions are as follows:

PG: Paging. Enables paging when set

CD: Cache Disable. Disables cache writes when set.

NW: Not Write through. Disables cache write throughoperations when set

AM: Alignment Mask. Allows alignment checking when set.

WP: Write Protect. Enforces supervisor-level write protection

when set. NE: Numeric Error. Allows floating-point errors to be reported

when set.

ET: Extension Type. Reserved.

TS: Task Switch. Set when a task switch occurs.

EM: Emulation. Indicates the presence of a coprocessor. Shouldbe zero on the

Pentium, which has an internal FPU.

MP: Monitor Coprocessor. Must be set to run 80286 and 80386programs on the Pentium.

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CR2 contains the 32-bit linear address that generated the mostrecent page fault.

CR3 contains the base address of the current Page Directory,which is used to support

paging.

CR4 has 6 bits whose operation is as follows:

VME: Virtual-8086 Mode Extensions. When set, enablesemulation of a virtual

interrupt flag. PVI: Protected Mode Vtrtual Interrupts. When set, allows a

virtual interrupt ftag to be

maintained in protected mode.

TSD: Time Stamp Disable. Used to make the RDTSC instructionprivileged.

DE: Debugging Extensions. Enables UO breakpoints when set.

PSE: Allows 4MB pages when set.

MCE: Enables the machine check exception

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Privileged instructions that operate on these new registerssuch as GDTR (global descriptor table register), LDTR (localdescriptor table register), IDTR (interrupt descriptor tableregister), and TR (task register).

ARPL

CLTS

CPUID

LAR

LGDT

LIDT

LLDTAdjust requested privilege level

Clear task switched flag

CPU identification Load access rights

Load global descriptor table register

Load interrupt descriptor table register

Load local descriptor table register

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Segmentation

Segmented memory is utilized by protected mode to

allow tasks to have their own separate memory spaces.

which are protected from access by other tasks.

Selectors

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Segment selectors contain a 13-bit index field that

is used to select one of 8,192 segment descriptors

that reside either in the global descriptor table(GDT) or the local descriptor table (LDT).

There is only one GDT in protected mode.Protected-mode tasks, however may each have

their own LDT.

The 11 bit in the segment selector picks the

appropriate descriptor table during translation.

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The GDT is located in memory through use of the

GDTR.

The GDTR is initialized with the LGDT (load global

descriptor table register) instruction.

LGDT loads 6 bytes of data from a source memory

operand into the GDTR.

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