UNIT-6 Memory Mgt.

8/12/2019 UNIT-6 Memory Mgt.

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Memory Organization

We designed computers, with memory subsystem comprised solely of ROM and RAM

This is fine for simple computers that perform specific tasks, such as controlling a microwave oven

or comple! computers, a memory subsystem consisting only of such physical memory would be

relatively slow and somewhat limited

"omputer designers utili#e several methods to design a memory system hierarchy that maximizes

overall system performance at an acceptable cost

One important component of memory hierarchy is cache memory$ This is high speed memory that

reduces the amount of time the "%& needs in order to access data

Another component of memory hierarchy is virtual memory, which expands the amount of memory

the CPU can access while minimizing cost

6.1 Hierarchical Memory Systems:

A computer system usually is not constructed using a single type of memory

'everal types are used

They comprise the hierarchical memory system of the computer


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The most well known element of the memory subsystem is the physical memory, which is constructed

using dynamic random access memory ()RAM* chips

As processor speeds increase, physical memory becomes a bottleneck in system performance

A computer system with only physical memory would spend most of its time waiting for data

This is the motivation behind using cache memory

"ache memory is constructed using 'RAM chips

"ache memory sits between "%& and main memory

A cache controller copies data from physical memory to cache memory before or when the "%& needs

it

"ache memory itself can be arranged hierarchically, usually with two levels

+$ + cache

-$ - cache

The goal of cache memory is to minimi#e the processor.s memory access time at a reasonable cost

/n addition to the cache levels, each level may contain - separate caches

0 )ata cache

0 /nstruction cache

(Motivation: to improve performance, especially in pipelined systems)

%rinciple behind 1arvard architecture

On the otherhand of the hierarchy is virtual memory


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"onsider a processor that supplies 2-3bit address

6.2 Cache Memory !ssociative Memory

!ssociative Memory:

"ache memory can be constructed using either 'RAM or associative memory, depending upon themapping scheme used

Associative memory is also called as Content Addressable Memory

Most of the types of memory are accessed by specifying the address (including 'RAM*

Associative memory is accessed differently

A memory unit accessed by content is called anAssociative Memoryor Content Addressable Memory Thismemory is accessed simultaneously and in parallel on the basis of contentrather than address

An associative memory is more expensive than random access memory, because each cell must have

storage capability as well as logic circuits for matching its content with e!ternal argument

or this reason, associative memories are used where the search time is very short and critical

Associative memory consists of set of words "alid #it

4ach word, in addition to data bits, contains additional bit 3 valid bit (labeled 5*

/t indicates whether the data is valid or not$ This is important in determining data matches $at

re%ister


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To read a value from associative memory, the "%& must specify the data value to be matched

This value is called argument or data$

Mas& 'e%ister

Mask register is used to in connection with checking portion of data bits

4ach bit that is to be checked is set to +

The other bits are set to 6

Mach 'e%ister

Match register contains one bit for each location in the associative memory$

/f a location generates a match, its bit in the match register is set to +, otherwise it is set to 6

Once match occurs, circuitry within associative memory would copy this data to its output register

/f more than one match occurs, the data can be read out se7uentially

ritin% data to associative memory

/s straight forward

The "%& supplies data to data register and asserts write signal

The associative memory checks for a location whose valid bit is 6$ /f it finds, it stores the data in that

location and sets the valid bit to +

/f no such location is found, it clears a location in order to store data$$


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Match o%ic:

Associative memory checks each location in parallel

Match occurs if

(+* for every bit position that has a value of + in the mask register, the location.s bits are same as data

register

(-* the location.s valid bit is set to +

"onsider +8!9 associative memory whose content is given below$ What data should be stored in data

and mask registers to select the last location:

Cache memory Mappin% *echni+ues:


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'eplacin% data in the cache:

)irect mapping offers the easiest solution to the replacement problem$

The associative cache allows any location in the physical memory to be mapped to any location i

cache$ Three typical replacement strategies are

0 /O

0 R&

0 Random

The set3associative cache also needs replacement strategy$ (igure ;$;*


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Cache performance

"ache hits and cache misses

1it ratio

Average memory access time

Where Tc< cache access time, Tp


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Basic Idea:The basic idea of virtual memory is to create an illusion of memory that is a

large as a disk (in gigabytes) and as fast as memory (in nanoseconds).

Most advanced CPUs can address more memory locations than physically exist in

their computers. For examle! a comuter "hose CPU issues #$%bit addresses ca

directly access &' of memory! much more than most comuters have.

Terminology

Physical address:n address in main memory is calledphysical address* the set osuch addresses is called memory space

Virt!al"Logical address : logical address is the address generated by CPU (or) an

address used by a rogrammer * the set of such addresses is called address space

Address s#ace o$ a Process:% +et of addresses available for a Process

Virt!al Memory: There are t"o rimary methods for imlementing virtual memory,

Paging

%egmentation

VIRTUAL MEMORY & PA'I('

-n Paging! the entire range of logical addresses (the addresses that can be outut by the

CPU)! is divided into contiguous blocks called! Pages.

ach age is the same si/e! and each logical address resides exactly in one age.

Physical memory is divided into nonoverlaing $rames.

The si/e of each frame is thesame as the si/e of one age.

Consider 0elatively +imle CPU!

"hich has a logical address sace

"ith 1&2 locations. -n this

system! there is 312 of hysical

memory and the age si/e is &2.

The memory is sho"n in the

4gure given belo",

)ig: One #ossi*le memory con+g!ration $or th

Relati,ely %im#le -PU

Pagingmoves ages from the disk to frames of the hysical memory so data can be

accessed by the rocessor.

ny age can occuy any frame.


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This leads to several issues that must be resolved by a aging system,

5hen should a age be moved into

hysical memory6 (7emand Paging)

8o" does the CPU 4nd data in hysical

memory! esecially if its logical address

is not the same as its hysical address6

(ddress translation done by MMU)

5hat haens "hen all the frames have

ages and the CPU needs to access data from a age )ig: MMU

con+g!ration .ithin the memory hierarchy not currentl

stored in hysical memory6 (0elacement lgorithms)

ll of these issues are handled by the memory management unit (MMU) as sho"n above.

The logical address is outut from the CPU to the MMU.

The MMU converts this address to a hysical address! "hich it sulies to the cache an

hysical memory. -f the data is not located in hysical memory! it generates a Page )a!lt/ and moves tha

age from the s"a disk to a frame (removing another age if necessary).

Throughout this rocess! the CPU has no information as to the actual hysical location i

is accessing.

The MMU uses a Page Ta*leto kee track of "hich ages are in "hich frames.

Consider a Page Table for the 0elatively +imle CPU described earlier! "ith 312 of hysica

memory and &2 age si/e. The Page Table has 31 entries (locations)! one entry for eac

age in the logical address sace. ach location contains )rame n!m*er! Valid *it(als

called Presence *it)! -o!ntand 0irty *it.o )rame n!m*er: indicates in "hich frame (in main memory) the age from virtua

memory is loadedo Valid *it:indicates "hether the virtual memory age is available in main memoryo -o!nt 1 0irty *its:are used in connection "ith age relacement. 7irty bit (als

called Modi$y *it) is needed to indicate if the age has been altered since it "a

last loaded into main memory. -f no change has been made! the age does no

have to be "ritten to the disk "hen it needs to be s"aed out

The MMU uses the age table to calculate the re9uired hysical addresses. To do so! th

MMU treats the logical address as t"o arts,

Logical address: 2Page (!m*er/ O3set4


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)ig:Address Translation in Paging Mechanism )ig:

Address Translation E5am#le

This maing rocess "orks "hen the age resides in hysical memory. ut "ha

haens "hen the age is not currently located in hysical memory6

Page )a!lt: 5hen the re9uired age is not currently located in hysical memory! ag

fault (interrut) is generated * the MMU causes the age to be coied from the disk to

frame in hysical memory. 5hile bringing re9uired age from disk to memory! if there are

unused frames! the re9uired age is coied there. :ther"ise! the MMU "ill us

0elacement lgorithm.

0emand Paging:The rocess of bringing re9uired age from disk to main memory a

and when it is required(on demand) is called demand aging. The ractice of deman

aging is used by virtually all MMUs.

Im#ortant Points:

67 %!##ort (eeded $or Virt!al Memory:o 8ard"are must suort aging and segmentation

o :erating system must be able to manage the movement of ages and;o

segments bet"een secondary memory and main memory

87 Each #rocess has its o.n #age ta*le

Translation Loo9aside B!3er:

-n Paging! each virtual memory reference can cause t"o hysical memory accesses, :ne to fetch the age table :ne to fetch the data

To overcome this roblem a high%seed cache is set u for age table entries. This i

called Translation Loo9aside B!3er TLB;7 T


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VIRTUAL MEMORY:: %E'ME(TATIO(

+egmentation is another method of allocating memory. -n +egmentation! the program is divided

into segments segment is a logical unit such as,

subroutine! or data structure Unlike ages! segments can vary in size

The MMU uses %egment Ta*le to kee track

of the segments resident in

memory. +ince a segment can start at one of many

addresses and can be of any si/e! each

segment table entry must include the start

address and segment size

%egmentation Architect!re


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The logical address is artitioned into a segment number and o>set

The segment number is inut to the

segment table,

-f the segment is located in

memory! oututs the starting

address of the segment and the

segment si/e

-f the segment is not in hysical

memory! it generates %egment

)a!lt! "hich causes the MMU to

load the segment into memory

The o>set is comared to the segment

si/e.

)ig: Addres

Translation in %egmentation

-f the o>set is greater than or e9ual to the segment si/e! it indicates that the location i

not art of the segment! an error is generated

-f the o>set is valid! then it is added to the start of the segment address to generate the

correct hysical address

s "ith aging! a +egmented MMU can also have a Ters from E=TER(AL )RA'ME(TATIO((unused sace bet"een block

in memory is called external fragmentation)

Paged %egmentation Paging > %egmentation;

-t is ossible to combine segmentation and aging by constructing a segment $rom

#ages! rather than as one contiguous block of memory


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-n this scenario! a logical address is broken into # arts )ig: Addres

translation in Paged %egmentation

2%egment n!m*er/ Page n!m*er/

and O3set4

The +egment number is inut to the

%egment Ta*le

8o"ever! instead of oututting a start

address! the segment table oututs a

#ointer to one o$ se,eral #age ta*les

(one for each segment)

The age table then oututs the

corresonding frame number in main

memory! or issues a Page )a!lt if the

age is not resident in memory

The frame number is concatenated"ith

o>set to roduce the hysical address

Ad,antages

The allocation of segments to physical memory is simpler since it is no longe

necessary to 4nd one contiguous block large enough to hold entire segment. The age

that comrise the segment can be located any"here in main memory

Tradeo3 :: lthough external fragmentation is eliminated! internal fragmentation i

introduced

?o longer necessary to add o>set! quicker concatenation can be used to the framenumber

0isad,antages

T"o levels of table look us

Virt!al Memory :: Memory Protection

Multitasking :+ may have several di>erent rograms (or arts of rograms ) resident i

memory simultaneously

These rogram comonents may belong to one user or to di>erent users

The :+ may also have comonents resident in memory

+ome mechanism is needed to ensure that one comonent does not over"rite another

and that no comonent can read data from another comonent

-n addition! a comonent can be rotected from its o"ner by restricting its mode o

access

ll of these fall under memory rotection


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referable otion to rotect memory is to #rotect the segment or #age! rather tha

individual location

To accomlish this! rotection bits are added to

each entry in the segment or age table

These bits might signify that a segment or

age is read only! read;"rite! or execute! and

that it is a user segment or age or is o"ned bythe :+. This is referred to as %!#er,isor or

?ernal mode

lso it is necessary to kee track of "hich

segments or ages are associated "ith "hich

users

A multi tasking OS may allow more than

one user or process to access a segment

%haring o$ segments

+hared resources! such as the dynamic link libraries (7erent ages or segments

This simli4es the assignment of values to caches


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Moti,ation,, behind dividing the cache into instruction and data caches is imrovin

erformance! esecially in Pielined +ystems

Beyond the *asics o$ Virt!al Memory

For smaller comuter systems! the

aging and segmentation schemes for

managing @irtual Memory "ork "ell

8o"ever! their si/es becomerohibitively large as the si/e of the

virtual memory address sace increases

xamle, CPU "ith #$%bit address si/e!

is caable of accessing & ' of memory

Page si/e = 312

Page Table contains $A12 (i.e.

$3B$1$!3&&) entries in its age table

:ne "ay to resolve this roblem is to

imlement the age table as a

multilevel hierarchy

Primary Table contains ointers to

secondary tables

The rimary table can be stored in

memory * secondary tables could be

moved in and out of hysical memory

as needed

The Al#ha micro#rocessor suorts

u to & levels of age tables

)ig: M!ltile,e

Page Ta*le @ierarchy

Real orld E5am#le: : Memory Management in a Penti!m"indo.s Persona

-om#!ter

Consider a Personal Comuter that has an -ntel Pentium Microrocessor and run

Microsoft 5indo" ?T.

First "e look at the +ystemDs

Cache Memory! and then "e

examine its @irtual Memory

Memory hierarchy is sho"n in

the Figure.

The system has 312 of


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ach line has $E%bit tag

The entries in this cache are "rite%rotected

The code cache also has its o"n #$%entry translation lookaside bu>er

The T

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UNIT-6 Memory Mgt.

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