Unit 6 - Storage and Bus

7/29/2019 Unit 6 - Storage and Bus

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Storage and Other I/OTopics

Lecture 01 Storage


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Chapter 6 Storage and Other I/O Topics 2

Introduction

I/O devices can be characterized by Behavior: input, output, storage, network

Partner: human or machine

Data rate: bytes/sec, transfers/sec

Storage I/O bus connections

I/O Management

6.1Introduction


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Outline

Storage Disk

Flash Interconnecting Components

and I/O bus

File System & Web Benchmarks I/O System Design


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I/O System Characteristics

Dependability is important Particularly for storage devices

Performance measures Latency (response time)

Throughput (bandwidth)

Desktops & embedded systems Mainly interested in response time & diversity of

devices

Servers Mainly interested in throughput & expandability of

devices


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Dependability

Fault: failure of acomponent

May or may not leadto system failure

Fault-tolerant system

Service accomplishmentService delivered

as specified

Service interruptionDeviation from

specified service

FailureRestorationrepair working

failed

Failure rate lRepair rate m

Finite State Machine


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Dependability Measures

Reliability R(t): Probability to the first failure in agiven time period

MTTF: Mean Time To Failure = R(t)dt

Service interruption: mean time to repair (MTTR) Mean time between failures

MTBF = MTTF + MTTR

Availability = MTTF / (MTTF + MTTR)

Improving Availability

Increase MTTF: fault avoidance, tolerance, forecasting

Reduce MTTR: improved tools and processes for

diagnosis and repair

0


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Disk Storage

Nonvolatile, rotating magnetic storage

6.3DiskStorage

Each sector records Sector ID

Data (512 bytes, 4096 bytes proposed)

Error correcting code (ECC) Used to hide defects and recording errors

Fault tolerance technique

Synchronization fields and gaps

Sector


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Disk Sectors and Access

Access time to a sector involves Queuing delay if other accesses are pending

Seek: move the heads to select tracks

Disk rotational latency to select sector

Data transfer time to read the sector

Controller overhead

Sectors

Platter Platters

Disk

Track

Reading arms

and heads

Tracks


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Disk Performance Example

Given 512B sector, 15,000rpm, 4ms average seek

time, 100MB/s transfer rate, 0.2ms controlleroverhead, idle disk (no waiting queue)

Average read time seek time = 4ms

avg rotational latency = / (15,000/60) = 2msdata transfer time 512 / 100MB/s = 0.005mscontroller delay = 0.2ms

Total = 6.2ms If actual average seek time, considering

locality, is 1ms Average read time = 3.2ms


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Disk Performance Issues

Manufacturers quote average seek time

Based on all possible seeks

Locality and OS scheduling lead to smaller actualaverage seek times: there are many patentedalgorithms of reducing seek time!

Disk controller hides specific details of physicalsectors on disk

Present logical (standard) sector interface to host

SCSI, ATA, SATA

Disk drives include caches

Pre-fetch sectors in anticipation of access

Avoid seek and rotational delay


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Flash Storage

Nonvolatile semiconductorstorage 100 1000 faster than disk

Smaller, lower power, more robust

But more $/GB (between disk and DRAM)

6.4Flash

Storage


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Flash Types (Solid State Drive)

NOR flash: bit cell like a NOR gate

Random read/write access

Used for instruction memory in embedded systems

NAND flash: bit cell like a NAND gate

Denser (bits/area), but block-at-a-time access Cheaper per GB

Used for USB keys, media storage,

Flash bits wears out after 1000s of accesses

Not suitable for direct RAM or disk replacement

Wear leveling: remap data to less used blocks


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NOR vs. NAND Flash

Source: Toshiba America


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Outline

Storage

Interconnecting Components

and I/O bus IO Management

File System & Web Benchmarks

I/O System Design


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Need interconnections between CPU, memory, I/O controllers, devices

Bus: shared communication channel Parallel set of wires for data, address, controls Wires are shared in different time slots One component can send at one time; All components will receive the data (broadcasting). If

the destination address is different, discard data. Collision will occur if two components send at the

same time; Then, resend. Coordination among control and data lines necessary Can become a bottleneck

Performance limited by physical factors Wire length, number of components connected


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Bus Types

Synchronous Buses: Short, high speed, clocked,taking an action in each clock

Processor-memory bus

Graphic bus

Asynchronous Buses: Longer, slower, andallowing multiple devices, usinghandshaking

I/O buses Backplane Bus connecting bridges to IO

Busses


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Bus Types and Organization

Processor-Memory Bus

I/OBus

. . . . . .

I/OBus

Backplane

BusCPU SRAM

DRAMGraphic

Card

High-speedbus bridge

Bus bridge

SynchronousBus

AsynchronousBus

Control linesData lines


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Bus Types andOrganizationExample L2

Cache

Process-MemoryBus

SynchronousBus

AsynchronousBus

Disk

CDKeyboard

Mouse

FSB


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Bus Slots

Connectingto Device


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Bus Signals and Synchronization

Data lines Carry address and data

Multiplexed (shared) or separate

Control lines Indicate data type, synchronize transactions

Synchronous Bus Protocol Uses a bus clock

Use for fast devices

Asynchronous Bus Protocol Uses request/acknowledge control lines for

handshaking

Use for slow speed devices


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SynchronousSeparate Address and Data Lines (Write)

Address

Data

Write

Clock


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SynchronousSeparate Address and Data Lines (Read)

Address

Data

Read

DataReady

Clock


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Synchronous Communication Protocol Analogy

Teaching a large class

Clock Instructor Students

week1 Prepare assignment

week2 Assignment 1 release Do assignment 1

week3 Prepare assignment Assignment 1 submission










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Asynchronous Communication Protocol Analogy

Individual Learning

Instructor Student

Week1 Prepare assignment 1

Assignment 1 release

Do assignment 1

I am nearly completed

week2 Prepare assignment 2 Assignment 1 submitted

Assignment 2 releaseDo assignment 2


week7 Prepare assignment 3 Assignment 2 submitted


Do assignment 3I am nearly completed

week 9 Prepare assignment 4 Assignment 3 submitted


Do assignment 4



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I/O Bus Examples

Firewire USB 2.0 PCI Express Serial ATA Serial

AttachedSCSI

Intended use External External Internal Internal External

Devices perchannel

63 127 1 1 4

Data width 4 2 2/lane 4 4Peakbandwidth

50MB/s or100MB/s

0.2MB/s,1.5MB/s, or60MB/s

250MB/s/lane1, 2, 4,8, 16, 32

300MB/s 300MB/s

Hotpluggable

Yes Yes Depends Yes Yes

Max length 4.5m 5m 0.5m 1m 8m

Standard IEEE 1394 USBImplementersForum

PCI-SIG SATA-IO INCITS TCT10


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Bus Arbitration

Multiple master devices are connected to a single bus,which can start to send a message at the same time.

Arbitration is needed to decide which device is going to

use the bus.

Bus arbitration schemes

A single master (processor): All devices send requests

to the processor, which decides which device will use

the bus

Daisy chain arbitration

Centralized parallel arbitration

Distributed arbitration by collision detection: Ethernet


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Daisy Chain Arbitration

Advantages:

simple to implement

high utilization of bus (no conflict overhead)

extendableDisadvantages:

unfairness: low priority devices may never get a chance

priority is position-related

unreliable (a broken device can block other devices)


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Centralized Parallel Arbitration

Advantages:

a broken device can not block other devices

can design flexible priorities

high utilization of bus (no conflict overhead)

disadvantages:

not easy to extend once the design is completed

vulnerable for single-point-of-failure (arbiter)


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Distributed Arbitration

Advantages:

less vulnerable for single-point-of-failure

fairness among the devices (contention protocols) extendable

disadvantages:

lower utilization of bus (conflict overhead)


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ALOHA broadcast protocol (Contention Protocol)

(1) A station transmits whenever it has data,

(2) Check whether the feedback = sent message?

(3) If not (collision), wait a random time, transmit again

Distributed Bus Arbitration/LAN Protocols


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IEEE 802.3 and Ethernet Protocol

1. listen to the channel, if the channel is free, then it transmits,

else wait until its free,2. earlier collision detection and abortion

3. by collision, wait a random time, goto (1)

1. by 1st collision, wait 0 or 1 slot (= 2t, the round-trip time);

2. by 2nd collision, wait 0, 1, 2, or 3 slots;

3. by 3rd collision, wait 0, 1, 2, 3, 4, 5, 6, or 7 slots;4. by 4th collision, wait 0 , 1, 2, 3, ..., or 15 slots;

5.

6. by nth collision, wait 0 , 1, 2, 3, ..., or 2n-1 slots;

The random time is defined by binary exponential backoff:


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IEEE 802.11 Wireless Ethernet Protocol

Can be configured into two modes

ad hoc mode

infrastructure mode

Different radios and bandwidths

802.11a:

radios transmit at 5 GHz and send data up to 54

Mbps, with distances of about 60 feet

802.11bradios transmit at 2.4 GHz and send data up to 11

Mbps, with distances of about 300 feet.

More: 802.11c, 802.11d, 802.11e, 802.11f, 802.11g ...


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IEEE 802.11 Ad Hoc Mode

Devices communicate with each other directly


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IEEE 802.11 Infrastructure Mode

wired network

station

station

Devices communicate with each other via base stations, similar to cellularphone networks


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Outline

Storage


and I/O bus I/O Management

I/O Performance

6


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I/O Management

I/O is mediated by the OS

Multiple programs share I/O resources

Need protection and scheduling

I/O causes asynchronous interrupts

Same mechanism as exceptions

I/O programming is fiddly (small, but awkward)

OS provides abstractions to programs

Using library functions to access I/O, e.g., system calls, which are OS functions, in

MARS simulator

6.6Interfacin

gI/ODevices


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I/O Registers and Commands

I/O devices are managed by I/O

controller hardware Transfers data to/from device

Synchronizes operations with software

Command registers Cause device to do something

Status registers Indicate what the device is

doing and occurrence of errors

Data registers Write: transfer data to a device

Read: transfer data from a device

busyreadyerror

data

Device

Data register

Command reg

Status register

I/O controller

CPU


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I/O Register Mapping

Memory mapped I/O (MIPS)

I/O registers are addressed in same space as memory(considered as memory locations)

Address decoder distinguishes between them

OS uses address translation mechanism to makethem only accessible in kernel mode, not available inthe user mode. Drivers are running in kernel mode!

No additional I/O instructions are required

I/O instructions (Intel) Separate instructions to access I/O registers

Can only be executed in kernel mode

Example: x86


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Typical x86 PC I/O System

OtherI/ODevices


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Polling with loop-waiting: while (not busy) do send data

Pollingwith periodically checking the busy bit andpossible multitasking Interrupt-driven: More efficient if requests are not

frequent; less efficient if requests are frequent, I/O processor: delegating I/O from CPU

Interface Devices to CPU

Polling

Ready fornext data

Interrupt-driven

periodicallybusyreadyerror

data

Device

Data register

Command reg

Status register

I/O controller

CPU

busyready

error

data

Device

Data register

Command reg

Status register

I/O controller

CPU

Example: Polling


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CPU wants to transfer 1024 words to a device (e.g., printer)

Example: Polling

// CPU process

counter = 1024

L0 load the status register of the devicetest the busy bitif busy = true goto L0 // or call Sleep(500) in multitasking OSelse store a word into the data register of the device

set data-ready = truecounter = counter - 1if counter = 0 exitelse goto L0

// Device process

L1 set busy bit to falseL2 test data-ready bitif data-ready = false goto L2

set busy bit to trueprint the data byte0, byte1, byte2, byte3set data-ready = falsegoto L1

busy

readyerror

data

Printer

Data register

Command reg

Status register

I/O controllerCPU

D i C l E l


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Device Control Example

Which device should we use polling?

Which device should we use interrupts?

What about a computer science doctors office

hours and a medical doctors office hours?

42

Sonarrangesensor

Touchsensor

I/O D T f i h DMA


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I/O Data Transfer with DMA

Polling and interrupt-driven I/O

CPU transfers data between memory and I/Odata registers

Time consuming for high-speed devices

Direct Memory Access (DMA)

OS provides starting address in memory andpackage size

I/O controller transfers to/from memoryautonomously

Controller interrupts on completion or error


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DMA: Direct Memory Access, a specialized processor

that transfers data between memory & device, e.g.,

printer or disk. CPU sends DMA address and # of

bytes. After completion, DMA sends done.

I/O processor(I/O controller or channel controller): is

more intelligent than DMA. It handles multiple inputs in

a queue and multiple outputs to a number of devices.An I/O processor normally doesnt convert data, only

transfer.

DMA and I/O Processor

DMA d I/O P


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DMA and I/O Processor

CPU Mem

Device

address size

data

CPU Mem

Device

address dst/src

data

sizeaddress dst/src sizeaddress dst/src sizeaddress dst/src sizeaddress dst/src size

Device. . .

DMA I/OProcessor

DMA

Device

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Unit 6 - Storage and Bus

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