Department of Electronics and Communication Engineering, VBITDepartment of Electronics and Communication Engineering, VBIT
P.VIDYA SAGAR ( ASSOCIATE PROFESSOR)
https://potharajuvidyasagar.wordpress.com
Subject Code : EC702PC
Subject Name : VLSI DESIGN
UNIT - I
INTRODUCTION
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Course Outcomes (with reference to syllabus and taxonomy levels)
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Taxanomy Course Outcome
CO 1 L2-UnderstandingAt the end of the course Students are able to acquire qualitative knowledge about the MOS transistors fabrication
CO 2 L3-ApplyingAt the end of the course Students are able to develop the layout of any logic circuit which helps to understand and estimate parasitical effects.
CO 3 L3-ApplyingAt the end of the course Students are able to develop Structures of logical gates using CMOS inverter and analyze their transfer characteristics.
CO 4 L3-ApplyingAt the end of the course Students are able to understand the concepts required to design building blocks of data path using gates and design simple memories using MOS transistors
CO 5 L2-UnderstandingAt the end of the course Students are able to design simple logic circuit using Array memories and to acquire Knowledge on testing and testability of a system.
Department of Electronics and Communication Engineering, VBITDepartment of Electronics and Communication Engineering, VBIT
Contents
UNIT I
INTRODUCTION: Introduction to IC Technology – MOS, PMOS, NMOS, CMOS & BiCMOS
technologies.
BASIC ELECTRICAL PROPERTIES : Basic Electrical Properties of MOS and BiCMOS Circuits:
Ids-Vds relationships, MOS transistor threshold Voltage, gm, gds, figure of merit ωo ; Pass transistor,
NMOS Inverter, Various pull ups, CMOS Inverter analysis and design, Bi-CMOS Inverters.
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The First Computer
The BabbageDifference Engine(1832)
25,000 parts
cost: £17,470
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ENIAC - The first electronic computer (1946)
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A Brief History Invention of the Transistor
❖ Vacuum tubes ruled in first half of 20th century Large, expensive,power-hungry, unreliable
❖ 1947: first point contact transistor (3 terminal devices)
❖ Shockley, Bardeen and Brattain at Bell Labs
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A Brief History, contd..
❖ 1958: First integrated circuit❖ Flip-flop using two transistors
❖ Built by Jack Kilby (Nobel Laureate) at Texas Instruments
❖ Robert Noyce (Fairchild) is also considered as a co-inventor
smithsonianchips.si.edu/ augarten/
Kilby’s IC
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❖ 1970’s processes usually had only nMOS transistors❖ Inexpensive, but consume power while idle
❖ 1980s-present: CMOS processes for low idle power
❖
MOS Integrated Circuits
Intel 1101 256-bit SRAM Intel 4004 4-bit Proc
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WHY VLSI?
Integration Improves the Design
• Lower parasitic, higher clocking speed
• Lower power
• Physically small
Integration Reduces Manufacturing Costs
• (almost) no manual assembly
• About $1-5billion/fab
• Typical Fab 1 city block, a few hundred people
• Packaging is largest cost
• Testing is second largest cost
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n+n+S
GD
+
DEVICE
CIRCUIT
GATE
MODULE
SYSTEM
Design Levels
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Moore’s Law
❖ 1965: Gordon Moore plotted transistor on each chip
❖ Fit straight line on semilog scale
❖ Transistor counts have doubled every 26 months
❖ He predicted that the number of transistors on a chip would double
about every 18 months
Year
Tra
nsisto
rs
40048008
8080
8086
80286Intel386
Intel486Pentium
Pentium ProPentium II
Pentium III
Pentium 4
1,000
10,000
100,000
1,000,000
10,000,000
100,000,000
1,000,000,000
1970 1975 1980 1985 1990 1995 2000
http://www.intel.com/technology/silicon/mooreslaw/
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INTEGRADED CIRCUIT (IC):
Multi terminal electronic device in which discrete components like
transistors,resisters,capacitors are fabricated in a single
construction process.
Classification of ICs :
•Based on application -Analog , digital
•Based on complexity -SSI, MSI, LSI, VLSI
•Based on fabrication-Monolithic , hybrid
•Based on technology -RTL ,DTL, TTL, MOS.
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IC Evolution :
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Name Year Transistors number Logic gates number
small-scale integration (SSI) 1964 1 to 10 1 to 12
medium-scale integration (MSI) 1968 10 to 500 13 to 99
large-scale integration (LSI) 1971 500 to 20,000 100 to 9,999
very large scale integration (VLSI) 1980 20,000 to 1,000,000 10,000 to 99,999
Ultra large scale integration (ULSI) 1984 1,000,000 and more 100,000 and more
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Pentium 4 Processor
http://www.intel.com/intel/intelis/museum/online/hist_micro/hof/index.htm
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Ref: http://micro.magnet.fsu.edu/creatures/technical/sizematters.html
• Modern transistors are few microns wide and approximately 0.1 micron or less in length
• Human hair is 80-90 microns in diameter
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➢MOS (Metal-oxide-silicon)
➢ although invented before bipolar transistor, was initially difficult to manufacture
➢ nMOS (n-channel MOS) technology developed in 1970s required fewer masking steps,
was denser, and consumed less power than equivalent bipolar Ics.
➢CMOS (Complementary MOS): n-channel and p-channel MOS transistors =>
lower power consumption, simplified fabrication process
➢Bi-CMOS - hybrid Bipolar, CMOS (for high speed)
➢GaAs - Gallium Arsenide (for high speed)
➢Si-Ge - Silicon Germanium (for RF)
Metal-oxide-semiconductor (MOS) and related VLSI technology
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Mos transistors
➢ Basic MOS transistors with the doping concentration of transistor two types of MOS transistors
are available as NMOS transistor and PMOS transistor. With their mode of operation further
they are classified as depletion mode transistor and enhancement mode transistor.
nMOS enhancement mode transistor
➢ nMOS devices are formed in a p-type substrate of moderate doping level. The source and drain
regions are formed by diffusing n-type impurities through suitable masks into these areas.
Thus source and drain are isolated from one another by two diodes and their Connections are
made by a deposited metal layer. The basic block diagrams of nMOS enhancement mode
transistor is shown in figure.
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nMOS depletion mode
transistor
nMOS enhancement mode
transistor
– The basic block diagram of nMOS depletion mode transistor is shown in figure. In depletion mode
transistor the channel is established even the voltage Vgs = 0 by implanting suitable impurities in
the region between source and drain during manufacture and prior to depositing the insulation
and the gate.
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1.What is Ids in Linear Region
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MOS Transistors
➢ Four terminal device: gate, source,
drain, body
➢ Gate – oxide – body stack looks like a
capacitor
➢ Gate and body are conductors (body
is also called the substrate)
➢ SiO2 (oxide) is a “good” insulator
(separates the gate from the body
➢ Called metal–oxide–semiconductor
(MOS) capacitor, even though gate is
mostly made of poly-crystalline
silicon (polysilicon)
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
NMOS
PMOS
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MOS Capacitor
❖ Gate and body form MOS capacitor
❖ Operating modes
❖ Accumulation
❖ Depletion
❖ Inversion
polysilicon gate
(a)
silicon dioxide insulator
p-type body+-
Vg < 0
(b)
+-
0 < Vg < V
t
depletion region
(c)
+-
Vg > V
t
depletion region
inversion region
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Terminal Voltages
➢ Mode of operation depends on Vg, Vd, Vs
➢ Vgs = Vg – Vs
➢ Vgd = Vg – Vd
➢ Vds = Vd – Vs = Vgs - Vgd
➢ Source and drain are symmetric diffusion terminals
➢ By convention, source is terminal at lower voltage
➢ Hence Vds 0
➢ nMOS body is grounded. First assume source is 0 too.
➢ Three regions of operation
➢ Cutoff
➢ Linear
➢ Saturation
Vg
Vs
Vd
Vgd
Vgs
Vds
+-
+
-
+
-
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nMOS Cutoff
➢ Assume n-channel MOSFET and VSB=0
➢ No channel
➢ Ids = 0
➢ Cutoff Mode: 0≤VGS<VT0
➢ The channel region is depleted and no current can flow
+-
Vgs
= 0
n+ n+
+-
Vgd
p-type body
b
g
s d
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VGS < VT0
gate
drainsource
IDS=0
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nMOS Linear➢ Linear (Active, Triode) Mode: VGS≥VT0, 0≤VDS≤VD(SAT)
➢ Inversion has occurred; a channel has formed
➢ For VDS>0, a current proportional to VDS flows from source to drain.
➢ Current flows from d to s , e- from s to d
➢ Behaves like a voltage-controlled resistance
(Similar to linear resistor)
➢ Ids increases with Vds
+-
Vgs
> Vt
n+ n+
+-
Vgd
= Vgs
+-
Vgs
> Vt
n+ n+
+-
Vgs
> Vgd
> Vt
Vds
= 0
0 < Vds
< Vgs
-Vt
p-type body
p-type body
b
g
s d
b
g
s dIds
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VDS < VGS – VT0
VDS < VGS – VT0
gate
drainsourcecurrent
IDS
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nMOS Saturation➢ Pinch-Off Point (Edge of Saturation) : VGS≥VT0, VDS=VD(SAT)
➢ Channel just reaches the drain
➢ Channel is reduced to zero inversion charge at the drain
➢ Drifting of electrons through the depletion region between the channel and drain has begun
➢ Channel pinches off
➢ Ids independent of Vds
➢ We say current saturates
➢ Similar to current source
+-
Vgs
> Vt
n+ n+
+-
Vgd
< Vt
Vds
> Vgs
-Vt
p-type body
b
g
s d Ids
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VDS = VGS – VT0
gate
drainsourcecurrent
IDS
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MOSFET I-V Characteristics
Summary of Analytical Equations
➢ The voltage directions and relationships for the three modes of pMOS are in contrast to those of
nMOS.
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G
S
B
D
VDS
VSBVGS
ID
G
D
B
S
VDSVSB
VGS ID
nMOS
Mode ID Voltage Range
Cut-off 0 VGS<VT
Linear (μnCox/2)(W/L)[2(VGS-VT)VDS-VDS2] VGSVT,VDS< VGS -VT
Saturation (μnCox/2)(W/L)(VGS-VT)2(1+λVDS) VGS VT,VDS VGS -VT
pMOS
Cut-off 0 VGS>VT
Linear (μnCox/2)(W/L)[2(VGS-VT)VDS-VDS2] VGS VT,VDS> VGS -VT
Saturation (μnCox/2)(W/L)(VGS-VT)2(1+λVDS) VGS VT,VDS VGS -VT
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I-V Characteristics
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NMOS:Vgs < Vt OFFVds < Vgs -Vt LINEARVds > Vgs – Vt SATURATION
PMOSVsg < |Vt| OFFVsd < Vsg – |Vt| LINEARVsd > Vsg – |Vt| SATURATION
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CMOS
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Structure: n-channel MOSFET(NMOS)
pn+n+
metal
LW
source
S
gate: metal or heavily doped poly-Si
Gdrain
D
body
B
oxide
IG=0
ID=ISIS
x
y
(bulk or
substrate)
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Channel Charge
➢ MOS structure looks like parallel plate capacitor while operating in inversion
➢ Gate – oxide – channel
➢ Qchannel =
n+ n+
p-type body
+
Vgd
gate
+ +
source
-
Vgs
-drain
Vds
channel-
Vg
Vs
Vd
Cg
n+ n+
p-type body
W
L
tox
SiO2 gate oxide
(good insulator, ox
= 3.9)
polysilicon
gate
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Channel Charge
➢ MOS structure looks like parallel plate capacitor while operating in inversion
➢ Gate – oxide – channel
➢ Qchannel = CV
➢ C =
n+ n+
p-type body
+
Vgd
gate
+ +
source
-
Vgs
-drain
Vds
channel-
Vg
Vs
Vd
Cg
n+ n+
p-type body
W
L
tox
SiO2 gate oxide
(good insulator, ox
= 3.9)
polysilicon
gate
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Channel Charge
➢ MOS structure looks like parallel plate capacitor while operating in inversion
➢ Gate – oxide – channel
➢ Qchannel = CV
➢ C = Cg = oxWL/tox = CoxWL
➢ V =
n+ n+
p-type body
+
Vgd
gate
+ +
source
-
Vgs
-drain
Vds
channel-
Vg
Vs
Vd
Cg
n+ n+
p-type body
W
L
tox
SiO2 gate oxide
(good insulator, ox
= 3.9)
polysilicon
gate
Cox = ox / tox
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Channel Charge
➢ MOS structure looks like parallel plate capacitor while operating in inversion
➢ Gate – oxide – channel
➢ Qchannel = CV
➢ C = Cg = oxWL/tox = CoxWL
➢ V = Vgc – Vt = (Vgs – Vds/2) – Vt
n+ n+
p-type body
+
Vgd
gate
+ +
source
-
Vgs
-drain
Vds
channel-
Vg
Vs
Vd
Cg
n+ n+
p-type body
W
L
tox
SiO2 gate oxide
(good insulator, ox
= 3.9)
polysilicon
gate
Cox = ox / tox
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Carrier velocity
– Charge is carried by e-
– Carrier velocity v proportional to lateral E-field between source and drain
– v =
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Carrier velocity
➢ Charge is carried by e-
➢ Carrier velocity v proportional to lateral E-field between source and drain
➢ v = E called mobility
➢ E =
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Carrier velocity
➢ Charge is carried by e-
➢ Carrier velocity v proportional to lateral E-field between source and drain
➢ v = E called mobility
➢ E = Vds/L
➢ Time for carrier to cross channel:
➢ t =
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Carrier velocity
➢ Charge is carried by e-
➢ Carrier velocity v proportional to lateral E-field between source and drain
➢ v = E called mobility
➢ E = Vds/L
➢ Time for carrier to cross channel:
➢ t = L / v
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nMOS Linear I-V
➢ Now we know
➢ How much charge Qchannel is in the channel
➢ How much time t each carrier takes to cross
dsI =
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nMOS Linear I-V
➢ Now we know
➢ How much charge Qchannel is in the channel
➢ How much time t each carrier takes to cross
channelds
QI
t=
=
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nMOS Linear I-V
➢ Now we know
➢ How much charge Qchannel is in the channel
➢ How much time t each carrier takes to cross
channel
ox 2
2
ds
dsgs t ds
dsgs t ds
QI
t
W VC V V V
L
VV V V
=
= − −
= − −
ox = W
CL
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nMOS Saturation I-V
➢ If Vgd < Vt, channel pinches off near drain
➢ When Vds > Vdsat = Vgs – Vt
➢ Now drain voltage no longer increases current
dsI =
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nMOS Saturation I-V
➢ If Vgd < Vt, channel pinches off near drain
➢ When Vds > Vdsat = Vgs – Vt
➢ Now drain voltage no longer increases current
2dsat
ds gs t dsat
VI V V V = − −
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nMOS Saturation I-V
➢ If Vgd < Vt, channel pinches off near drain
➢ When Vds > Vdsat = Vgs – Vt
➢ Now drain voltage no longer increases current
( )2
2
2
dsatds gs t dsat
gs t
VI V V V
V V
= − −
= −
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nMOS I-V Summary
( )2
cutoff
linear
saturatio
0
2
2n
gs t
dsds gs t ds ds dsat
gs t ds dsat
V V
VI V V V V V
V V V V
= − −
−
➢ Shockley 1st order transistor models
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Thank you………………