UNIT6

INPUT/OUTPUT AND INTERFACE E3165 / UNIT 6 / 1

General Objective:

To understand and solving mathematical problems in the input/output and interface.

Specific Objectives:

At the end of the unit you should be able to:

6.1 discuss the operation of Input/Output 6.2 explain and discuss the technics of transferring data from and to

computer system.6.3 discuss the PPI 8255A/ PIA68216.4 calculate and explain the Input/Output interfacing circuit.

UNIT 6

OBJECTIVE


6.0 INTRODUCTION

In most computer system, microprocessor must communicate (interfacing) with main memory (Ram and ROM) and I/O devices or peripheral devices ( keyboard, printer ect). In which the operation that took place is write and read from the MPU (main memory), write and read from peripheral devisees, Interrupt, Direct Memory Access and Handshaking.

To ensure the microprocessor can communicate with I/O devices, interfacing are needed. In this chapter we will learn the interfacing concept and certain IC that can be used as an interface between microprocessor and I/O devices.

6.1 The operation of Input/Output

6.1.1 Unconditional I/O Transfer – MPU Initiated

There are several different ways in which I/O transfers can be initiated and controlled. For example, the transfer of data between an MPU and I/O devices can be initiated either by the MPU or by the devices. Once I/O transfer has been initiated, it can be carried out under the control of the MPU or, in some cases, under the control of the I/O devices. The basic alternatives are presented in figure 6.1

Figure 6.1 Basic I/O transfer alternatives.

INPUT-6A

* Requires some exchanging of control device information between MPU device(handshaking)

MPU initiated Device initiated

Unconditional transfer

Conditional transfer

Interrupt transfer*

Direct (DMA) memory access


The unconditional data transfer is used only in situation where an output device is always ready to accept data from the MPU or an input device always has data ready for the MPU. In such cases, there is no need for any exchange of control signals between the MPU and the I/O device. The MPU simply executes instructions that causes it to write data in to the output device or to read data from the input device.

6.1.2 Interrupt System

Interupt is a signal that causes the microprocessor to end its normal execution to initiate interrupt operation.

There are hardware and software interrupt. Hardware interrupt occurs when microprocessor interrupt pin given truth logic. Example the MIC 68000 interrupt pin is RESET. Software interrupt in the other hand needs an instruction programming to be initiated.

How interrupt is initiated

1. When a microprocessor receive interrupt request signal, the process will proceed until it end cycle before entertain the interrupt signal.

2. The instruction of program counter (PC) and register will be stored in stack with LIFO ways. Now PC will remember the new address for interrupt sequence to enhance the microprocessor in initiated interrupt sequence.

3. After executing interrupt sequence, PC will again be filled by the data in PC and register that already been stored in stack before.

4. Microprocessor will now return to initiate its original program operations.

Interrupt request signal

Main Program

interrupt service routine

After completion of interrupt service routine, control return to original program


6.1.2.1 Types of interrupt

1. Maskable Interrupt- interrupt signals that can be received or not by

microprocessor, depends on priority.

2. Nonmaskable Interrupt- interrupt signal that must be received by the

microprocessor.

6.1.2.2 The interrupt advantage

1. To ensure the I/O devices or peripheral devices interrupting microprocessor to initiate.

2. Reduce time and cost in such away that interrupt only occurs when microprocessor receive an interrupt signal.

6.1.3 Direct Memory Access

In direct-memory access (DMA), data transfer between memory and a peripheral is controlled externally; that is, the microprocessor is not involved during the transfer. This method is used in cases where microprocessor control would be too slow.

The 8085A has two pins used for DMA. These are the HOLD and HLDA (hold acknowledge). The HOLD signal is recived by the 8085A from an external source.

The DMA process requires a controller chip. For the MCS-85 family, this chip is the 8257 DMA controller. A diagram of the system is shown in figure 6.2.

A DMA is initiated by a low to high input to the HOLD line of the 8085A.

The 8085A completes the execution the machine cycle in progress.

Puts the buses in high impedance state, and sends the HLDA signal to the 8257.

The 8257 then take over the bus system and proceeds with the thansfer of data. In effect, it takes the place of


microprocessor. The transfer is directly between memory and the peripheral I/O.

when the transfer of data has been completed, the 8257 returns control of the buses to the 8085A by dropping the HOLD signal low.

Figure 6.2 8085 System with DMA controller


6.1.4 Hand-shaking

The handshake is a means of transfer of data between a microprocessor and a slower peripheral. To carry out this transfer, there is an exchange of control signal between the microprocessor and peripheral.

If there is to be input to the microprocessor, the peripheral first signal it is ready to send the data. The microprocessor than signals that it is ready to receive the data. The transfer goes ahead. Having received the data, the microprocessor signals the peripheral that the transfer is complete.

If there is to be output from the microprocessor, the peripheral first signals that data are available. The data are transferred. When the transfers are complete, the peripheral signals the microprocessor.

For the MCS-85 system, the 8155 can be used for handshake transfer of data. The three ports of 8155 as an example were configured as simple input or output ports; figure 6.3 shows the block of the 8155 RAM. Port C can also be used for control and status signals when a port A and B are used in the handshake mode.

PA0-7

PB0-7

256 x 8STATIC RAM

TIMER

A

B

C

PORT A

8

PORT B

8

8 PC0-5

TIMER CLK

TIMER OUT

IO/M

Vcc (+5V)

Vss (0v)

AD0-7

*

ALE

RD

WR

RESET


Figure 6.3 The block of the 8155 RAM

6A-1. Under the unconditional I/O transfers, how can data be transfered between MPU and I/O devices.

6a-2. When can unconditional data transfer be used.

6a-3. What is an interrupt?

6a-4. Describe about the Hardware interrupt and software interrupt and how is software interrupt initiated.

6a-5. Name and describe two type of interrupt.

1. Maskable Interrupt- Interrupt signals that been receive or not by

microprocessor.

3. Nonmaskable Interrupt- interrupt signal that must be recive by the

microprocessor.

6a-6. What is the interrupt advantage during the data transfer.

6a-7. What is the defination of Handshake.

ACTIVITY – 6A

TEST YOUR UNDERSTANDING BEFORE YOU CONTINUE TO THE NEXT INPUT….!


6A-1. Under the unconditional I/O transfers, how can data be transfered between MPU and I/O devices.

MPU and I/O can be initiated either by the MPU or by the devices.

6a-2. When unconditional data transfer can be used.

The unconditional data transfer is used only in situation where an output devices is always ready to accept data from MPU or an input devices always has data ready for the MPU.

6a-3. What is an interrupt?

Interrupt is a signal that causes the microprocessor to end its normal execute to initiated interrupt operation.

6a-4. Describe the Hardware interrupt and software intrrupt and how software interrupt initiated.

Hardware interrupt occurs when microprocessor interrupt pin given truth logic. Example the MIC 68000 interrupt pin is RESET. Software in the otherhand need an instruction programming to be initiated.

6a-5. Named and desribed two types of interrupt.

1. Maskable Interrupt- interrupt signals that has been recived or not by

microprocessor.

4. Nonmaskable Interrupt- interrupt signal that must be recived by the

microprocessor.

6a-6. What is the interrupt advantage during the data transfer.

The interrupt advantage

FEEDBACK TO ACTIVITY – 6A


1. To ensure the I/O devices or peripheraldevices interrupting microprocessor to initiate.

2. Reduce time and cost in suchway that interrupt only occurs when microprocessor recived an interrupt signal.

6a-7. What is the defination of Handshake.

Means the of transfer of data between a microprocessor and a slower peripheral


6.2 Techniques in feeding and fetching data in series or parallel from computer.

6.2.1 Digital data can be transfered to other location as a series or parallel.

Series data transfer

- Binary data been transfer in one line, one bit at a time.

- Transfering data are slow.- Usually used for trank data transfer, example if

microprocessor been connected to peripheral telephone line.

Parellel data transfer

- Every data bit have its own line and been transfered simultaneously.

- Data transfer in synchronous either in form of byte, word or longword.

- Much faster data transfer.- Usually used if the speed are count.- This transfer methods used to transfer data in the

computer between;

1. CPU and memory2. CPU and I/O devices3. Memory and I/O devices.

INPUT-6B

Computer A

Computer BSeries technique of transfer


Disadvantage

- High cost in using wires- and registers.- Gainer noise during data transfer between computer

or computer with peripheral devices.

6.2.2 Parallel and serial interface characteristic

- Transferring data by microprocessor using serial and parallel method during interfacing with peripheral devices.

- interfacing chips that can be use such as, PIA, PI, ACIA and UART.

Parellel Interface

- Two example parellel interface chips, PIA (peripheral interface adapter) and PPI (programmable peripheral interface).

- PIA are used to interfacing peripheral devices with CPU in parellel through data bus (example 8 bit data bus)

- All data line that been used can be programmed as input and output.

Computer Printer

Parallel data transfer (4 bit)


Example: PIA which is used as interface peripheral I/O with CPU.

Data Bus

Consist of two part which are the “CPU Side” and “peripheral Side"

- CPU and PIA are connected through data bus, address bus and control bus.

- 8 line data bus bidirectional D0-D7, execute data to be send between CPU and PIA

- PIA consist of two port, PORT A and Port B.- Every port have 8 line data bus (PA0 –PA7 and PB0 -PB7 )- can be programmed to input or output

Serial Interface

- Two examples of series interface chip, ACIA ( Asynchronous Communication Interface Adapater) and UART (Universal Asynchronous Receiver-Transmitter).

- ACIA are the main source for series data, the function is to interface between series and parellal data.

- The data which came through ACIA are in series, this data will be store in data register before synchronously sent in parallel as shown below,

CPU RAM ROM PIA

PORT A (output)

PORT B (input)

Data 0 –7 parellal output

7 6 5 4 3 2 1 0Data series input


- In computer system, ACIA is needed when the signal from peripheral devices are series, as we know that the data movement in microprocessor system are parellal, so every signal that came in must be converted to parellal signal before the CPU can process it.

- in the opposite ways , if any data from microprocessor which will be send to peripharel devices, the data first need to be converted from parrellel to series.

- As an example, modem are use to send or receive data from telephone line.

- UART ( Universal Asynchronous Receiver-Transmitter)

Computer UART Peripheral Devices

Perrellal data bus

Series data bus

INPUT/OUTPUT AND INTERFCE E3165 / UNIT 6 / 14

6.2.3 Asynchronous serial data comunication

Most of the serial data communication performed by microcomputers uses asynchronous communication. Figure 6.4 shows the basic hardware arrangement needed for an MPU to communicate with a serial I/O device. The interface circuit performs two basic operations;

1. Takes an 8-bit parellel data word from the MPU data bus and converts it to a serial data word to be sent to the serial device

2. Takes a serial data from the serial device and converts it to an 8-bit parellel data word that is transferred to the MPU via data bus.

Figure 6.4; MPU interfaced to a serial device

(Source: Ronald J. Tocci; page 421; figure 9.5)

Figure 6.5 A serial data signal is divided into time intervals called bit times


A serial data signal is divided into time intervals called bit times (see fig. 6.5). during each bit time interval (TB), the signal is either a 0 or a 1; it can change logic levels only at the start of a new bit time interval.

In serial data communication, the terms mark and space are often used to represent logic 1 and 0, respectively. This terminology is a carry-over from the use of Morse code in telegraphy.


When asynchronous serial data are transmitted between two devices such as an MPU and a video terminal, a standard format is used to transmit a single data word. This format (Figure 6.6A) consists of three (or optionally, four) parts;

1. A START bit, which is always a logic 0 ( that is, space).

2. Five ti 8 data bits, representing the actual information being transmitted. The LSB is normally transmitted first.

3. An optional parity bit for error-detection capability. If the parity bit is included, either odd or even parity can be used.

4. One, 1½,* or 2 STOP bits, which are always 1s. Most frequently, there will be 2 STOP bits.

*One and a half STOP bits would be represented as a 1½ level, which last for 1 bit times (i.e 1.5 TB)

For given a system, the number of data bits, the parity-bit option, and the number of STOP bit are fixed by the design. Figure 6.6B shows ans example of a serial data word that uses 7 data bits, an even parity bit, and 2 STOP bits. This is the format used by most terminals, where the 7 data bits are the ASCII code for the alphanumaric character being transmitted.The completed serial data word in figure 6.6B begins with a START bit of 0.

The signal line is assumed to be transmitted a constant HIGH level prior to the START bit. This is called marking or idling. Whenever data word is not being trnasmitted, the signal line will always be marking.

Thus, the beginning of each transmitted data word is characterized by a I to 0 transition when the START bit occurs.

Here the Start bit is followed by 7 bits of data, beginning with the LSB and ending with the MSB, thus, the actual data transmitted here are read as 1001011, which happens to be the ASCII code for the letter K.

The data bits are followed by an even-parity bit; in this case it is a 0, since the 7 bits of data contain an even number of 1s. the parity bit is followed by 2 STOP bits, which are always 1s.


Figure 6.6A; Standard asynchronous serial data format; (B) example of a serial data word using 7 data bits, an even-parity bit, and 2 STOP bits. tHe data represented here are 1001011, which is the ASCII code for the letter K.


Baud Rate

The term baud is use to identify the rate at which the data signal is changing in a serial communication system. In general, the

the baud is given by

Baud Rate = 1

Time between transition

If, for instance, the signal is changing every 1 ms, the baud rate would be 1/1ms = 100 Baud.

The baud is a measure of how frequently the serial signal is changing, and a relative indication of the bandwidth required for a communication channel to transmit the signal faithfully. A

( Baud )


higher baud rate means the signal is changing more rapidly and would require a greater channel bandwidth.

In some situation, but not always, the baud rate is equivalent to the rate at which data bits are being transferred. For example, in the standard asynchronous serial data format (figure 6.6 ) a new bit is sent every bit time interval (TB), so that data bits are being transferred at rate given by

Data Rate = 1

TB

If TB = 1 ms, the data rate becomes 1000 bits/s. the baud rate ia also 1000 because the time between signal transition is equal to 1 ms. Thus, in this simple serial data format the baud rate and data rate are the same, although they are expressed in different units – 1000 bits/s versus 1000 Baud.

Example 1

A certain video display terminal is operating at a baud rate of 9600 using the standard asynchronous serial format. What is the time duration of one bit in the serial data going to and from from this terminal?

Solution;

For this situation the baud rate and data rate are the same. Thus, since data rate = 9600 bits/s, the bit time will be 1/9600 = 104.17 s.

6.2.4 Synchronous serial data communication

(bita/s)


This is a more efficient, yet more costly, method of transferring serial data. In synchronous serial communication, the individual data words are transmitted continuously one after the other (i.e., a block of data) without any intervening START or STOP bits.

The receiver is synchronized to the transmitter through the use of special sync characters that the transmitter sends before each of data.

The transmitter also continuously sends these sync characters when the communication channel is idle (no data being transmitted). The sync character is a special agreed-upon character code. When ASCII character codes are being used, the sync character code is 000101102 = 166, which is given the mnemonic SYN.

The receiver uses the SYN character to synchronize its internal; clock with that of the transmitter. When a transmitter stop sending SYN character and begins sending a message, the receiver automatically knows that every 8 bits serial data (i.e., ASCII characters) following the SYN character and convert them to parallel data that can be read by a computer.

Several message formats are used in synchronous serial communication. One of the more popular is illustrate in figure 6.7. It is part of the binary synchronous communications protocol or BISYNC, for short. This diagram shows a typical transmission sequence with time progressing from left to right. It begins with the transmitter sending SYN characters while it is idling.

When the transmitter is ready to send a message (i.e., data), it will send a special character called start-of-text (STX) which in ASCII is 0216.

The STX character tells the receiver that the message characters will follow. The transmitter than send a block of ASCII characters that represent the message. The message portion may contain 128 or 256 characters (this will vary from system to system).

The transmitter sends an end-of-text (ETX) character to indicate the end of the message. The ASCII code for ETX is 03. Immediately following the EXT character, a block check character (BCC) is sent.

BCC is not an ASCII code; it is a single byte that represent some complex parity information calculated from the data bytes in the message. The function of the BCC is to detect if any error has occurred in the transmission or reception of the data. The receiver can recalculate its own BCC from the data in the message, and compare it with the BCC sent by the transmitter. If they are different, the receiver can send a message to the transmitter requesting that it send its previous message over again.


After the BCC character, the transmitter can send the next portion of the message by first sending two SYN characters which the receiver can use to resynchronize its clock, followed by an STX character and the data. If the transmitter has no more data to send (i.e. the complete message has been sent), it will send continuous SYN characters.

Synchronous communication is more efficient than asynchronous because only about 2 or 3 percent of the transmitted data is taken up by SYN characters and other special characters, compared to about 20 percent for asynchronous. However the transmitter and receiver circuitry for synchronous operation is more complex.

Figure 6.7; Typical transmission synchronous communication sequence using BISYNC format


INPUT/OUTPUT AND INTERFACE E3165 / UNIT / 20

6B-1. State the two technics of data transfer

6B-2. Describe briefly on how parallel data transfer is done.

6B-3. What is the disadvantage in using parallel technics

6B-4. Named two example of parallel interface chip that you know

6B-5. Named two example of serial interface chip that you know

6B-6. what is the ACIA function in computer system.

6B-7. In Asynchronous serial data communication, show/draw the basic block diagram hardware arrangment need for MPU to communicate with a serial I/O device.

6B-8. In serial data communication, the term mark and space are represent logic?

6B-9 .Describe three or four parts which took place as a format during data transmite?

6B-10. show/draw the block diagram and labeled which, stop bit, data bit, even bit and 2 stop bit – example of a serial data words that uses 7 data bits.

6B-11. Create or show the start bits, data bits, even bits and 2 stop bits for letter A – refer the ASCII

ACTIVITY – 6B



6B-12. State the Baund rate formula?

6B-13. What is the Baund Rate if Time Between Transition is 0.5 ms.

6B-14. When do the synchronous serial data communication start receiving data.

6B-15. What is the different between asynchronous and synchronous serial data communication format of transmit data.


6B-1. State the two technics of data transfer

1. Series data transfer

2. Parallel data transfer

6B-3. Describe briefly on how parallel data transfer is done.

- every data bit has its own line and been transfer simultaneously.

- Data transfer in synchronous either in form of byte, word or longword.

- Much faster data transfer.- Usually used if the speed are counted.- This transfer methods used to transfer data in the

computer between;

4. CPU and memory5. CPU and I/O devices6. Memory and I/O devices.

6B-4. What are the disadvantages in using parallel technic

Disadvantage

- High cost in using wayer and registers.- Gainer noise during data transfer between computer

or computer with peripheral divices.

FEEDBACK TO ACTIVITY – 6B

Computer Printer

Parellel data transfer (4 bit)


6B-5. Named two example parallel interface chip that you know

- Two example of parellel interface chips, PIA (peripheral interface adapter) and PPI ( programmable peripheral interface).

6B-6. Name two examples of serial interface chip that you know

- Two examples series interface chip, ACIA ( Asynchronous Communication Interface Adapater) and UART (Universal Asynchronous Receiver-Transmitter).- Two examples of series interface chip, ACIA ( Asynchronous Communication Interface Adapater) and UART (Universal Asynchronous Receiver-Transmitter).

6B-7. what is the ACIA function in computer system.

- In computer system, ACIA is needed when the signal from peripheral devices are series, as we know that the data movement in microprocessor system are parellal, so every signal that came in must be converted to parellal signal before the CPU can process it.

6B-9. In serial data communication, the term mark and space are represent logic?

Mark and Space are often used to represent logic 1 and 0.

6B-10 .Describe three or four parts which took place as a format during data transmite?

1. A START bit, which is always a logic 0 ( that is, space).

3. Five ti 8 data bits, representing the actual information being transmitted. The LSB is normally transmitted first.

4. An optional parity bit for error-detection capability. If the parity bit is included, either odd or even parity can be used.

5. One, 1,* or 2 STOP bits, which are always 1s. Most frequently, there will be 2 STOP bits.

*One and a half STOP bits would be represented as a 1 level, which last for 1 bit times (i.e 1.5 TB)


6B-11. Show/draw the block diagram and lebeled which, stop bit, data bit, even bit and 2 stop bit – example of a serial data words that uses 7 data bits.

6B-12. Create or show the start bits, data bits, even bits and 2 stop bits for letter A – refer the ASCII

6B-13. State the Baund rate formula?

Baund Rate = 1 Baund

Time Between Transition

6B-14. What is the Baund Rate if Time Between Transition is 0.5 ms.

Baund Rate = 1 / 0.5 ms = Baund

6B-15. When do the synchronous serial data communication start receiving data.

When a transmitter stop sending SYN character.

6B-16. What is the different between asynchronous and synchronous serial data communication format of transmit data.


6.3 PPI 8255A/PIA 6821

6.3.1 Description of The Block diagram, Register Function and Programmable Interface Process.

A more in-depth look at the MC 6821 is necessary to get a full grasp of the power and flexibility that this chip provides microcomputer system designers. Figure 6.8 shows the block diagram of the MC 6821.

The chip can be thought of as two completely independent 8-bit I/O ports. Ports A and B contain data direction registers (DDRA, DDRB) wich allow the programmer to specify independently each pin of both ports as either an input or an output pin.

Putting a “0” in a data direction register bit causes the corresponding pin on the port to act as an input.

Placing a “ 1 “ in a particular bit position of the DDR causes the corresponding pin on the port to act as an output.

The control registers ( CRA, CRB ) allow the programmer to choose certain interrupt and peripheral control capabilities. Also, the control register provides certain status information concerning interrupt activity.

The output registers (ORA,ORB) hold data that are to be sent to output devices until such devices are ready to accept it. Inputs CA1, CA2, CB1 and CB2 can be ued as status inputs for conditional I/O transfer, or for interrupt interfacing cpabilities. Under softwarecontrol CA2 and CB2 can be programmed, via the control register, to act as peripheral control outputs that can be used in various handshaking schemes.

In dealing with this chip the MPU must be able to communicate with six different registers. In Fig. 6.8 you will notice that the CHIP SELECT and control section has only two register select inputs, RS0 and RS1.

This seems to indicate that the MPU can only communicate with four registers. However, one bit in each control register is used to distinguish between addressing of the data direction register and the output register.

INPUT-6C

R/W


This allows the choice then of the communicating with one of six different registers; two data direction registers, two control registers, and two output registers. The REGISTER SELECT and CHIP SELECT input operate in the same manner as those of the 6850 UART.

Figure 6.8; Block diagram of the MC 6821 PIA

PPI 8255A


The 8255A is a programmable peripheral interface (PPI) device designed for use in Intel microcomputer systems. Its function is that of a general purposes I/O component to Interface peripheral equipment to the microcomputer system bush. The functional configuration of the 8255A is programmed by the systems software so that normally no external logic is necessary to interface peripheral devices or structures.

Data Bus Buffer

This 3-stable bi-directional 8-bit buffer is used to interface the 8255A to the systems data bus. Data is transmitted or received by the buffer upon execution of input or output instructions by the CPU. Control words and status information are also transferred through the data bus buffer.

Read/Write and Control Logic

The function of this block is to manage all of the Internal and External transfers of both Data and Control or Status words. It accepts inputs from the CPU Address and Control business and in turn, issues commands to both of the Control Groups.

(CS)

Chip Select. A “low’ on this input pin enables the communication between the 8255A, and the CPU.

(RD)

Read. A “low” on this Input pin enables the 8255A to send the data or status information to the CPU on the data bus. In essence, it allows the CPU to “read from the 8255A.

(WR)

Write. A. “ low” on the input pin enables the CPU to write data or control words into the 8255A.

(A0 and A1) Port Select 0 and Port Select 1. The Input signals, in conjunction with the RD and WR Inputs, controls the selection of one of the three ports or the control word registers. They are normally connected to the least significant bits of the address bus (A0 and A1).


8225 BASIC OPERATION

Figure 6.9; 8255 A Block Diagram Showing Data Bus Buffer and Read/Write Control Logic Functions

A1 A0 RD WR CSINPUT OPERATION (READ)

0 0 0 1 0 PORT A - DATA BUS0 1 0 1 0 PORT B - DATA BUS1 0 0 1 0 PORT C - DATA BUS

OUTPUT OPERATION (WRITE)

0 0 1 0 0 DATA BUS - PORT A0 1 1 0 0 DATA BUS - PORT B1 0 1 0 0 DATA BUS - PORT C1 1 1 0 0 DATA BUS - CONTROL

DISABLE FUNCTIONX X X X 1 DATA BUS - 3 STATE1 1 0 1 0 ILLEGAL CONDITIONX X 1 1 0 DATA BUS - 3 STATE


(RESET)

Reset. A “high” on this Input clears the control register and all ports (A, B, C) are set to the Input mode.

Group A and Group B Controls

The functional configuration of each port is programmed by the systems software. In essence, the CPU “output” a control word to the 8255A. The control word contains information such as “mode”, bit set”, bit reset”, etc. that Initializes the functional configuration of the 8255A.

Each of the Control blocks (Group A and Group B) accepts commands from the Read/Write Control Logic, receives control words from the internal data bus and issues the proper commands to its associated ports.

Control Group A – Port A and Port C upper (C7 C4)

Control Group B – Port B and Port C lower (C3 C0)

The Control Word Register can only be written into. No.

Read operation of the Control Word Register is allowed.

Ports A, B, and C The 8255A contains three 8-bit ports (A , B, and C). All can be configured in a wide variety of functional characteristics by the system software but each has its own special features or personally to further enhance the power and flexibility of the 8255A.

Port A. One 8 bit data output latch/buffer and one 8-bit data input latch.

Port B. One 8-bit data output latch/buffer and one 8-bit data input buffer.

. One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input). This port can be divided into two 4-bit ports under the mode control. Each 4-bit port contains a 4-bit latch and it can be used for the controls signal outputs and status signal inputs in conjunction with ports A and B. ACTIVITY – 6C



6C-1. Refering to figure 6.7, describe briefly DDRA,DDRB,CRA,CRB, ORA and ORB.

6C-2. What is the main advantage of unconditional transfer.

6c-3. How can the data transfer take place by using the 6821 for conditional transfer.

6C-4. In PPI 8255A, define the function READ/WRITE and Control logic


6C-1. Refering to figure 6.7, describe briefly DDRA,DDRB,CRA,CRB, ORA and ORB.

DDRA,B - Data direction register A or B

- which allow the program to specify independently each pin of both ports.

CRA,B - Control register A or B

- Allow the register to choose certain interrupt and peripheral control capability.

ORA,B - Output register A or B

- hold data that are tobe sent to output devices until such devices are ready to accept.

6C-2. what is the main advantage of unconditional transfer.

The main advantage of this type of interface chip ii its programmability.

6c-3. How can the data transfer take place by using the 6821 for conditional transfer.

A conditional transfer of data can easily be implemented using the 6821. Each control register has 2 read-only bits or flags reserved for status information. This flags are activated by inputs CA1, CA2 or CB1, CB2, respectively.

6C-4. In PPI 8255A, define the function READ/WRITE and Control logic

The function of this block is to manage all of the Internal and External transfers of both Data and Control or Status words. It accepts inputs from the CPU Address and Control business and in turn, issues commands to both of the Control Groups.

FEEDBACK TO ACTIVITY – 6C


6.4 Describe function And Examples Interface I/O Circuit

6.4.1 ADC/DAC

Most physical variables are analog in nature and can take on any value within a continuous range of values. Examples include temperature, pressure, light intensity, audio signal, position, rotational speed, and flow rate. Digital system perform all of there internal operatiions using digital circuitry and digital operations. Any information that has to be input to a digital system must first be put into digital form. Similarly, the outputs from a digital system are always in digital form. When a digital form such as computer is to be used to monitor and/or control a physical process, we must deal with the difference between variables. Figure 6.10 illustrate the situation. This diagram shows the five elements that are involved when a computer is monitoring and controlling a physical variable that is assumed to be analog.

Figure 6.10 Analog to digital converter (ADC) and digital to analog (DAC) are used to interface a computer to the analog world so that the computer can monitor and control a physical variable.


INPUT-6D


1. Transducer. The physical variable is normally a nonelectrical quantity. A transducer is a device that converts the physical variable to an electrical variable. Some common transducer include thermistors, photocells, photodiodes, flow meter, pressure transducers, and tachnometers. The electrical output of the transducer is an analog current or voltage that is proportional to the physical variable it is monitoring. For example, the physical variable could be the temperature of a water in a large tank that is being filled from cold and hot water pipes. Let’s say that the water temperature varies from 80 to 150 oF and that a thermistor and its associated circuitry convert this water temperature to a voltage ranging from 800 to 1500 mV. Note that transducer’s output is directly proportional to temperature, such that each 10F produces a 10 mV output. This proportionality factor was chosen for convenience.

2. Analog to digital converter (ADC). The transducer’s electrical analog output serves as the analog input the ADC. The ADC converts this analog input to a digital output. This digital output consists of a number of a bits that represent the value of the analog input. For example, the ADC might convert 01010000 (80) to 10010110 (150). Note that the binary output from the ADC is proportional to the analog input voltage so that each unit of the digital output represent 10 mV.

3. Computer. The digital representation of the process variable is transmitted from the ADC to the digital computer, which store the digital value and processes it according to a program of instruction that is executing. The program might perform calculations or other operation on this digital representation of temperature to come up with a digital output will eventually be used to control the temperature.

4. Digital to Analog Converter (DAC). This this digital output form the computer is connected to a DAC, which convert it to a proportional analog voltage or current. For example the computer might produce a digital output ranging from 00000000 to 11111111, which the DAC converts to a voltage ranging from 0 to 10 v.

5. Actuator. The analog signal from the DAC is often connected to some device or circuit that serves as an actuator to control the physical variable. For our water temperature example, the actuator might be an electrically conrolled valve that regulates the flow of hot water into the tack in accordance with the analog voltage from the DAC. The flow rate would vary in proportion to this analog voltage, with 0v producing no flow and 10 v producing the maximum flow rate.


Thus we see that ADCs and DACs fuction as interface between a completely digital system, like a computer, ad the analog world. The function has become increasingly more important as inexpensive microcomputers have moved into areas of process control where computer control was previously not feasible.

Input/Output And Motor Control Circuit.

Basically, D/A conversion is the process of taking a value represented in digital code (such as straight binary or BCD) and converting it to a voltage or current which is proportional to the digital value. Figure 6.11a shows the symbol for a typical 4-bit D/A converter. We will examine the various input/output relationships.

Figure 6.11 Four bit DAC with voltage output.(Source: Ronald J. Tocci; page 564; figure 10.2)

The digital inputs, D, C, B and A are usually derived from the output register of a digital system. The 24 = 16 different binary numbes represented by these 4 bits are listed in figure 6.11b. For each input number, the D/A converter output voltage is a unique value. In fact, for this case, the analog output voltage Vout is equal in volts the binary number. It could also have been twice the binary number or some other proportionality factor. The same idea would hold true if the D/A output were a current Iout.

In general,

Analog output = K x digital input


Where K is the proportionality factor and is a constant value for a given DAC. The anaog can of course be a voltage or current. When it is a voltage, k will be in voltage units, and when the output is current, k wil be in current units. For the DAC of figure 6.12, K = 1v, so that

Vout = ( 1 v ) X digital input

We can use this to calculate Vout for any value of digital input. For example, with a digital input of 11002 = 1210 we obtain

Vout = 1 v X 12 = 12 v

Example 2

A 5 bit Dac has a current output. For a digital input of 10100, an output current of 10 mA is produced. What will I out be for a digital input of 11101?

Solution

The digital input 101002 is equal to decimal 20. Since Iout =m 10 mA for this case, the proportionality factor must be 0.5 mA. Thus we can find Iout for any digital input such as 111012 = 2910 as follows;

Iout = (0.5 mA ) x 29 = 14.5 mA

remember, the proportionality factor, k will vary from 1one DAC to another


Resolution (Step Size). Resolutin of a D/A converter is defined as the smallest change that can occur in the analog output as a result of a change in the digital input. Refering to the table in figure 6.11 we can see that the resolution is 1 v. since Vout can change by no less than 1 v when the digital input value is changed. The resolution is always equal to the weight of the LSB and is also referred to as the step size, since it is the amount that Vout will change as the digital input value is changed from one step to the next. This is illustrate better in figure 6.12 where the output from a 4 bit binary counter provide the inputs to to our Dac. As the counter is being continually cycled through its 16 state by the clock signal, the Dac output is a staircase waveform that goes up 1 v per step.

When the counter is at 1111, the Dac output is at its maximum value of 15 v, this is full-scale output. When the counter recycles to 0000, the Dac output returns to 0 v. the resolution or step size is the size of the jumps in the staircase waveform in this case each step is 1 v.

Figure 6.12; Output waveform of DAC as inputs are provided by a binary counter.


Note that the staircase has 16 levels corresponding to the 16 input state,but there are only 15 step or jumps between the 0 v level and full-scale. In general, for an N-bit Dac the number different level will be 2N and the number of steps will be 2N – 1.


You may have already figured out the resolution (step size) is the same as the proportionality factor in the Dac input/output relationship.

Analog output = K x digital input

A new interpretation of this expression would be that the digital input is equal to the number of the step, K is the amount of voltage (or current) per step,and the analog output is the product of the two.

Figure 6.13 shows a computer controlling the speed of a motor. The 0 to 2 mA analog current from the DAC is amplified to produce motor speed from 0 to 1000 rpm (revolutions per minute). How many bits should be used if the computer is to be able to produce a motior speed that is within 2 rpm of the desired speed?

Figure 6.13; Example of computer controlling speed motor.(Source: Ronald J. Tocci; page 569; figure 10.4)


Solution

The motor speed will range from 0 to 1000 rpm as the DAC goes from zero to full scale. Each step in the DAC output will produce a step in the motor speed. We want the step size to be no greater than 2 rpm. Thus we need at least 500 steps (1000/2). Now we must determine how many bits are required so that there are at least 500 steps from zero to full scale. We know that the number of steps is 2N – 1, and so we can say

2N - 1 500

or

2N - 1 501

since 28 = 256 and 29 = 512, the smallest number of bits that will produce at least 500 steps in nine. We could use more than 9 bits, but this might add the cost of the DAC.


6D-1. Why do the analog form/value need to be converted to digital form?

6D-3. What is transducer in ADC/DAC?

6D-4. Briefly describe Actuator

6D-5 Define K in DAC?.

6D-6. Using the analog output formula,assuming K 1v, what is the Vout for

digital input 0110?

ACTIVITY – 6D



6D-1. Why do the analog form/value need to be converted to digital form?

Digital system perform all of there internal operatiions using digital circuitry and digital operations. Any information that has to be inputted to a digital system must first be put into digital form.

6D-3. what is transducer in ADC/DAC?

The physical variable is normally a nonelectrical quantity. A transducer is a device that converts the physical variable to an elevtrical variable

6D-4. Briefly describe Actuator

The analog signal from the DAC is often connected to some device or circuit that serves as an actuator to control the physical variable.

6D-5 Define K in DAC?.

K is the proportionality factor and is a constant value for a given DAC

6D-6. Using the analog output formula,assuming K 1v, what is the Vout for

digital input 0110?

V out = 1 v X 6 ( 0110 ) = 6 v.

FEEDBACK TO ACTIVITY – 6D


You are approaching success. Try all the questions in this self-assessment section and check your answers with those given in the Feedback on Self-Assessment 1 given on the next page. If you face any problem, discuss it with your lecturer.

Good Luck

Question 1:

1. With the help of diagram, derive point by point on how interrupt is initiated?

1. When a microprocessor receive interrupt request signal, the process will proceed until it end cycle before entertain the interrupt signal.

2. The instruction of program counter (PC) and register will be stored in stack with LIFO ways. Now PC will remember the new address for interrupt sequence to enhance the microprocessor in initiated interrupt sequence.

3. After executing interrupt sequence, PC will again be filled by the data in PC and register that already been stored in stack before.

4. Microprocessor will now return to initiate its original program operations.

SELF-ASSESSMENT 1 U1

Interrupt request signal

Main Program

interrupt service routine

After completion of interrupt service routine, control return to original program


2. Explain what is an exchange of control signal between the microprocessor and peripheral .

If there is to be input to the microprocessor, the peripheral first signal it is ready to send the data. The microprocessor than signals that it is ready to receive the data. The transfer goes ahead. Having received the data, the microprocessor signals the peripheral that the transfer is complete.

If there is to be output from the microprocessor, the peripheral first signals that data are available. The data are transferred. When the transfers are complete, the peripheral signals the microprocessor

3. In digital data transferring, explain what is serial data transfer with the help of a diagram

- Binary data been transfer in one line, one bit at a time.

- Transfering data are slow.- Usually used for trank data transfer, example if

microprocessor been connected to peripheral telephone line.

Computer A

Computer BSeries technique of transfer


4. In asynchronous serial data communication, explain with the help of a diagram, how MPU communicate with a serial I/O device ( take 8 bits as a data ).

1. Takes an 8-bit parellel data word from the MPU data bus and converts it to a serial data word to be sent to the serial device

2. Takes a serial data from the serial device and converts it to an 8-bit parellel data word that is transferred to the MPU via data bus.

5. Define the function of CS – chip selecter, RD – READ, WR-WRITE, and RESET

CS - Chip Select. A “low’ on this input pin enables the communication between the 8255A, and the CPU

RD - Read. A “low” on this Input pin enables the 8255A to send the data or status information to the CPU on the data bus. In essence, it allows the CPU to “read from the 8255A

WR - Write. A. “ low” on the input pin enables the CPU to write

data or control words into the 8255A


6. Draw the basic block diagram, analog to digital converter.

7. What is the largest value of output voltage from an 8-bit DAC that

produce 1 v for a digital input of 00110010?

001100102 = 5010

1 v = K x 50

therefore = 20 mv

the largest o/p will occur for an i/p of 111111112 = 25510

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