Universal serial bus implementation in an integrated access chip for ISDN systems

H.Cruickshank, Z.Sun and Z.Fan

Abstract: The universal serial bus technology comes as a response to the increasing demands for unlfied interfaces and the need for flexible easy-to-use products for personal computers. Integrating this technology into PBXs and ISDN ICs can play an important role in the integration of telecommunications and computer technologies. The paper reports the findings of a research project called COPARIS for ISDN chip design with the additional USB interface. It also presents the software and hardware design approaches for implementing USB functions in the COPARIS chip. The research indicates that a balanced approach is the best, where the computationally intensive functions should be implemented in hardware and the rest in software.

1 Introduction

The universal serial bus (USB) is an expansion scheme that replaces the serial cards in a PC. It provides a high-speed serial connection to the Pc‘s bus and as many as 63 devices can be connected to the same bus [ 11. Today, computer-tel- ephone integration and video conferencing through digital cameras and computers have become a necessity in the work place and are starting to make their way into homes. These two interrelated communication functions, along with future PBXs and a number of standard PC peripher- als, such as keyboards, joysticks and mice, wdl benefit from USB usage [2-51.

In ISDN systems, small and medium-sized private branch exchanges (PBX) represent the most evolving ele- ments in terms of both growth and required advancements in technical features. Advanced PBXs with both telephone and datacom interfaces (i.e. Internet access) can offer signif- icant cost benefits to their users, where the target is the small officehome office (SOHO) systems. As an example, such a PBX could automatically select the PSTN interface (analogue or ISDN) for local telephone calls and the ‘telephony over internet’ service for low-cost international calls to subscribers with similar facilities [6]. The implemen- tation of USB functionality in such PBXs provides seam- less integration between telephone and Internet applications.

The constantly increasing demand for high-speed inte- grated communications drives the development of advanced ISDN chip design to provide both telecom and datacom services. Telecommunications systems manufac- turers and component designers face increasing demand for cheaper and more integrated products to satisfy user requests for seamless and cost-efficient service integration and network interconnectivity.

0 IEE, 2001 IEE Proceedizgs online no. 20010397 DOL 10.1049/ipcom:20010397 Paper fmt received 7th October 1999 and in revised form 27th March 2001 H. Cruickshank and Z . Sun are with the University of Surrey, Guildford GU2 m, UK Z. Fan is with Infimeon TechnologieS k Ltd, Bristol, UK

Programmability and easy reconfiguration are key requirements for future ISDN systems. For traditional application specific integrated circuits (ASIC), the reconfig- uration can only be implemented on a major redesign basis, which requires a considerable effort and development time, thus increasing cost. A programmable DSP core can be incorporated in the integrated circuit (IC) architecture to implement a significant part of these functions in software. Thus the functional modifications will be easier by a simple software reprogramming. One example of such reprogram- ming is addindenhancing USB functionality. This approach offers an efficient way for realising modifications at minimal cost and in a relatively short time.

This paper presents a study within the common physical access chip for ISDN systems (COPARIS) project for implementing USB in a balanced approach between hard- ware and software. COPARIS is a European ESPRIT research project.

2

2.1 USB basic concepts USB is a communication protocol that supports serial data transfers between a USB host computer and USB-capable peripherals. The host serves as the master of the bus. Data transfer is serial with two modes of signalling: full-speed mode with a signalling rate of 12Mbit/s, and low-speed mode with a signalling rate of lSMbit/s [7, 81. The periph- erals act as slaves connected to the host through hubs, in a tiered star topology, with a hub at the centre of each star as shown in Fig. 1.

USB provides facilities such as ease-of-use connectivity to the PC, flexibility and low-cost implementations. This is in addition to the ‘plug and play’ feature, which is one of the main reasons behind the inception of USB. With USB, users can connect or disconnect a peripheral without hav- ing to reconfigure or alter the setup, or be concerned with what plugs to use for their peripherals, because of the standard connection interface.

In general, USB transactions consist of up to three pack- ets: a token packet, a data packet and a handshake packet. Each packet has a packet ID (PID) that specifies its type. A transaction starts when the host sends a token packet

COPARIS approach in USB system design

207 IEE ProcCommun., Vol. 148. No. 4, August 2001

with a device address, and endpoint number and the direc- tion of data transfer. The addressed device selects itself by decoding its address from the token. If the direction field in the token indicates that the host is aslung for data, the device responds with a data packet, otherwise, the host fol- lows up with the data packet. In general, after the data is received the destination (host or device) sends a handshake packet to acknowledge the reception of that packet.

(root tier)

tier 1 hub 1

4

Fig. 1 USB bus topology

2.2 COPARIS architecture overview The main objective of COPARIS is to define a new archi- tecture for small and medium size PBX for SOH0 systems. The COPARIS design approach is to maximise the transfer hardware functionality into software without compromis- ing system performance [&9]. The incorporation of a USB interface into the COPARIS IC archtecture provides a number of additional capabilities:

port expansion; low-cost solution for supporting up to 12MbiUs serial

interface; direct PC compatibility for ISDN applications; and

full support for the real time data for voice, audio and compressed video. As shown in Fig. 2, the external interfaces provided by this architecture are:

A number of ISDN interfaces such as the primary rate interface (PRI);

ISDN-oriented module 2 (IOM-2) system interface:, and pulse code modulation (PCM) system interface;

basic interfaces compatible with other networking tech- nologies such as 10MbiUs ethernet and USB; and

support interfaces such as the universal asynchronous receiver transmitter (UART), and the on-chip emulation module (OCEM). In this architecture there is a digital signal processing (DSP) core with a program and data sections. The DSP is the master of a common bus, which is connected a number of dedicated hardware functional blocks. These blocks imple- ment the necessary functions to connect external interfaces such as USB, ISDN or Ethernet. Also there is the rnicro- processor functional block that is responsible for the man- agement and the implementation of higher-layer protocol functions.

3 USB implementation study

The basic building blocks for implementing the USB device inside the COPARIS IC and the data flow from the USB line to the microprocessor are depicted in Fig. 3. lJnder traditional system Aconfiguration, the hardware functions are performed in&e following units:

Dlfferential transceiver; Drives the USB cable with data from the device and receives data ftom the USB cable.

Digital phase lock loop (DPLL) module: Perfomis the recovery of the encoded USB clock (in the USB protocol, the clock is transmitted encoded alon with the data). Thus it perfoms the separation of the d f tdclock information

Fig.2

208 LEE Proc.-Commun., Vol. 148, No. 4, August 2001

_I..__._.I__..__ .... ""-_ - ....,... - ....... _. ""_.__.._.I..____..... ~. * .

I C clock

FIFO I I , I I states identification ltrenSce'ver I '

i m i 1-1 . . Lx software i ; hardware

" ./ 'L ........................................................................ "_____*.i

Fig.3 us~dataflow

discard packet

Q r - 1 handshake CRC-16 identification

(3 0 Ono<:) discard packet

yes

pass data to up device

address number

____________ discard packet

endpoint number ACK decodlng

token identification

I

U Fig. 4 Flow chart for W i n g received USBpackets

and identification of USB standard messages such as the start of packet (SOP), endof packet (EOP), idle, reset and resume states of the USB dfferential line.

Serial interface ingine (SIE) module: Performs functions such as non return to zero inverted ("1) conversion, bit stuf'fingldestuffing and SYNC field identlfication. The software functions are implemented in the following units:

GHDLC module: Generic hgh-level data hnk control (GHDLC) performs the serial-to-parallel and parallel-to- serial conversion, data delineation, using the line control clock (LNCCLK) signal. The hardware modules of the USB device handles this signal in an asynchronous way, i.e. the decoding of a SYNC field starts 'cloclung' the

IEE Proc.-Commun., Vol. 148, No. 4, August 2001

GHDLC, while an EOP field deactivates the LNCCLK signal

DSP unit: Performs the remaining software functions to realise a USB device system. It forwards data to the micro- processor through mailbox communications, for upper- layer applications. The GHDLC unit contains a 32byte first-in-fht-out (FIFO) buffer for both transmit and receive directions. The data transfer between the GHDLC buffer and the DSP is interrupt driven. The GHDLC interrupts the DSP when the GHDLC reception buffer is full or the transmission buffer is empty.

Several functions can be performed either by software embedded in the DSP unit or by hardware added in the SIE block. Such functions include:

209

clock identification destuffing - enable

EOP

resume

reset c---

SE0 - Fig. 5 Mhimwn hurdvure upproueh (reception)

PID generation for transmission functions and checking and identification for the receive functions;

token packet decoding such as the identification of the device address and endpoint number; and

cyclic redundancy check (CRC) checking and generation such as calculations of CRC-5 and CRC-16. The flow chart depicted in Fig. 4 describes the procedure for handling a received packet. Within the COPARIS project a theoretical analysis has been conducted on the integration of the USB system components inside the COPARIS IC. The main objective is the optimum hard- ware-software functions partitioning, where several USB functions can be performed either by hardware or software as explained in the following subsections.

3. I Minimum hardware implementation In this approach all functions are implemented in software such as PID checlung and identification; processing CRC such as calculation and checking of CRC-S/CRC-16; token packet recognition and handshake packet control. As shown in Figs. 5 and 6, the hardware is kept to minimum, and the area estimation (gate level) for the SIE hardware needed for this approach is about 50 flip-flops (FF) and 110 gates. This solution is characterised by the hgh DSP power consumption. To estimate the required DSP power, the instructions needed for handling a packet were calcu- lated. The code used for MIPS (million instructions per sec- ond) estimation implements the functions except data transfer to the microprocessor. The code requires about 250 bytes of code memory.

Y a r B MUX bit H NRZl I data t

stuffing fn 4 m * y p

generation

Fig. 6 Minhwri luirdvure upprouch ( t rm iss ion)

Tables 1 and 2 present the software MIPS and hardware area estimations for a USB device in the DSP with full and low-speed data rates.

CRC-5

Table 1: DSP software MIPS consuming estimation

Data rate (Mbit/s) 12 1.5

MIPS estimation for minimum hardware approach 49.22 6.08

MIPS estimation for the balanced approach 14.20 1.93

Table 2 SIE hardware implementation area estimation

Hardware area estimation Flip-flops Gates

Minimum hardware approach 50 '110

Balanced software and hardware approach 80 .I 30

3.2 Balanced software and hardware implementation Based on the fact that the calculation of CRC-5 and CRC- 16 are the most power-consuming functions, the calcula- tions are implemented in hardware. Figs. 7 and 8 present the balanced approach in the reception and transnlission directions. The CRC-5 or CRC-16 machine is aciivated after the PID field (PID fields are not included in the CRC mechanism since they have their own checlung mecha- nism). If the least significant bit (LSB) of the PID is 1, no CRC is executed since the packet is a handshake packet. Otherwise, if the previous bit is 1, the CRC-5 machine is activated (SOF or token packet), otherwise the CRC-16 machine is activated (data packet). The calculated CRC reminder is passed to the received FIFO at the end of the packet (2 bytes). After packet identification in DSP, CRC-5 or CRC-16 checking is executed for token packets or data packets, respectively. Fig. 8 shows the implementation block diagram of the transmit direction.

The CRC check into the DSP is performed according to the USB specification [7]. If all token bits are received with- out error, the 5-bit residual at the receiver will be 01100 (CRC-5). If all data and CRC bits are received without error, then the 16-bit residual will be 1000000000001 101 (CRC-16). Thus the DSP compares the CRC reminder fed by hardware with a constant value. This alternative method to the one described in Section 3.1 is characterised by low DSP power consumption. The SIE hardware estimation for ths approach is about 80 FFs and 130 gates. The code

SYNC ident destuff bit ing H NRZI data clock -

n start . clock

SOP

EOP

resume

reset

SE0

- i enable ..................... ~ ........,.. " ........................... .....,.,,..

........ - - +------

+--

..

U

Fig. 7 Buluneed softwure and hurdvure upproneh (reeeption)

210 IEE Proc.-Curnmun., Vol. 148, Nu. 4, August 200I

data -

CRC-16

- MUX bit stuffing H NRZI SYNC generation

L CRC-5

Fig. 8 Buhced sofiwre and hurdwre approach ( trmisswn)

requires about 150 bytes of code memory, which is smaller Our study shows that performing all the functions in soft- than the minimum hardware approach (Section 3.1). ware is not optimal and may not meet the COPARIS sys-

Tables 1 and 2 present a comparison between the soft- tem requirements. The best solution is to implement CRC ware MIPS and hardware area estimations for both calculatiodchecking in hardware and this save about 65Yo approaches. It is clear that the balanced software and hard- of the DSP computation power. ware approach is the best solution. It reduces the DSP power requirements over the 65% in both data rates (12 5 Acknowledgments and 1.5MbiVs) compared with the fxst approach without inserting a large amount of hardware overhead.

4 Conclusion

This paper has proposed a new architectural approach for the next generation ISDN ICs (which may include USB interfaces) to offer programmability and hgh flexibility. The benefits of such an approach are mainly on the reduced IC production cost, the increased system integra- tion and the capability to provide customised solutions without the traditional high cost of ASIC redesign. The incorporation of a USB interface into the COPARIS IC architecture provides a number of additional capabilities such as port expansion, direct PC compatibility with ISDN applications and full support for the real-time data for voice and compressed video.

Two design approaches have been presented for imple- menting the USB functions in software or hardware such as PID checking and identification, calculation and check- ing of CRC, token packet recognition and handshake packet control. The calculations of CRC-5ICRC-16 are characterised by high computation power consumption.

The authors gratefully acknowledge the support from the European ESPRIT 25390 COPARIS project. The project includes the following partners: Siemens AG (project co- ordinator, Germany), Solinet Gmbh (Germany), Teletel S.A. (Greece), National Technical University of Athens (Greece) and University of Surrey (UK).

6 References

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CHOU, S., and LIN, Y.: ‘Computer telephony integration and its applications’, IEEE Commun. Surveys Tutorials, First quarter 2000, 3,

DHOOGE, H.: ‘The communicating PC‘, IEEE Commun. Mug., April 1996 RINDE, J.: ‘Telephony in the year 2005’, Comput. Netw., 1999, 31, (3) pp. 157-168 JAFF, K.A.: ‘Universal serial bus and the multimedia PC‘ 1996, http://developer.intel.com/design/CiSB/paperd USB Implementers Forum: http://usb.org/ DOUMENIS, G., KALOUDIS, V., and KARMAZIN, P.: ‘Next generation telecommunication processors for ISDNLAN applica- tions’. Presented at the EMMSEC‘98 conference, France, September 1998 USB specification 1.1, September 1998: http://www.usb.orgi ANDERSON, D.: ‘Universal senal bus system architecture’ (Mind- Share Inc., 1997) ISBN 0-201-46137-4 COPARIS web page: http://www.ee.surrey.ac.u!dCCSR/Espritl Coparid

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