1ESSDERC 2002 – Florence – 25.09.2002

Universal Test Structure andUniversal Test Structure andCharacterization Method for BiasCharacterization Method for Bias--Dependent Dependent

Drift Series Resistance of HV MOSFETsDrift Series Resistance of HV MOSFETs

C. Anghel1, N. Hefyene1, A.M. Ionescu1, R. Gillon2, S. Frere2, J. Rhayem2

1Institute of Microelectronics and Microsystems,Swiss Federal Institute of Technology Lausanne (EPFL)

2AMIS, Oudenaarde, Belgium

2ESSDERC 2002 – Florence – 25.09.2002

Outline:Outline:- Introduction- HV X-DMOS and Intrinsic Drain (Key) Voltage, VK:impact on modelling and electrical characterization

- New Test Structure and related DC characterization:MESDRIFT

- Experimental investigation of Rdrift with MESDRIFT- Physics and modelling of bias-dependent Rdrift

- HV DC model build-up with MESDRIFT- Extension for AC modelling- Conclusion

3ESSDERC 2002 – Florence – 25.09.2002

IntroductionIntroduction

Modelling Status: • Macro-models → good accuracy, but not physical ⇒ not able to take into account phenomena specific to the extended drain region: quasi-saturation • Compact models → time consuming for calibration and convergence

Interest HV Lateral MOSFETs: +Automotive RF

Hot Topics:• Develop fully-analytical DC/AC accurate models of the HV MOSFETs• Investigation of SOA & HC degradation

Modelling & Characterisation Possible Approach: • Investigate/access/model separately the intrinsic MOS channel region and the bias-dependent characteristics of the drift region

4ESSDERC 2002 – Florence – 25.09.2002

XDMOS Transistor Architecture and Intrinsic Drain Voltage, VXDMOS Transistor Architecture and Intrinsic Drain Voltage, VKK

0

1

2

3

4

5

6

7

0 20 40 60 80 100

VD (V)

ID(m

A)

VG=12V

10V

8V

6V

4V

2V3V

5V

7V

9V

11V

I

II

III

XDMOS – ID(VD) characteristics- I – intrinsic MOS channel pinch-off- II – quasi-saturation → channel pinch-off →

self-heating- III – quasi-saturation

VK allows: • distinguish between different saturation mechanisms → physical modeling!• investigation and modeling of the drift region: bias dependent resistance

Intrinsic MOS

Drain extension

Intrinsic MOS saturation

Self-heating

Quasi-saturation

5ESSDERC 2002 – Florence – 25.09.2002

MESDRIFT MESDRIFT –– a new test structurea new test structure

MESDRIFT:• small contact, same type as drift, close to the boundary MOSFET – drift zone• high impedance voltmeter used to monitor VK

• width of K contact negligible in comparison with W of global transistor → no influence on the global characteristics• physical dimensions of K contact → small shift in VK

MESDRIFT – XDMOS – cross-section

MESDRIFT – XDMOS – upper view

6ESSDERC 2002 – Florence – 25.09.2002

XDMOS vs. MESDRIFT XDMOS vs. MESDRIFT –– DC Characteristics:DC Characteristics:

ID – VG @ #VD

• very good match obtained for transfer characteristics• increased leakage currents observed in the sub-threshold regime due to the influence of the K contact near the metallurgical junction

• low VG: VDBR MESDRIFT < VDBR XDMOS (<5%)

ID – VD @ #VG

7ESSDERC 2002 – Florence – 25.09.2002

Experimental investigation of Experimental investigation of RRdriftdrift with MESDRIFT (1)with MESDRIFT (1)Rdrift extraction at low VD: intrinsic vs. extrinsic characteristics

Transfer Characteristics: Extrinsic/Intrinsic – using MESDRIFT – low VD Rdrift when VG due to:

• (acc.) channel formation in drift• slight reduction of depletion zones

( ) ( ) ( )gext G gint Gdrift G

ox 0

V VR V

(W / L)Cθ −θ

=µ

max int. max extr.

g int. g extr.

g > g < θ θ

( )( )

D m G Tg

G T

I / g V V 1V V

− − θ =−

8ESSDERC 2002 – Florence – 25.09.2002

Experimental investigation of Experimental investigation of RRdriftdrift with MESDRIFT (2)with MESDRIFT (2)VK measurements, @ different biasing conditions

0

5

10

15

0 5 10 15 20 25 30 35

VD (V)

VK (V

)

VG = 2V

3V

4V

5V

6V

12V

VK vs. VG with VD as parameter

0

4

8

12

16

20

1 2 3 4 5 6 7 8 9 10 11 12

VG(V)

VK(V

)

VD=30V

20V

10V

5V

2V

1V

VK vs. VD with VG as parameter

• VK slope-change – transition saturation – linear • VK VG (see explanation on next slide)• VK VD (expected)

9ESSDERC 2002 – Florence – 25.09.2002

Drift resistance variation function of biasing conditionsDrift resistance variation function of biasing conditions

Rdrift vs. VD with VG as parameter

100

1000

10000

100000

0 5 10 15 20 25 30

VD(V)

R drif

t, R c

h, (

k Ω)

VG=2V

4V, 6V, 8V, 10V and 12V

0.1

1.0

10.0

100.0

1000.0

10000.0

1 2 3 4 5 6 7 8 9 10 11 12

VG(V)

Rdr

ift, R

ch (k

Ω)

VD=30V

20V, 10V, 5V, 2V and 1V

Rdrift vs. VG with VD as parameter

• Extraction: straight-forward, no time consuming method• Rdrift Rch VG - drift influence dictates the overall behaviour at high VG

10ESSDERC 2002 – Florence – 25.09.2002

Drift resistance variation induced by accumulation/depletion in Drift resistance variation induced by accumulation/depletion in driftdrift

Depletion zones evolution VD= 20V, #VG Depletion zones evolution VG= 3V, #VD

#VG, VD=const• depletion depth induced by pin diode:slight reduction• channel modulation controlled by gate terminal in the drift zone (JFET effect)

#VD, VG=const• by increasing VD the accumulation channel in the drift pinches off → a depletion zone appears in the drift (JFET - like turn-off)

11ESSDERC 2002 – Florence – 25.09.2002

RRdriftdrift/R/Ronon in all XDMOS operation regimesin all XDMOS operation regimes Temperature influenceTemperature influence

0

25

50

75

100

0 2 4 6 8 10 12

VG(V)

Rdr

ift/(R

ch+R

drift

)(%)

VD=1V

VD=30V

T(°C)=25, 75, 125

0

20

40

60

80

100

0 5 10 15 20 25 30

V D(V)

Rdr

ift/(R

ch+R

drift

) (%

)

V G=1V

2V

3V

4V

12V

Rdrift/Ron vs. VD, #VG, at T=25°C(~ negligible self-heating)

Rdrift/Ron vs. VG, VD and T as parameters

• analogue operation regime → Ron dominated by Rch• medium, high voltage for VD or/and VG→ Ron dominated by Rdrift

• proper modelling of drift region is critical for accurate simulation at high voltages

12ESSDERC 2002 – Florence – 25.09.2002

HV DC model buildHV DC model build--up with MESDRIFTup with MESDRIFT

1. Low voltage MOS model calibrated on intrinsic transfer and output characteristics

2. Quasi-empirical expression tuned on Rdrift experimentally revealed by MESDRIFT

1000

10000

100000

0 10 20 30

VD (V)

Rdrif

t (Ω

)T = 25 C

75 C150 C

VG = 2V

VG = 4V

VG = 12V

o o o o o o o measures

_____ drift expression

( )[ ]1CVBexplnARR D0DD ++⋅+=*

* N. Hefyene, E. Vestiel , S. Frere, C. Anghel, A.M. Ionescu, R. Gillon, SISPAD 2002

Rdrift (VD), #VG and T, solid – quasi-empirical expression, dashed – MESDRIFT

13ESSDERC 2002 – Florence – 25.09.2002

Modelling HV XDMOS with MESDRIFT: transfer characteristicsModelling HV XDMOS with MESDRIFT: transfer characteristics

0.E+00

1.E-03

2.E-03

3.E-03

4.E-03

5.E-03

0 2 4 6 8 10 12 14

VG (V)

ID (A

)

VD = 20V

10V9V

2V

3V

4V

5V

6V7V

8V

1V

ID(VG) black – simulation, red – measurement

MAX. ERR. < 15%

1.E-13

1.E-11

1.E-09

1.E-07

1.E-05

1.E-03

0 2 4 6 8 10 12 14

VG (V)

Lo

g ID

(A

)

VD = 1 to 20V

log ID(VG) black – simulation, red – measurement

0.E+00

2.E-04

4.E-04

6.E-04

8.E-04

1.E-03

0 2 4 6 8 10 12 14

VG (V)

gm (S

)

VD = 20V

10V

1V

gm(VG) black – simulation, red – measurement

• medium and high voltage regimes →optimization using drift resistance parameters

14ESSDERC 2002 – Florence – 25.09.2002

Modelling HV XDMOS with MESDRIFT: output characteristicsModelling HV XDMOS with MESDRIFT: output characteristics

0

2

4

6

8

0 20 40 60 80

V D (V)

I D (m

A)

VG = 12V

VG = 6V

T = 25, 75 & 125°C

Quasi-saturation • good results obtained for overall characteristics including temperature dependence (max. err. < 20% and RMS < 5%)• saturation phenomena, including quasi-saturation well modelled with physical parameters• better results are expected when tuning the drift model on the pulsed measurements (without self-heating)

ID(VD) black – simulation, red – measurement

15ESSDERC 2002 – Florence – 25.09.2002

ConclusionConclusion• a new test structure, MESDRIFT, for characterisation of the drift zone of HV MOSFETs was designed and successfully validated based on the intrinsic drain voltage concept (VK)• for the first time, drift resistance variation for the entire voltage domain was revealed• temperature effects studied from 25°C up to 150°C• a simple VK - based modelling strategy using a low-voltage BSIM3v3transistor module and an empirical expression for drift resistance calibrated using MESDRIFT → validated for the whole operation range.

Acknowledgement• This work was supported by the IST-1999-12257 'Automacs' EC project and the Swiss OFES No. 00-0009• The authors acknowledge M. Vermandel and B. Bakeroot from ELIS TFCG/IMEC, University of Gent and P. Moens from AMIS, Belgium for TCAD simulations