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de Engenharia

Informatica

UNIVERSIDADE TECNICA DE LISBOA

INSTITUTO SUPERIOR TECNICO

Architectures for Embedded Computing

MEIC-A, MEIC-T, MERC

Lecture Slides

Version 3.0 - English

Lecture 20

Title: Digital Signal Processors (DSP)

Summary: Digital Signal Processors (DSP); Architectures (Example

2010/2011

[email protected]

Digital Signal Processors (DSP)

Prof. Nuno Roma ACE 2010/11 - DEI-IST 1 / 46

Architectures for EmbeddedComputing

Previous Class

Digital SignalProcessors (DSP)

Architectures

Example:TMS320C55 fromTexas Instruments

ParallelismExploitation (SIMD,VLIW)

Example:TMS320C6x fromTexas Instruments

DSP Market AndTheir Future


In the previous class...

� System Buses:

◮ Input / Output devices;

◮ Organization of the Input/Output system;

◮ Direct Memory Access (DMA).

Road Map


Architectures






Summary


Architectures






Today:

� Digital Signal Processors (DSP)

� Architectures

◮ Example: TMS320C55

� Parallelism exploitation (SIMD, VLIW)

◮ Example: TMS320C6x

� DSP market and their future

Bibliography:

• Computer Architecture: a Quantitative Approach, Appendix D

Digital Signal Processors (DSP)


Architectures






Introduction


Architectures






� The advantages offered by DSPs have allowed them to occupy agradually important space in the applications domain:

◮ Provide real-time analysis and manipulation of signalsacquired by sensors;

� Wide set of applications in the embedded systems domain:

◮ Digital photo/video cameras;

◮ Cellular phones;

◮ MP3 Players;

◮ Modems;

◮ Wireless devices;

◮ Geo-localization (GPS) devices;

◮ Set-top boxes (digital TV);

◮ Medical equipment;

◮ Musical equipment, etc.

Motivation


Architectures






� Their success is mainly owed to their great capacity toadapt to the applications and market requisites:

◮ Implementation of specific mathematical calculations;

◮ High performance;

◮ Small dimension;

◮ High power-saving capabilities;

◮ Low development and manufacture costs;

◮ Demanding time-to-market deadlines;

◮ etc.

Motivation


Architectures






� DSPs appeared in the 1970’s (XX century)

◮ Great investments in order to introduce Digital SignalProcessing in several areas;

� The significant cost of computers restricted the investmentto few key areas:

◮ The government and military needs leaded the firstinitiatives;

◮ Sonars and radars;

◮ Oil prospection;

◮ Space exploration;

◮ Medical imaging (X-ray computed tomography (CT),magnetic resonance imaging, etc.)

Motivation


Architectures






� With the advent of the personal computer, DSP weredisseminated in the market:

◮ 1980’s (XX century)

� Nowadays, they can be found everywhere:

◮ Scientific research, medicine, spatial exploration, army,marketing, industry, telecommunications, etc.

◮ Wide set of formats: cellular phones, MP3 players,digital cameras, etc.

DSP Characterization


Architectures






� Processor that was specifically conceived for signalprocessing in the digital domain;

◮ To fully understand what a DSP is and why it isdifferent from the remaining processors, it is firstnecessary to understand what Digital SignalProcessing means.

Video Audio Communications

Digital Signal Processing


Architectures






� Studies the signals and the required techniques to processthem in the digital domain;

� Usually, the signals are acquired with sensors, which collectinformation from the real world:

◮ Light waves;

◮ Sound waves;

◮ Electromagnetic fields;

◮ Seismic waves;

◮ Temperature, etc.



Architectures






� Signals are converted between the analog domain and thedigital domain by using signal converters:

◮ Analog-to-Digital Converter (ADC)

◮ Digital-to-Analog Converter (DAC)

� Many signal processing operations present strict latencyrestrictions, posing fixed limits in their maximum executiontime.



Architectures






� Digital Signal Processing is widely applied in a broadapplicational spectrum:



Architectures






� Most common signal processing algorithms:

◮ Time-domain filtering:

• Finite Impulse Response (FIR);

• Infinite Impulse Response (IIR);

◮ Convolution;

◮ Transforms:

• Fast Fourier Transform (FFT);

• Discrete Cosine Transform (DCT);

◮ Error detection and correction, in signal transmission;

◮ Control algorithms.



Architectures






� The mathematical calculations that result from the appliedtechniques may reach very high complex levels;

◮ The DSP should be able to satisfy the requiredcomputational resources;

◮ As a consequence, there isn’t one single “universal”DSP: a great variety of DSPs are available, targetingdifferent application domais;

� Restrictions concerning the energy consumption, requiredmemory space and manufacturing costs frequentlydetermine the specific type of DSP that should be adopted.



Architectures






� Most computational systems focus on two main domains:

◮ Data manipulation;

◮ Mathematical computation.

� It is not easy to design a processor that efficiently meetsboth domains:

◮ Technical compromises, high costs and marketingchallenges;

◮ Intel and AMD focused on processors oriented for datamanipulation;

◮ DSPs focused on specialized architectures targetingthe mathematical operations required for digital signalprocessing.



Architectures






� Most signal processing applications make use offixed-point arithmetic:

◮ The decimal separator (.) is assumed to be on theright of the sign bit;

◮ The represented values vary between -1 and 1;

◮ Each digit that is placed on the right of the decimalseparator at position i, is weighted as 2−i.

Examples:0100 0000 0000 0000 = 0.100 0000 0000 0000 = 2−1 = 0.5

0100 1000 0000 1000 = 0.100 1000 0000 1000 = 2−1+2−4+2−12 = 0.56274

1100 0000 0000 0000 = 1.100 0000 0000 0000 = (−1)× 2−1 = −0.5

� Applications with greater precision requisites usually adoptfloating-point arithmetic.

Architectures


Architectures








Architectures






� Main differences between a DSP and General PurposeProcessor (GPP):

◮ Instruction set

◮ Estimated execution time

� Instruction Set:

◮ GPPs are optimized for data transfer instructions(A←B) and conventional logic (IF A=B ...)

◮ DSPs are optimized for intensive mathematicalcomputations:

• Example: Multiply-and-ACcumulate (MAC) unit(A←A+B*C)



Architectures






Multiply-and-ACcumulate (MAC) unit

� Operation: A←A+B*C

� Synopsys:

MAC pma,dma - multiply/accumulate

P <- pma x dma

ACC <- ACC + P

(repeatable with pma+1)

� Applications:

◮ Digital filtering;

◮ Matrix operations;

◮ etc.



Architectures






Example:

Linear combination of vector elements:

Y =∑N

k=0 ck · x(k)

Prog. Mem Data Mem.

C0 X(0)C1 X(1)C2 X(2)· · ·CN X(N)

LARP AR3 ;AR3 active pointer

LAR AR3,#X0 ;point to X0

ZAP ;A=P=0

RPT #N

MAC C0,*+ ;sum of products

APAC ;final A=A+P

SACH Y ;save LSB



Architectures






� Estimated execution time:

◮ Not possible in General Purpose Processors (GPPs)!

◮ Mandatory in DSPs!

• Algorithm execution in real-time;

• Select the most appropriate DSP and algorithms.

� Real-time processing:

◮ A given code segment has a strict restriction in whatconcerns its execution time.

Architectures


Architectures






AT&T DSP32C

Architectures


Architectures






� Digital signal processing depends on very frequent accessesto memory:

◮ By operation: instruction, operands and coefficients

• The usage of the traditional Von Neumannarchitecture requires a minimum of 3 clock cyclesper operation⇒ Insufficient performance!!!

� DSPs adopt alternative architectures:

◮ Harvard architecture

◮ Super Harvard architecture

� Generalized use of Direct Memory Access (DMA)mechanisms.

Architectures


Architectures






� Von Neumann architecture

◮ Adopted by the majority of General PurposeProcessors (GPPs);

◮ One single memory is shared by instructions and data;

◮ The processor is interconnected by a data bus and anaddress bus;

◮ Memory accesses are serialized:

• instruction → operands → coefficients

◮ Minimum of 3 clock cycles!

Architectures


Architectures






� Harvard architecture

◮ Adopted by the majority of DSPs;

◮ Separated memories for data and instructions;

◮ Independent data and address buses for each memory;

◮ Data and instruction accesses are executed in parallel:

• instruction

• operands → coefficients

◮ Minimum of 2 clock cycles!

Architectures


Architectures






� Super Harvard architecture

◮ Adopted by the newest DSPs generations;◮ Additional instruction cache and I/O controller;◮ The I/O controller releases the DSP from data transfers

between the memory and the outside world;◮ Minimizes the existing asymmetries in instructions and data

accesses;◮ Exploits the repetitive characteristics of the algorithms:

• instruction / coefficients in cache

• operands

◮ Minimum of 1 clock cycle!

Example: TMS320C55 from TexasInstruments


Architectures






Example: TMS320C55 from Texas Instruments


Architectures






� Characteristics:

◮ 7 pipeline stages

◮ WAR and RAW hazard detection

◮ 24kB configurable instruction cache

• 2-ways set associativity• Direct mapping

◮ 2 MAC units:

• 17-bits multiplier• 40-bits accumulator

◮ Up to 900 MIPS

◮ Low power:

• 0.33mA/MHz• Some non-used units can beturned off



Architectures






� Architecture:



Architectures






� Data computation unit:



Architectures






� Applications:

Parallelism Exploitation (SIMD, VLIW)


Architectures






Parallelism Exploitation


Architectures






� Parallelism exploitation increases the processor performance:

◮ Allows the simultaneous execution of multiple units;

◮ General Purpose Processors (GPP) use super-scalararchitectures to achieve instruction level parallelism;

◮ The unpredictability and the impossibility to estimate theexecution time has led to a small penetration ofsuper-scalar architectures in DSP.

Main reasons:

• Dynamic branch prediction techniques;

• Dynamic scheduling;

• Variable cache access latencies.



Architectures






� Parallelism exploitation increases the processor performance:

◮ Allows the simultaneous execution of multiple units;

◮ General Purpose Processors (GPP) use super-scalararchitectures to achieve instruction level parallelism;

◮ The unpredictability and the impossibility to estimate theexecution time has led to a small penetration ofsuper-scalar architectures in DSP.

Main reasons:

• Dynamic branch prediction techniques;

• Dynamic scheduling;

• Variable cache access latencies.

� DSPs adopt alternative architectures:

◮ SIMD (Single Instruction Multiple Data) architecture

◮ VLIW (Very Long Instruction Word) architecture



Architectures






� SIMD architecture:

◮ Introduction of data-level parallelism;

◮ Each instruction may be executed over multipleoperands.

◮ Optimizes vectorial processing (e.g.: image processing);

◮ ISAs SIMD extensions: MMX, SSE1, SSE2, SSE3.



Architectures






� VLIW architecture:

◮ Delegates the instruction schedulingto the compiler;

◮ Each instruction encodes more thanone operation, where each opera-tion is implemented by a differentprocessing unit;

◮ The compiler defines the optimalorder!

◮ Removes the complexity (at execu-tion time) as well as the need forre-ordering.

Example: TMS320C6x from TexasInstruments


Architectures






Example: TMS320C6x from Texas Instruments


Architectures






� Characteristics:

◮ VLIW architecture, with 8 operations per instruction

◮ 11 pipeline stages (C64x family)

◮ Execution unit divided in two parts, each onecomposed by:

• L1/L2: logic and arithmetic operations• D1/D2: memory accesses• M1/M2: multiplications and shifts• S1/S2: branches and SIMD operations

◮ Each part has its own register bank(32 registers)

◮ Caches:

• 16kB L1 program (direct mapping)• 16kB L1 data (2-ways set associativity)• unified 256kB L2

◮ 8 operations executed in each clock cycle

◮ Compression in the encoding of each VLIW

◮ Up to 4000MIPS @ 500MHz



Architectures






� Architecture:



Architectures






� Data computation unit:



Architectures






� Applications:

DSP Market And Their Future


Architectures





Next Class




Architectures





Next Class


� DSPs market:

◮ Always expanding;

◮ Stimulated by an immense demand!

◮ As more and more DSP applications continue to beintroduced, the increase of the DSP market demand isexpected to continue over the next years.



Architectures





Next Class


� Wide range of offers and integration alternatives:

◮ To meet the market needs, which is often widelyheterogeneous;

◮ Alternatives:

• Core (only!)

• Processor (alone)

• Integrated solutions in a signal processing board

Core Processor Signal processing board

Next Class


Architectures





Next Class


Next Class


Architectures





Next Class


� Microcontrollers

� Smart-Cards

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