University Exam - VLSI Lab Record

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KAMBAN ENGINEERING COLLEGE TIRUVANNAMALAI

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

ENGINEERING

Certified that this is the Bonafide Record of work done by

Mr./Ms……………………………………………………. Reg.No:……………………

of Third Year B.E(Electronics and Communication Engineering) class

in the VLSI Design Laboratory during the year Dec 2010 – April 2011.

Staff Incharge Head of the Department.

External Examiner Internal Examiner.

Date………….2011

VLSI DESIGN LAB RECORD

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CONTENTS

Ex.No Date of Experiment Name of the Experiment Page

No. Remarks/ Initial

1. Schematic Entry of a CMOS Inverter.

2. Layout Design of a CMOS Inverter.

3. Schematic Entry of a MOS Differential Amplifier

4. AC Response of a MOS Differential Amplifier

5. Design of a 10 bit number controlled oscillator.

6. Digital Logic Gates Design using Verilog

7. COMBINATIONAL LOGIC CIRCUIT

DESIGN a) Half Adder and Full Adder

8. b) Half Subtractor and Full subtractor

9. c) Implementation of 2:4 Decoder and 4:2 Encoder

10. d) Implementation of 4:1 Multiplexer and 1:4 Demultiplexer.

11. SEQUENTIAL LOGIC CIRCUIT DESIGN. a)Flip Flops, PRBS Generator, Accumulators.

12. b) Implementation of Counters.

13. c) Implementation of Registers.

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Expt No: SCHEMATIC ENTRY OF A CMOS INVERTER Date:

AIM: To design a basic CMOS inverter using a schematic entry process for 130nm technology.

APPARATUS REQUIRED:

1. PC with Linux Ubuntu. 2. SlamPlus software. 3. Features of 130 nm and 45 nm channel width technology of in Layout and Schematic processes design.

PROCEDURE:

1. Create a folder Stabie in home folder.

2. Open a new terminal. Type ‘cd stabie’ and next line ‘slamPlus’

3. SlamPlus opens three windows a). Control window-slamplus,

b)Library browser window, c)Tkcon Window(Process console

Window).

4. In slamPlus window – create a library –using Admin tool.

5. ‘Create library box’ is opened.

6. Type Library Name: training

Library path: /home/kcclient1/stabie

Config file: t013m9.cfg

Select * add reference.

7. In slamPlus window – schematic – window – open.

8. ‘New cell window’ is opened.

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Library path : /home/kcclient1/stabie

Cell name: Inverter

View name: Sch

Select --- create.

10. New ‘training write window’ is opened.

11. Create – Instance.

12. ‘Create Instance window’ is opened.

13. Type Library name : schref:/opt/ssoft/example/sch.

Libray path : /opt/ssoft/example/sch.

Cell name : PMOS

W-0.50; L-0.15; M-1.

Click blank.

14. Drag and fit PMOS in write window.


16. Use same step for generating NMOS, by giving cell name as

NMOS.

17. Then Creating the connection as inverter as shown in below

diagram by select ‘j’.

Fig 1:- Schematic representation of a simple CMOS inverter.

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18. Select -Create – Pin in write window.

19. Create input and output pin by selecting direction and pin name

options as ‘in’ and ‘out’.

20. Create Vdd and Vss by direction as ‘inout’.

21. Extra – Distill schematic – ok.

22. Verifying if there any errors in Tkcon window.

23. Select – ARR - Run Simulation.

24. New simulation window is opened – Choose transients – then

write stimulus in blank space.

“ V1 vdd vss 1.8

V2 in vss pulse 0 1.8 2n 2n 2n 10n 20n

V3 Vss 0 0”

25. In stimulus 2n 2n 2n represents initial delay, rise time and fall time

respectively. 10n –hight time of single clock. 20n represents time

taken from one peak to another peak.

26. Click Run to check the corresponding Output Waveforms which

gets the output of CMOS inverter as shown in below diagram.

Fig 2:- Schematic Output of a simple CMOS inverter.

RESULT:

Thus schematic entry of CMOS inverter is designed and verified the

corresponding output waveforms by 130nm technology design.

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Expt No: LAYOUT DESIGN OF A CMOS INVERTER Date:

AIM: To design a basic CMOS inverter using Layout design process for 130nm technology. APPARATUS REQUIRED:


PROCEDURE:





Window).







7. In slamPlus window – Layout – window – open.

8. New ‘cell window’ is opened.



Cell name: Inverter

View name: ‘lay’

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Select --- create


11. Create – TLG (Tool command language Line Group).

12. ‘Create TLG window’ is opened.

13. Type Layer name : 1.

Proc name : Pmos_t013.

Length: 0.15

Width : 0.50

14. Drag and drop PMOS in top.

15. Create – TLG. Process name: Nmos_t013; L:0.15 and Width :

0.50.

16. Drag and drop NMOS in bottom as shown in below diagram.

Fig 1:- Layout representation of a simple CMOS inverter

17. Create - path. Layer name: Poly

Path width: 0.15. (to connect the NMOS and

PMOS as shown in lengthy green connection in above diagram).

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18. Create - path. Layer name: m1

Path width: 0.16. (to connect the NMOS and

PMOS as shown in lengthy Blue connection in above diagram)

19. Create - path. Layer name: m1

Path width: 0.5. (to draw vdd in above PMOS and

Vss in below NMOS)

20. Create – Via. ; Via name : ptap

Col : 3

21. Drag and drop it in NMOS Vss window.

22. Create – Via. ; Via name : ntap

Col : 3

23. Drag and drop it in PMOS Vdd window.

24. Create – Via.; Via name: pcon

Col : 1. Then click blank.

25. Drag and connect in the middle of the green lengthy connection

between NMOS and PMOS.

26. Create Text: Layer name: m1tx.

Mag : 0.1

vdd(intop), vss(inbottom), in(green connc), out(blue connection).

27. Verification – DRC – FDRC.

DRC: deck t013m9.rdvc

28. Verification Violation stepper is used for checking errors.




“ V1 vdd vss 1.8

V2 in vss pulse 0 1.8 2n 2n 2n 10n 20n

V3 Vss 0 0”.

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gets the output of CMOS inverter as shown in below diagram.

Fig 2:- Layout Output of a simple CMOS inverter.

---------

To get spice out netlist:

1. ARF- In simulation window – after writing stimulus – Run

spiceout.

2. Open New window – Cd stabie – ls. _ltr.

3. Gedit_spiceout<name>_inverter_inverter_lay.sp.

4. Netlist file is created in the new window.

RESULT:

Thus Layout entry of CMOS inverter is designed and verified the

corresponding output waveforms. Also its spice simution output for

130nm technology design.

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Expt No: SCHEMATIC ENTRY OF A DIFFERENTIAL AMPLIFIER Date:

AIM: To design a MOS Differential Amplifier using a schematic entry process for 130nm technology and Determination of gain, bandwidth, output impedance and CMRR.

APPARATUS REQUIRED:


PROCEDURE:





Window).









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Cell name: differential amplifier

View name: Sch

Select --- create.






Cell name : PMOS

W-4.00; L-1.00.

Click blank.




NMOS, W-8.00 and L- 0.5.



Fig 1:- Schematic representation of a Differential amplifier.

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18. Select -Create – Pin in ‘write window’.

19. Create input pin by selecting direction and pin name options as

‘vinn’, ‘vinp’ and ‘vb’.

20. Create output pin by selecting direction and pin name options as

‘vout’. Create Vdd and Vss by direction as ‘inout’.






“V1 Vdd 0 1.8

V2 Vb 0 0.65

V3 X 0 0.7

Vinp Vinp X SIN 100m 100m 5k -200u 0

Vinn Vinn 0 0”


gets the output of Diff amplifier as shown in below diagram.

Fig 2:- Schematic Output of a MOS Differential amplifier.

RESULT:

Thus schematic entry of MOS differential amplifier is designed and

verified the corresponding output waveforms for 130nm technology design.

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Expt No: AC RESPONSE OF A DIFFERENTIAL AMPLIFIER Date:

AIM: To design a MOS Differential Amplifier for AC response in a schematic entry process for 130nm technology and Determination of gain, bandwidth, output impedance and CMRR.

APPARATUS REQUIRED:


PROCEDURE:





Window).









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Cell name: differential amplifier

View name: Sch

Select --- create.






Cell name : PMOS

W-4.00; L-1.00.

Click blank.




NMOS, W-8.00 and L- 0.5.



Fig 1:- Schematic representation of a Differential amplifier.

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18. Select -Create – Pin in ‘write window’.

19. Create input pin by selecting direction and pin name options as

‘vinn’, ‘vinp’ and ‘vb’.

20. Create output pin by selecting direction and pin name options as

‘vout’.





25. New simulation window is opened.

Select –AC, then choose ‘Decimal’

Plot 1: db(v(Vout)/(v(Vinp)-v(Vinn))) vp(Vout)*180/3.142

then write stimulus in blank space.

“V1 Vdd 0 1.8

V2 Vb 0 0.65

V3 Vss 0 0

Vinp Vinp 0 DC 0.7 AC -0.5 0

Vinn Vinn 0 DC 0.7 AC 0.5 0”

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gets the output of AC response of MOS Diff amplifier as shown in

below diagram.

Fig 2:- Schematic Output of AC Response of MOS Differential amplifier.

RESULT:

Thus schematic entry of AC response of MOS differential amplifier is

designed and verified the corresponding output waveforms for 130nm

technology design.

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Expt No: DESIGN OF 10 BIT NUMBER CONTROLLED OSCILLATOR. Date:

AIM: To design a 10 bit number controlled oscillator using standard cell approach using a schematic entry process of 130nm technology.

APPARATUS REQUIRED:


PROCEDURE:





Window).









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Cell name: nco

View name: Sch

Select --- create.






Cell name : PMOS

W-0.50; L-0.15; M-1.

Click blank.




NMOS.



Fig 1:- Schematic representation of a 10 bit Number controlled oscillator.

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18. Select -Create – Pin in write window.

19. Create input and output pin by selecting direction and pin name

options as ‘in,d1,d2’ and ‘out’.




23. Symbol – generate symbol.

Cell name: <enter new name>.

View name: sym.

Pin style: square.

24. Windows – save.

25. SlamPlus – Schmatic – Window – Open.

Open ‘cell window’ is opened.

Cell name: NCO

View name: sch

Select – create. Then click ok.

26. Create Instance:

Library name: <….>

Library path: <….>

Cell name: NCO

View name: sym

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Fig 2. Symbol representation of a 10 bit number controlled

oscillator.




30. New simulation window is opened –Clik on Transient then Step

Value=0.01n Stop Value= 100n. Then write stimulus in blank

space.

“v1 VDD VSS 1.8 v2 VSS 0 0 v3 D1 0 1.8 v4 D2 0 0 v5 D3 0 1.8 v6 D4 0 0 v7 D5 0 1.8 v8 D6 0 0 v9 D7 0 1.8 v10 D8 0 0 v11 D9 0 1.8 v12 D10 0 0”

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gets the output of Number controlled oscillator as shown in below

diagram.

Fig 2:- Schematic Output of a 10 bit number controlled oscillator.

RESULT:

Thus schematic entry of 10 bit number controlled oscillator is designed

and verified the corresponding output waveforms by 130nm technology design.

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Expt.No: DIGITAL LOGIC GATES DESIGN USING VERILOG Date :

AIM:

To design and implement basic logic gates using Verilog Hardware Descriptive language.

APPARATUS REQUIRED:

1. PC with Windows XP. 2. XILINX, ModelSim software. 3. FPGA kit. 4. RS 232 cable.

PROCEDURE:

1. Select the new project

2. In project name field give your project name, select location.

3. The top level module select the verilog module and click the next

and finish the window.

4. Type the program and modulate the program.

5. Check the syntax and simulate the above verilog code (using

ModelSim or Xilinx) and verify the output waveform as obtained.

6. Implement the above code in Spartan III using FPGA kit.

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AND Gate:

PROGRAM: AND Gate: // Module Name: Andgate module Andgate(i1, i2, out); input i1; input i2; output out; and (out,i1,i2); endmodule Truth Table: AND Gate ------------------------------------------------ Input1 Input2 Output ------------------------------------------------ 0 0 0 0 1 0 1 0 0 1 1 1 ------------------------------------------------- Output waveform for AND gate:

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OR Gate:

PROGRAM: OR Gate: // Module Name: Orgate module Orgate(i1, i2, out); input i1; input i2; output out; or(out,i1,i2); endmodule Truth Table: OR Gate ------------------------------------------------ Input1 Input2 Output ------------------------------------------------ 0 0 0 0 1 1 1 0 1 1 1 1 ------------------------------------------------ Output Waveform for OR gate:-

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NAND Gate:

PROGRAM: NAND Gate: // Module Name: Nandgate module Nandgate(i1, i2, out); input i1; input i2; output out; nand(out,i1,i2); endmodule Truth Table: NAND Gate ------------------------------------------------ Input1 Input2 Output ------------------------------------------------ 0 0 1 0 1 1 1 0 1 1 1 0 ------------------------------------------------ Output Waveform for NAND gate:-

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NOR Gate:

PROGRAM: NOR Gate: // Module Name: Norgate module Norgate(i1, i2, out); input i1; input i2; output out; nor(out,i1,i2); endmodule Truth Table: NOR Gate ------------------------------------------------ Input1 Input2 Output ------------------------------------------------ 0 0 1 0 1 0 1 0 0 1 1 0 ------------------------------------------------ Output Waveform for NOR gate:-

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XOR Gate:

PROGRAM: XOR Gate: // Module Name: Xorgate module Xorgate(i1, i2, out); input i1; input i2; output out; xor(out,i1,i2); endmodule Truth Table:- XOR Gate ------------------------------------------------ Input1 Input2 Output ------------------------------------------------ 0 0 0 0 1 1 1 0 1 1 1 0 ------------------------------------------------- Output Waveform for XOR gate:

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XNOR Gate:

PROGRAM: XNOR Gate: // Module Name: Xnorgate module Xnorgate(i1, i2, out); input i1; input i2; output out; xnor(out,i1,i2); endmodule Truth Table: XNOR Gate ------------------------------------------------ Input1 Input2 Output ------------------------------------------------ 0 0 1 0 1 0 1 0 0 1 1 1 ------------------------------------------------ OutputWaveform for XNOR gate:-

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Not Gate:

PROGRAM: NOT Gate: // Module Name: Notgate module Notgate(in, out); input in; output out; not(out,in); endmodule Truth Table: NOT Gate --------------------------- Input Output --------------------------- 0 1 1 0 --------------------------- OutputWaveform for NOT gate:-

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Buffer:

PROGRAM: Buffer: // Module Name: Buffer module Buffer(in, out); input in; output out; buf(out,in); endmodule Truth Table: BUFFER --------------------------- Input Output --------------------------- 0 0 1 1 --------------------------- OutputWaveform for XNOR gate:-

RESULT: Thus the verilog program for the Logic Gates was simulated and output was verified.

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Expt. No: HALF ADDER AND FULL ADDER Date :

AIM:

To design and implement the combinational logic circuits of half adder and full adder using Verilog HDL. APPARATUS REQUIRED:


PROCEDURE:


2. In new project enter the project name and select location.







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Half Adder:

PROGRAM: HALF ADDER: // Module Name: HalfAddr module HalfAddr(sum, c_out, i1, i2); output sum; output c_out; input i1; input i2; xor(sum,i1,i2); and(c_out,i1,i2); endmodule Truth Table: Half Adder ------------------------------------------------------------------ Input1 Input2 Carry Sum ------------------------------------------------------------------ 0 0 0 0 0 1 0 1 1 0 0 1 1 1 1 0 ------------------------------------------------------------------ OutputWaveform for Half Adder:-

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Full Adder:

PROGRAM: FULL ADDER: // Module Name: FullAddr module FullAddr(i1, i2, c_in, c_out, sum); input i1; input i2; input c_in; output c_out; output sum; wire s1,c1,c2; xor n1(s1,i1,i2); and n2(c1,i1,i2); xor n3(sum,s1,c_in); and n4(c2,s1,c_in); or n5(c_out,c1,c2); endmodule Truth Table: Full Adder -------------------------------------------------------------------------------------------- i1 i2 C_in C_out Sum --------------------------------------------------------------------------------------------- 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 ----------------------------------------------------------------------------------------------

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OutputWaveform for Full Adder:-

RESULT:

Thus the verilog program for the Combinational Logic circuits of Half

adder and Full adder was simulated and output was verified

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Expt. No: HALF SUBTRACTOR & FULL SUBTRACTOR Date :

AIM:

To design and implement the combinational logic circuits of half subtractor and full subtractor using Verilog HDL. APPARATUS REQUIRED:


PROCEDURE:









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Half Subtractor:

PROGRAM: HALF SUBTRACTOR: // Module Name: HalfSub module HalfSub(i0, i1, bor, dif); input i0; input i1; output bor; output dif; wire i0n; not(i0n,i0); xor(dif,i0,i1); and(bor,i0n,i1); endmodule Truth Table: Half Subtractor ------------------------------------------------------------------------ Input1 Input2 Borrow Difference ------------------------------------------------------------------------- 0 0 0 0 0 1 1 1 1 0 0 1 1 1 0 0 ------------------------------------------------------------------------ OutputWaveform for Full Subtractor:-

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Full Subtractor:

PROGRAM: FULL SUBTRACTOR: // Module Name: FullSub module FullSub(b_in, i1, i0, b_out, dif); input b_in; input i1; input i0; output b_out; output dif; assign {b_out,dif}=i0-i1-b_in; endmodule Truth Table: Full Subtractor ------------------------------------------------------------------------------------------------ B_in I1 i0 B_out Difference ------------------------------------------------------------------------------------------------ 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 1 0 0 1 0 0 1 1 1 0 1 0 0 1 1 0 1 0 1 1 1 1 1 -------------------------------------------------------------------------------------------------

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OutputWaveform for Full Subtractor:-

RESULT:

Thus the verilog program for the Combinational Logic circuits of Half

Subtractor and Full Subtractor was simulated and output was verified.

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Expt No: IMPLEMENTATION OF 2 x 4 DECODER AND Date: 4 x 2 ENCODER

AIM:

To design and implement the combinational logic circuits of 2 x 4 Decoder and 4 x 2 Encoder Verilog HDL.

APPARATUS REQUIRED:


PROCEDURE:









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Encoder:

PROGRAM: ENCODER: // Module Name: Encd2to4 module Encd2to4(i0, i1, i2, i3, out0, out1); input i0; input i1; input i2; input i3; output out0; output out1; reg out0,out1; always@(i0,i1,i2,i3) case({i0,i1,i2,i3}) 4'b1000:{out0,out1}=2'b00; 4'b0100:{out0,out1}=2'b01; 4'b0010:{out0,out1}=2'b10; 4'b0001:{out0,out1}=2'b11; default: $display("Invalid"); endcase endmodule

Truth Table: 4to2 Encoder ------------------------------------- Input Output ------------------------------------- 1000 00 0100 01 0010 10 0001 11 ------------------------------------

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OutputWaveform for 4to2 Encoder:-

Decoder:

PROGRAM: Decoder: // Module Name: Decd2to4 module Decd2to4(i0, i1, out0, out1, out2, out3); input i0; input i1; output out0; output out1; output out2; output out3; reg out0,out1,out2,out3; always@(i0,i1) case({i0,i1}) 2'b00: {out0,out1,out2,out3}=4'b1000; 2'b01: {out0,out1,out2,out3}=4'b0100; 2'b10: {out0,out1,out2,out3}=4'b0010; 2'b11: {out0,out1,out2,out3}=4'b0001; default: $display("Invalid"); endcase endmodule

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Truth Table: 2to4 Decoder ------------------------------------- Input Output ------------------------------------- 00 1000 01 0100 10 0010 11 0001 ------------------------------------ OutputWaveform for 2to4 Decoder:-

RESULT:

Thus the verilog program for the Combinational Logic circuits of 2 x 4 Decoder and 4 x 2 Encoder was simulated and output was verified.

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Expt. No: IMPLEMENTATION OF 4:1 MULTIPLEXER & Date : 1:4DEMULTIPLEXER

AIM:

To design and implement the combinational logic circuits of 4:1 Multiplexer 1:4 Demultiplexer.

APPARATUS REQUIRED:


PROCEDURE:









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4:1 Multiplexer:

PROGRAM: MULTIPLEXER: // Module Name: Mux4to1 module Mux4to1(i0, i1, i2, i3, s0, s1, out); input i0; input i1; input i2; input i3; input s0; input s1; output out; wire s1n,s0n; wire y0,y1,y2,y3; not (s1n,s1); not (s0n,s0); and (y0,i0,s1n,s0n); and (y1,i1,s1n,s0); and (y2,i2,s1,s0n); and (y3,i3,s1,s0); or (out,y0,y1,y2,y3); endmodule

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Truth Table:

4to1 Multiplexer ----------------------------------------------- Input=1011 ----------------------------------------------- Selector Output ----------------------------------------------- {0,0} 1 {1,0} 0 {0,1} 1 {1,1} 1 ----------------------------------------------- OutputWaveform for 4to1 Multiplexer:-

Demultiplexer:

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PROGRAM: Demultiplexer: // Module Name: Dux1to4 module Dux1to4(in, s0, s1, out0, out1, out2, out3); input in; input s0; input s1; output out0; output out1; output out2; output out3; wire s0n,s1n; not(s0n,s0); not(s1n,s1); and (out0,in,s1n,s0n); and (out1,in,s1n,s0); and (out2,in,s1,s0n); and (out3,in,s1,s0); endmodule Truth Table: 1to4 Demultiplexer ----------------------------------------------- Input=1 ----------------------------------------------- Status Output ----------------------------------------------- {0,0} 1000 {0,1} 0100 {1,0} 0010 {1,1} 0001 ---------------------------------------------

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OutputWaveform for 1to4 Demultiplexer :-

RESULT:

Thus the verilog program for the Combinational Logic circuits 4:1 Multiplexer 1:4 Demultiplexer was simulated and output was verified.

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Expt.No: FLIP-FLOPS, PRBS GENERATORS, ACCUMULATORS. Date :

AIM: To design and implement the Sequential logic circuits of Flipflops, PRBS Generators, Accumulators using Verilog HDL.

APPARATUS REQUIRED:


PROCEDURE:









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Flip-Flop: D Flip-Flop:

PROGRAM: D FLIP-FLOP: // Module Name: DFF module DFF(Clock, Reset, d, q); input Clock; input Reset; input d; output q; reg q; always@(posedge Clock or negedge Reset) if (~Reset) q=1'b0; else q=d; endmodule

Truth Table: D FipFlop -------------------------------------------------------------------------- Clock Reset Input (d) Output q(~q) --------------------------------------------------------------------------- 0 0 0 0(1) 1 0 0 0(1) 0 0 1 0(1) 1 0 1 0(1) 0 0 0 0(1) 1 0 0 0(1) 0 1 1 0(1) 1 1 1 1(0) 0 1 0 1(0) 1 1 0 0(1) 0 1 1 0(1) 1 1 1 1(0) 0 0 0 0(1) 1 0 0 0(1) 0 0 0 0(1) --------------------------------------------------------------------------

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OutputWaveform for D Flip Flop:-

T Flip-Flop:

PROGRAM: T Flip-Flop: // Module Name: TFF module TFF(Clock, Reset, t, q); input Clock; input Reset; input t; output q; reg q; always@(posedge Clock , negedge Reset) if(~Reset) q=0; else if (t) q=~q; else q=q; endmodule

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Truth Table: T FipFlop --------------------------------------------------------------------------- Clock Reset Input (t) Output q(~q) --------------------------------------------------------------------------- 0 0 0 0(1) 1 0 0 0(1) 0 0 1 0(1) 1 0 1 0(1) 0 0 0 0(1) 1 0 0 0(1) 0 1 1 0(1) 1 1 1 1(0) 0 1 0 1(0) 1 1 0 1(0) 0 1 1 1(0) 1 1 1 0(1) 0 0 0 0(1) 1 0 0 0(1) 0 0 0 0(1) -------------------------------------------------------------------------- OutputWaveform for T- Flip Flop:-

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JK Flip-Flop:

Program: JK Flip-Flop: // Module Name: JKFF module JKFF(Clock, Reset, j, k, q); input Clock; input Reset; input j; input k; output q; reg q; always@(posedge Clock, negedge Reset) if(~Reset)q=0; else begin case({j,k}) 2'b00: q=q; 2'b01: q=0; 2'b10: q=1; 2'b11: q=~q; endcase end endmodule

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Truth Table: JK FipFlop -------------------------------------------------------------------------- Clock Reset Input (j,k) Output q(~q) -------------------------------------------------------------------------- 0 0 (0,0) 0(1) 1 0 (0,0) 0(1) 0 0 (0,1) 0(1) 1 0 (0,1) 0(1) 0 0 (1,0) 0(1) 1 0 (1,0) 0(1) 0 0 (1,1) 0(1) 1 0 (1,1) 0(1) 0 1 (0,0) 0(1) 1 1 (0,0) 0(1) 0 1 (0,1) 0(1) 1 1 (0,1) 0(1) 0 1 (1,0) 0(1) 1 1 (1,0) 1(0) 0 1 (1,1) 1(0) 1 1 (1,1) 0(1) 0 0 (0,0) 0(1) 1 0 (0,0) 0(1) 0 0 (0,0) 0(1) ------------------------------------------------------------------------- OutputWaveform for JK- Flip Flop:-

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PRBS generators

module lfsr(input clk,reset,en,output reg[7:0] q); always@(posedge clk or posedge reset) begin if (reset) q<=8’d1;//can be anything except zero else if(en) q<={q[6:0],q[7]^ q[5]^ q[4]^ q[3]}; // polynomial for maximal LFSR end endmodule;

Accumulator

module accum (C, CLR, D, Q); input C, CLR; input [3:0] D; output [3:0] Q; reg [3:0] tmp; always @(posedge C or posedge CLR) begin if (CLR) tmp = 4'b0000; else tmp = tmp + D; end assign Q = tmp; endmodule

RESULT:

Thus the verilog program for the Sequential Logic circuits of Flipflops, PRBS Generators, Accumulators was simulated and output was verified.

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Expt No: IMPLEMENTATION OF COUNTERS

Date:

AIM: To design and implement the Sequential logic circuits of 2- Bit Counter using Verilog HDL.

APPARATUS REQUIRED:


PROCEDURE:









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2- Bit Counter::

PROGRAM: 2- BIT COUNTER: // Module Name: Count2Bit module Count2Bit(Clock, Clear, out); input Clock; input Clear; output [1:0] out; reg [1:0]out; always@(posedge Clock, negedge Clear) if((~Clear) || (out>=4))out=2'b00; else out=out+1; endmodule OutputWaveform for 2 Bit Counter:-

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Truth Table: 2 Bit Counter --------------------------------------------------- Clock Clear Output[2] --------------------------------------------------- 0 0 00 1 0 00 0 0 00 1 0 00 0 0 00 1 0 00 0 0 00 1 0 00 0 0 00 1 0 00 0 1 00 1 1 01 0 1 01 1 1 10 0 1 10 1 1 11 0 1 11 1 1 00 0 1 00 1 1 01 0 1 01 1 1 10 0 1 10 1 1 11 0 1 11 1 1 00 0 0 00 1 0 00 ------------------------------------------------ RESULT:

Thus the verilog program for the Sequential Logic circuits of 2- Bit Counter was simulated and output was verified.

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Expt No: IMPLEMENTATION OF REGISTERS Date:

AIM: To design and implement the Sequential logic circuits of 2- Bit Registers using Verilog HDL.

APPARATUS REQUIRED:


PROCEDURE:









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Register:

Truth Table: 2 Bit Register ----------------------------------------------------------------------- Clock Clear Input[2] Output[2] ----------------------------------------------------------------------- 0 0 00 00 1 0 00 00 0 0 01 00 1 0 01 00 0 0 10 00 1 0 10 00 0 0 11 00 1 0 11 00 0 1 00 00 1 1 00 00 0 1 01 00 1 1 01 01 0 1 10 01 1 1 10 10 0 1 11 10 1 1 11 11 0 0 11 00 1 0 11 00 0 0 11 00 -------------------------------------------------------------------- PROGRAM: 2 – Bit Register: // Module Name: Reg2Bit module Reg2Bit(Clock, Clear, in, out); input Clock; input Clear; input [0:1] in; output [0:1] out; reg [0:1] out; always@(posedge Clock, negedge Clear) if(~Clear) out=2'b00; else out=in; endmodule

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OutputWaveform for 2 – Bit Register:-

RESULT:

Thus the verilog program for the Sequential Logic circuits of 2- Bit Registers was simulated and output was verified.

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Processing steps in XILINX Step 1: Open Xilinx software Step 2: Select File à New Project.

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Step 3: In the New Project window enter project name and project location.

Step 4: Select the corresponding entries for the property names.

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Step 5: Click New Source.

Step 6: Enter the file name and then select Verilog module.

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Step 7: Define the input and output port names ,then click Next for all successive windows.

Step 8: The Verilog file will be created under .ise file.

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Step 9: Double click the Verilog file and enter the logic details and save the file.

Step 10: Double click Synthesize – XST for checking the syntax .

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Step 11: Right click the halfadd.v file and select new source ,then click Implementation Constraints File and enter the filename.

Step 12:.ucf file will be created .

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Step13: Open the .ucf file and enter the pin location and save the file

Step14: Goto Generate programming file and select Generate PROM,ACE or JTAG file in the processes Swindow.

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Step 15: In Slave Serial mode ,right click and select Add Xilinx Device.

Step 16: In the Add Device window select the .bit file to add the device.

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Step 17: Connect the RS232 cable between computer and kit. Connect the SMPS to kit and switch on the kit. Step 18: Right click the device and select Program to transfer the file to kit.

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Step 19: After successful transmission of file “Programming Succeeded” will be displayed.

********* All the best

by M.Devanathan. Lect-ECE

Kamban Engineering College

Date post:	21-Apr-2015
Category:	Documents
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University Exam - VLSI Lab Record

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