Guidelines for Poster Presentation 1m 0.8m X Space is limited! X Must be clear, concise, and easy to read. X Should include some background material (e.g. current standards), objectives (e.g. specifications) and challenges (e.g. technical limitations) X Present only the high-lights of important results and accomplishments of your project. X Target audience: 3 rd and 4 th year students, professors, industry representatives, and ECE496 administrators X Make good use of diagrams and drawings (a picture worth more than a thousand words). X No place for complete program codes and derivations. Project ID, Title, names of students, supervisor and administrator, section number
Transcript
Guidelines for Poster Presentation
1m
0.8m
Space is limited!Must be clear, concise, and easy to read.Should include some background material (e.g. current standards), objectives (e.g. specifications) and challenges (e.g. technical limitations)Present only the high-lights of important results and accomplishments of your project.Target audience: 3rd and 4th year students, professors, industry representatives, and ECE496 administratorsMake good use of diagrams and drawings (a picture worth more than a thousand words).No place for complete program codes and derivations.
Project ID, Title, names of students, supervisor and administrator, section number
Guidelines for Poster Presentation
Doping Conc. at Emitter
1.0E+15
1.0E+16
1.0E+17
1.0E+18
1.0E+19
1.0E+20
1.0E+21
0 0.2 0.4 0.6 0.8 1
DEPTH (µm)
Car
rier C
onc.
(cm
3 )
AKM
TS4
Emitter
Emitter
Deep NWell
Base
Poly
Simulation Results Conclusions & Future WorkDevice Layout, emitter finger length and width optimizationComplete electrical performance simulation of the vertical npn transistor using TSUPREM and MEDICIFinalize process recipes forn+ buried layern-epitaxial layerp-base diffusionn+ sinker diffusion
8½”
11”
Vertical BJT StructureTrench IsolationMore complicated process changesReduced parasitic capacitance
Need new shallow p-base, trench etch and poly refill recipesNeed new mask for n+ poly-emitterOptimum characteristics
p-substrate
CE B
n-sinkn+
n-epi
n+ buried layer
RC1 RC3
B
TepiCCB
CCS
RC2
p+p+SiO2 p-base
SiO2SiO2
poly-filled
n+
poly-filled
… … … …6-bi
t add
ress
dec
oderA0
A1A2A3A4A5
…
Word 0
Word 1
Word 2
Word 63
Input DataBuffer Write
Enable
SenseAmplifiers
OutputData Buffers
4 64SRAM Array
A3 A2 A1 A0
B3 B2 B1 B0
…
Internal organizationof a
4 64 SRAM array
about 6 pages
Amplifier Frequency ResponseAssuming that rds2 rds,p, gm2 gm,p
Therefore, ys2 becomes
2
2, ,
1 1 dsL
L mm p ds p
gGR gg r
22
2
1
1m
s dsdss
ds m
gy ggrg g
if gm/gds >> 1
The impedance Rd1 thus can be expressed as
1 1 2// //2ds
d ds s ds dsrR r r r r
1m
0.8m
Example 1 : Poster made up of separate sheets
Project ID, Title, names of students, supervisor and administrator, section number
Project Title
1m
IntroductionField programmable capability to wireless portable telecommunication equipment
True 5V or lower operationCompatible with CMOS/BiCMOSprocessesHigh operation speeds and high densityKey to embedded systemsSolid-state nonvolatile memoriesMulti-level Encoding
Design ChallengesMost require high drain bias voltage (VD > 5V) to generate hot electrons for programming. Not directly scalable to shorter channel length. Not suitable for low voltage applications.Require high drain current (IDS @ 1mA) during programming. Require large charge pump circuits and limits the number of cells that can be programmed at once.Suffers from slow programming speed (a few µs). Not suitable to replace RAM and electronic hard drives.
n+n+
p+p-substrate
n+n+
p+p-substrate n+ n+
p+p-substrate
Programming (Program Section)
Reading (Sense Section)
Erasing (Entire Width)
VCG = 12VVD 3.3V
VS = 0V
VCG = 3.3V
VD = 1V
VS = 0VVS = 3.3V
VCG = -12V
Time (s)
Th
res
ho
ld V
olt
ag
e (
V)
Erase Time
VT Programmed
VT Erased
L = 0.8µm
-12V
3.3V floating
Results & Conclusions
0.8m
Design for low voltage applications —eliminate the voltages applied to the source and drain to be below the 5V or 3.3V supplyImprove the performance — more specifically the programming and erasing speed need to be increaseCompatible to existing CMOS/BiCMOS— simple cell construction and reduce cost, ensure the viability for low cost single chip embedded systems.
Example 2: An integrated poster
Project ID, names of students, supervisor and administrator, section number
