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Document No. U18598EJ1V0UD00 (1st edition)

Date Published January 2008 NS

Printed in Japan2008

78K0/KB2: PD78F0500A, 78F0501A, 78F0502A, 78F0503A, 78F0503DA,

78F0500A(A), 78F0501A(A), 78F0502A(A), 78F0503A(A)

78K0/KC2: PD78F0511A, 78F0512A, 78F0513A, 78F0514A, 78F0515A, 78F0513DA, 78F0515DA,

78F0511A(A), 78F0512A(A), 78F0513A(A), 78F0514A(A), 78F0515A(A)

78K0/KD2: PD78F0521A, 78F0522A, 78F0523A, 78F0524A, 78F0525A, 78F0526A, 78F0527A, 78F0527DA,78F0521A(A), 78F0522A(A), 78F0523A(A), 78F0524A(A), 78F0525A(A), 78F0526A(A), 78F0527A(A)

78K0/KE2: PD78F0531A, 78F0532A, 78F0533A, 78F0534A, 78F0535A, 78F0536A, 78F0537A, 78F0537DA,

78F0531A(A), 78F0532A(A), 78F0533A(A), 78F0534A(A), 78F0535A(A), 78F0536A(A), 78F0537A(A)

78K0/KF2: PD78F0544A, 78F0545A, 78F0546A, 78F0547A, 78F0547DA,

78F0544A(A), 78F0545A(A), 78F0546A(A), 78F0547A(A)

78K0/Kx2

8-Bit Single-Chip Microcontrollers

Users Manual

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Users Manual U18598EJ1V0UD2

[MEMO]

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Users Manual U18598EJ1V0UD 3

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VOLTAGE APPLICATION WAVEFORM AT INPUT PIN

Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the

CMOS device stays in the area between VIL(MAX) and VIH(MIN) due to noise, etc., the device may

malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,

and also in the transition period when the input level passes through the area between VIL(MAX) and

VIH(MIN).

HANDLING OF UNUSED INPUT PINS

Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is

possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS

devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed

high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDDor GND

via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must

be judged separately for each device and according to related specifications governing the device.

PRECAUTION AGAINST ESD

A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide andultimately degrade the device operation. Steps must be taken to stop generation of static electricity as

much as possible, and quickly dissipate it when it has occurred. Environmental control must be

adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that

easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static

container, static shielding bag or conductive material. All test and measurement tools including work

benches and floors should be grounded. The operator should be grounded using a wrist strap.

Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for

PW boards with mounted semiconductor devices.

STATUS BEFORE INITIALIZATION

Power-on does not necessarily define the initial status of a MOS device. Immediately after the power

source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does

not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the

reset signal is received. A reset operation must be executed immediately after power-on for devices

with reset functions.

POWER ON/OFF SEQUENCE

In the case of a device that uses different power supplies for the internal operation and external

interface, as a rule, switch on the external power supply after switching on the internal power supply.

When switching the power supply off, as a rule, switch off the external power supply and then the

internal power supply. Use of the reverse power on/off sequences may result in the application of an

overvoltage to the internal elements of the device, causing malfunction and degradation of internal

elements due to the passage of an abnormal current.

The correct power on/off sequence must be judged separately for each device and according to related

specifications governing the device.

INPUT OF SIGNAL DURING POWER OFF STATE

Do not input signals or an I/O pull-up power supply while the device is not powered. The current

injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and

the abnormal current that passes in the device at this time may cause degradation of internal elements.

Input of signals during the power off state must be judged separately for each device and according to

related specifications governing the device.

NOTES FOR CMOS DEVICES

5

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EEPROM is a trademark of NEC Electronics Corporation.

Windows and Windows NT are registered trademarks or trademarks of Microsoft Corporation in the United

States and/or other countries.

PC/AT is a trademark of International Business Machines Corporation.

HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.

SPARCstation is a trademark of SPARC International, Inc.

Solaris and SunOS are trademarks of Sun Microsystems, Inc.

SuperFlashis a registered trademark of Silicon Storage Technology, Inc. in several countries including the

United States and Japan.

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Caution: This product uses SuperFlashtechnology licensed from Silicon Storage Technology, Inc.

The information in this document is current as of January, 2008. The information is subject to

change without notice. For actual design-in, refer to the latest publications of NEC Electronics data

sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not

all products and/or types are available in every country. Please check with an NEC Electronics sales

representative for availability and additional information.

No part of this document may be copied or reproduced in any form or by any means without the prior

written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may

appear in this document.

NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual

property rights of third parties by or arising from the use of NEC Electronics products listed in this document

or any other liability arising from the use of such products. No license, express, implied or otherwise, isgranted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.

Descriptions of circuits, software and other related information in this document are provided for illustrative

purposes in semiconductor product operation and application examples. The incorporation of these

circuits, software and information in the design of a customer's equipment shall be done under the full

responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by

customers or third parties arising from the use of these circuits, software and information.

While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,

customers agree and acknowledge that the possibil ity of defects thereof cannot be eliminated entirely. To

minimize risks of damage to property or injury (including death) to persons arising from defects in NEC

Electronics products, customers must incorporate sufficient safety measures in their design, such as

redundancy, fire-containment and anti-failure features.

NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and

"Specific".

The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-

designated "quality assurance program" for a specific application. The recommended applications of an NEC

Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of

each NEC Electronics product before using it in a particular application.

The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NECElectronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications

not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to

determine NEC Electronics' willingness to support a given application.

(Note)

M8E 02. 11-1

(1)

(2)

"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its

majority-owned subsidiaries.

"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as

defined above).

Computers, office equipment, communications equipment, test and measurement equipment, audio

and visual equipment, home electronic appliances, machine tools, personal electronic equipment

and industrial robots.

Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed

for life support).

Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems and medical equipment for life support, etc.

"Standard":

"Special":

"Specific":

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INTRODUCTION

Readers This manual is intended for user engineers who wish to understand the functions of the

expanded-specification products (PD78F05xxA) of the 78K0/Kx2 microcontrollers and

design and develop application systems and programs for these devices.

The target products are as follows.

Expanded-specification products of the 78K0/KB2 (PD78F050xA):

PD78F0500A, 78F0501A, 78F0502A, 78F0503A, 78F0503DA, 78F0500A(A),

78F0501A(A), 78F0502A(A), 78F0503A(A)

Expanded-specification products of the 78K0/KC2 (PD78F051xA):

PD78F0511A, 78F0512A, 78F0513A, 78F0514A, 78F0515A, 78F0513DA,

78F0515DA, 78F0511A(A), 78F0512A(A), 78F0513A(A), 78F0514A(A),

78F0515A(A)

Expanded-specification products of the 78K0/KD2 (PD78F052xA):

PD78F0521A, 78F0522A, 78F0523A, 78F0524A, 78F0525A, 78F0526A,

78F0527A, 78F0527DA, 78F0521A(A), 78F0522A(A), 78F0523A(A), 78F0524A(A),78F0525A(A), 78F0526A(A), 78F0527A(A)

Expanded-specification products of the 78K0/KE2 (PD78F053xA):

PD78F0531A, 78F0532A, 78F0533A, 78F0534A, 78F0535A, 78F0536A,

78F0537A, 78F0537DA, 78F0531A(A), 78F0532A(A), 78F0533A(A), 78F0534A(A),

78F0535A(A), 78F0536A(A), 78F0537A(A)

Expanded-specification products of the 78K0/KF2 (PD78F054xA):

PD78F0544A, 78F0545A, 78F0546A, 78F0547A, 78F0547DA, 78F0544A(A),

78F0545A(A), 78F0546A(A), 78F0547A(A)

For the conventional-specification products of the 78K0/Kx2 microcontrollers

(PD78F05xx), see the following manuals.

Document Name Document No.

78K0/KB2 Users Manual U17328E

78K0/KC2 Users Manual U17336E

78K0/KD2 Users Manual U17312E

78K0/KE2 Users Manual U17260E

78K0/KF2 Users Manual U17397E

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Purpose This manual is intended to give users an understanding of the functions described in the

Organizationbelow.

Organization The manual for the expanded-specification products of 78K0/Kx2 microcontrollers is

separated into two parts: this manual and the instructions edition (common to the 78K0

microcontrollers).

78K0/Kx2

Users Manual

(This Manual)

78K/0 Series

Users Manual

Instructions

Pin functions

Internal block functions

Interrupts

Other on-chip peripheral functions

Electrical specifications

CPU functions

Instruction set

Explanation of each instruction

How to Read This Manual It is assumed that the readers of this manual have general knowledge of electricalengineering, logic circuits, and microcontrollers.

When using this manual as the manual for (A) grade products of the expanded-

specification products of 78K0/Kx2 microcontrollers:

Only the quality grade differs between standard products and (A) grade products.

Read the part number as follows.

PD78F050yAPD78F050yA(A) (y = 0 to 3)

PD78F051yAPD78F051yA(A) (y = 1 to 5)

PD78F052yAPD78F052yA(A) (y = 1 to 7)

PD78F053yAPD78F053yA(A) (y = 1 to 7)

PD78F054yAPD78F054yA(A) (y = 4 to 7)

To gain a general understanding of functions:

Read this manual in the order of the CONTENTS.

How to interpret the register format:

For a bit number enclosed in angle brackets, the bit name is defined as a

reserved word in the RA78K0, and is defined as an sfr variable using the

#pragma sfr directive in the CC78K0.

To check the details of a register when you know the register name:

See APPENDIX C REGISTER INDEX.

To know details of the 78K0 microcontroller instructions:

Refer to the separate document 78K/0 Series Instructions Users Manual

(U12326E).

Conventions Data significance: Higher digits on the left and lower digits on the right

Active low representations: (overscore over pin and signal name)

Note: Footnote for item marked with Notein the text

Caution: Information requiring particular attention

Remark: Supplementary information

Numerical representations: Binary ...or B

Decimal ...

Hexadecimal ...H

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Related Documents The related documents indicated in this publication may include preliminary versions.

However, preliminary versions are not marked as such.

Documents Related to Devices


78K0/Kx2 Users Manual This manual

78K/0 Series Instructions Users Manual U12326E

78K0/Kx2 Flash Memory Programming (Programmer) Application Note U17739E

78K0 Microcontrollers Self Programming Library Type01 Users ManualNote

U18274E

78K0 Microcontrollers EEPROMTM

Emulation Library Type01 Users ManualNote

U18275E

Note This document is under engineering management. For details, consult an NEC Electronics sales representative.

Documents Related to Development Tools (Software) (Users Manuals)


Operation U17199E

Language U17198E

RA78K0 Ver. 3.80 Assembler Package

Structured Assembly Language U17197E

Operation U17201ECC78K0 Ver. 3.70 C Compiler

Language U17200E

Operation U17246ESM+ System Simulator

User Open Interface U17247E

ID78K0-QB Ver. 2.90 Integrated Debugger Operation U17437E

PM+ Ver. 6.00 U17178E

Documents Related to Development Tools (Hardware) (Users Manuals)


QB-78K0KX2 In-Circuit Emulator U17341E

QB-78K0MINI On-Chip Debug Emulator U17029E

QB-MINI2 On-Chip Debug Emulator with Programming Function U18371E

Documents Related to Flash Memory Programming


PG-FP5 Flash Memory Programmer Users Manual U18865E

PG-FP4 Flash Memory Programmer Users Manual U15260E

PG-FPL3 Flash Memory Programmer Users Manual U17454E

Caution The related documents listed above are subject to change without notice. Be sure to use the latest

version of each document when designing.

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Other Documents


SEMICONDUCTOR SELECTION GUIDE Products and Packages X13769X

Semiconductor Device Mount Manual Note

Quality Grades on NEC Semiconductor Devices C11531E

NEC Semiconductor Device Reliability/Quality Control System C10983E

Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E

Note See the Semiconductor Device Mount Manual website (http://www.necel.com/pkg/en/mount/index.html).

Caution The related documents listed above are subject to change without notice. Be sure to use the latest

version of each document when designing.

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CONTENTS

CHAPTER 1 OUTLINE ............................................................................................................................ 19

1.1 Differences Between Conventional-specification Products (PD78F05xx) and

Expanded-specification Products (PD78F05xxA)................................................................... 19

1.1.1 Number of flash memory rewrites and retention time of standard products and (A) grade products .... 19

1.1.2 Processing time for self programming library .................................................................................. 20

1.1.3 Interrupt response time for self programming library....................................................................... 26

1.1.4 A/D conversion time........................................................................................................................ 29

1.2 Features......................................................................................................................................... 30

1.3 Applications.................................................................................................................................. 31

1.4 Ordering Information.................................................................................................................... 32

1.5 Pin Configuration (Top View)...................................................................................................... 35

1.5.1 78K0/KB2........................................................................................................................................ 35

1.5.2 78K0/KC2........................................................................................................................................ 37

1.5.3 78K0/KD2........................................................................................................................................ 40

1.5.4 78K0/KE2........................................................................................................................................ 41

1.5.5 78K0/KF2........................................................................................................................................ 43

1.6 Pin Identification........................................................................................................................... 44

1.7 Block Diagram .............................................................................................................................. 45

1.7.1 78K0/KB2........................................................................................................................................ 45

1.7.2 78K0/KC2........................................................................................................................................ 46

1.7.3 78K0/KD2........................................................................................................................................ 47

1.7.4 78K0/KE2........................................................................................................................................ 48

1.7.5 78K0/KF2........................................................................................................................................ 49

1.8 Outline of Functions..................................................................................................................... 50

CHAPTER 2 PIN FUNCTIONS............................................................................................................... 53

2.1 Pin Function List .......................................................................................................................... 53

2.1.1 78K0/KB2........................................................................................................................................ 54

2.1.2 78K0/KC2........................................................................................................................................ 57

2.1.3 78K0/KD2........................................................................................................................................ 60

2.1.4 78K0/KE2........................................................................................................................................ 63

2.1.5 78K0/KF2........................................................................................................................................ 67

2.2 Description of Pin Functions ...................................................................................................... 71

2.2.1 P00 to P06 (port 0).......................................................................................................................... 71

2.2.2 P10 to P17 (port 1).......................................................................................................................... 72

2.2.3 P20 to P27 (port 2).......................................................................................................................... 73

2.2.4 P30 to P33 (port 3).......................................................................................................................... 74

2.2.5 P40 to P47 (port 4).......................................................................................................................... 75

2.2.6 P50 to P57 (port 5).......................................................................................................................... 76

2.2.7 P60 to P67 (port 6).......................................................................................................................... 76

2.2.8 P70 to P77 (port 7).......................................................................................................................... 77

2.2.9 P120 to P124 (port 12).................................................................................................................... 78

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2.2.10 P130 (port 13)................................................................................................................................79

2.2.11 P140 to P145 (port 14)...................................................................................................................80

2.2.12 AVREF, AVSS, VDD, EVDD, VSS, EVSS................................................................................................81

2.2.13 RESET...........................................................................................................................................82

2.2.14 REGC ............................................................................................................................................82

2.2.15 FLMD0...........................................................................................................................................82

2.3 Pin I/O Circuits and Recommended Connection of Unused Pins........................................... 83

CHAPTER 3 CPU ARCHITECTURE...................................................................................................... 88

3.1 Memory Space.............................................................................................................................. 88

3.1.1 Internal program memory space ....................................................................................................103

3.1.2 Memory bank (PD78F05x6A, 78F05x7A, and 78F05x7DA (x = 2 to 4) only) ...............................105

3.1.3 Internal data memory space ..........................................................................................................106

3.1.4 Special function register (SFR) area ..............................................................................................107

3.1.5 Data memory addressing...............................................................................................................107

3.2 Processor Registers .................................................................................................................. 116

3.2.1 Control registers.............................................................................................................................116

3.2.2 General-purpose registers .............................................................................................................120

3.2.3 Special function registers (SFRs)...................................................................................................121

3.3 Instruction Address Addressing .............................................................................................. 127

3.3.1 Relative addressing .......................................................................................................................127

3.3.2 Immediate addressing....................................................................................................................128

3.3.3 Table indirect addressing...............................................................................................................129

3.3.4 Register addressing .......................................................................................................................130

3.4 Operand Address Addressing.................................................................................................. 130

3.4.1 Implied addressing.........................................................................................................................130

3.4.2 Register addressing .......................................................................................................................131

3.4.3 Direct addressing ...........................................................................................................................132

3.4.4 Short direct addressing ..................................................................................................................133

3.4.5 Special function register (SFR) addressing....................................................................................134

3.4.6 Register indirect addressing ..........................................................................................................135

3.4.7 Based addressing ..........................................................................................................................136

3.4.8 Based indexed addressing.............................................................................................................137

3.4.9 Stack addressing ...........................................................................................................................138

CHAPTER 4 MEMORY BANK SELECT FUNCTION

(PD78F05x6A, 78F05x7A, AND 78F05x7DA (x = 2 to 4) ONLY) ........................... 139

4.1 Memory Bank.............................................................................................................................. 139

4.2 Difference in Representation of Memory Space ..................................................................... 1404.3 Memory Bank Select Register (BANK)..................................................................................... 141

4.4 Selecting Memory Bank............................................................................................................. 142

4.4.1 Referencing values between memory banks .................................................................................142

4.4.2 Branching instruction between memory banks ..............................................................................144

4.4.3 Subroutine call between memory banks ........................................................................................146

4.4.4 Instruction branch to bank area by interrupt...................................................................................148

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CHAPTER 5 PORT FUNCTIONS......................................................................................................... 150

5.1 Port Functions ............................................................................................................................ 150

5.2 Port Configuration...................................................................................................................... 154

5.2.1 Port 0 .............................................................................................................................................155

5.2.2 Port 1 .............................................................................................................................................166

5.2.3 Port 2 .............................................................................................................................................172

5.2.4 Port 3 .............................................................................................................................................174

5.2.5 Port 4 .............................................................................................................................................177

5.2.6 Port 5 .............................................................................................................................................179

5.2.7 Port 6 .............................................................................................................................................180

5.2.8 Port 7 .............................................................................................................................................184

5.2.9 Port 12 ...........................................................................................................................................186

5.2.10 Port 13 .........................................................................................................................................189

5.2.11 Port 14 .........................................................................................................................................190

5.3 Registers Controlling Port Function ........................................................................................ 194

5.4 Port Function Operations.......................................................................................................... 211

5.4.1 Writing to I/O port ...........................................................................................................................211

5.4.2 Reading from I/O port.....................................................................................................................211

5.4.3 Operations on I/O port....................................................................................................................211

5.5 Settings of Port Mode Register and Output Latch When Using Alternate Function...........211

5.6 Cautions on 1-Bit Manipulation Instruction for Port Register n (Pn).................................... 214

CHAPTER 6 CLOCK GENERATOR .................................................................................................... 215

6.1 Functions of Clock Generator................................................................................................... 215

6.2 Configuration of Clock Generator ............................................................................................ 216

6.3 Registers Controlling Clock Generator.................................................................................... 219

6.4 System Clock Oscillator ............................................................................................................ 2306.4.1 X1 oscillator....................................................................................................................................230

6.4.2 XT1 oscillator .................................................................................................................................230

6.4.3 When subsystem clock is not used ................................................................................................233

6.4.4 Internal high-speed oscillator .........................................................................................................233

6.4.5 Internal low-speed oscillator...........................................................................................................233

6.4.6 Prescaler........................................................................................................................................233

6.5 Clock Generator Operation .......................................................................................................234

6.6 Controlling Clock........................................................................................................................ 237

6.6.1 Example of controlling high-speed system clock............................................................................237

6.6.2 Example of controlling internal high-speed oscillation clock...........................................................240

6.6.3 Example of controlling subsystem clock.........................................................................................243

6.6.4 Example of controlling internal low-speed oscillation clock ............................................................245

6.6.5 Clocks supplied to CPU and peripheral hardware ..........................................................................246

6.6.6 CPU clock status transition diagram ..............................................................................................247

6.6.7 Condition before changing CPU clock and processing after changing CPU clock .........................254

6.6.8 Time required for switchover of CPU clock and main system clock ...............................................255

6.6.9 Conditions before clock oscillation is stopped ................................................................................257

6.6.10 Peripheral hardware and source clocks .......................................................................................258

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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 ........................................................ 259

7.1 Functions of 16-Bit Timer/Event Counters 00 and 01............................................................. 259

7.2 Configuration of 16-Bit Timer/Event Counters 00 and 01...................................................... 260

7.3 Registers Controlling 16-Bit Timer/Event Counters 00 and 01 ............................................. 266

7.4 Operation of 16-Bit Timer/Event Counters 00 and 01............................................................. 278

7.4.1 Interval timer operation ..................................................................................................................278

7.4.2 Square-wave output operation.......................................................................................................281

7.4.3 External event counter operation ...................................................................................................284

7.4.4 Operation in clear & start mode entered by TI00n pin valid edge input..........................................288

7.4.5 Free-running timer operation .........................................................................................................301

7.4.6 PPG output operation ....................................................................................................................310

7.4.7 One-shot pulse output operation....................................................................................................314

7.4.8 Pulse width measurement operation..............................................................................................319

7.5 Special Use of TM0n .................................................................................................................. 327

7.5.1 Rewriting CR01n during TM0n operation.......................................................................................327

7.5.2 Setting LVS0n and LVR0n .............................................................................................................327

7.6 Cautions for 16-Bit Timer/Event Counters 00 and 01............................................................. 329

CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 .......................................................... 334

8.1 Functions of 8-Bit Timer/Event Counters 50 and 51............................................................... 334

8.2 Configuration of 8-Bit Timer/Event Counters 50 and 51........................................................ 334

8.3 Registers Controlling 8-Bit Timer/Event Counters 50 and 51 ............................................... 337

8.4 Operations of 8-Bit Timer/Event Counters 50 and 51............................................................. 343

8.4.1 Operation as interval timer .............................................................................................................343

8.4.2 Operation as external event counter ..............................................................................................345

8.4.3 Square-wave output operation.......................................................................................................346

8.4.4 PWM output operation ...................................................................................................................3478.5 Cautions for 8-Bit Timer/Event Counters 50 and 51............................................................... 351

CHAPTER 9 8-BIT TIMERS H0 AND H1 .......................................................................................... 352

9.1 Functions of 8-Bit Timers H0 and H1 ....................................................................................... 352

9.2 Configuration of 8-Bit Timers H0 and H1................................................................................. 352

9.3 Registers Controlling 8-Bit Timers H0 and H1........................................................................ 356

9.4 Operation of 8-Bit Timers H0 and H1 ....................................................................................... 362

9.4.1 Operation as interval timer/square-wave output ............................................................................362

9.4.2 Operation as PWM output..............................................................................................................365

9.4.3 Carrier generator operation (8-bit timer H1 only) ...........................................................................371

CHAPTER 10 WATCH TIMER ............................................................................................................. 378

10.1 Functions of Watch Timer ....................................................................................................... 378

10.2 Configuration of Watch Timer................................................................................................. 380

10.3 Register Controlling Watch Timer.......................................................................................... 380

10.4 Watch Timer Operations.......................................................................................................... 382

10.4.1 Watch timer operation..................................................................................................................382

10.4.2 Interval timer operation ................................................................................................................382

10.5 Cautions for Watch Timer ....................................................................................................... 383

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CHAPTER 11 WATCHDOG TIMER .....................................................................................................384

11.1 Functions of Watchdog Timer................................................................................................. 384

11.2 Configuration of Watchdog Timer .......................................................................................... 385

11.3 Register Controlling Watchdog Timer.................................................................................... 386

11.4 Operation of Watchdog Timer................................................................................................. 387

11.4.1 Controlling operation of watchdog timer .......................................................................................387

11.4.2 Setting overflow time of watchdog timer.......................................................................................388

11.4.3 Setting window open period of watchdog timer............................................................................389

CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER............................................... 391

12.1 Functions of Clock Output/Buzzer Output Controller .......................................................... 391

12.2 Configuration of Clock Output/Buzzer Output Controller.................................................... 392

12.3 Registers Controlling Clock Output/Buzzer Output Controller........................................... 392

12.4 Operations of Clock Output/Buzzer Output Controller ........................................................ 396

12.4.1 Operation as clock output ............................................................................................................396

12.4.2 Operation as buzzer output ..........................................................................................................396

CHAPTER 13 A/D CONVERTER ......................................................................................................... 397

13.1 Function of A/D Converter....................................................................................................... 397

13.2 Configuration of A/D Converter ..............................................................................................398

13.3 Registers Used in A/D Converter............................................................................................ 400

13.4 A/D Converter Operations .......................................................................................................408

13.4.1 Basic operations of A/D converter................................................................................................408

13.4.2 Input voltage and conversion results ............................................................................................409

13.4.3 A/D converter operation mode .....................................................................................................411

13.5 How to Read A/D Converter Characteristics Table............................................................... 413

13.6 Cautions for A/D Converter..................................................................................................... 415

CHAPTER 14 SERIAL INTERFACE UART0 ...................................................................................... 419

14.1 Functions of Serial Interface UART0...................................................................................... 419

14.2 Configuration of Serial Interface UART0 ............................................................................... 420

14.3 Registers Controlling Serial Interface UART0....................................................................... 423

14.4 Operation of Serial Interface UART0 ...................................................................................... 428

14.4.1 Operation stop mode....................................................................................................................428

14.4.2 Asynchronous serial interface (UART) mode ...............................................................................429

14.4.3 Dedicated baud rate generator.....................................................................................................435

14.4.4 Calculation of baud rate ...............................................................................................................436

CHAPTER 15 SERIAL INTERFACE UART6 ...................................................................................... 440

15.1 Functions of Serial Interface UART6...................................................................................... 440

15.2 Configuration of Serial Interface UART6 ............................................................................... 444

15.3 Registers Controlling Serial Interface UART6....................................................................... 447

15.4 Operation of Serial Interface UART6 ...................................................................................... 456

15.4.1 Operation stop mode....................................................................................................................456

15.4.2 Asynchronous serial interface (UART) mode ...............................................................................457

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15.4.3 Dedicated baud rate generator ....................................................................................................470

15.4.4 Calculation of baud rate ...............................................................................................................472

CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11................................................................ 477

16.1 Functions of Serial Interfaces CSI10 and CSI11 ................................................................... 477

16.2 Configuration of Serial Interfaces CSI10 and CSI11............................................................. 478

16.3 Registers Controlling Serial Interfaces CSI10 and CSI11.................................................... 480

16.4 Operation of Serial Interfaces CSI10 and CSI11 ................................................................... 486

16.4.1 Operation stop mode ...................................................................................................................486

16.4.2 3-wire serial I/O mode ..................................................................................................................487

CHAPTER 17 SERIAL INTERFACE CSIA0 ....................................................................................... 499

17.1 Functions of Serial Interface CSIA0....................................................................................... 499

17.2 Configuration of Serial Interface CSIA0................................................................................. 500

17.3 Registers Controlling Serial Interface CSIA0........................................................................ 502

17.4 Operation of Serial Interface CSIA0 ....................................................................................... 511

17.4.1 Operation stop mode ...................................................................................................................511

17.4.2 3-wire serial I/O mode ..................................................................................................................512

17.4.3 3-wire serial I/O mode with automatic transmit/receive function ..................................................517

CHAPTER 18 SERIAL INTERFACE IIC0 ........................................................................................... 537

18.1 Functions of Serial Interface IIC0 ........................................................................................... 537

18.2 Configuration of Serial Interface IIC0..................................................................................... 540

18.3 Registers to Control Serial Interface IIC0 .............................................................................. 543

18.4 I2C Bus Mode Functions .......................................................................................................... 556

18.4.1 Pin configuration ..........................................................................................................................556

18.5 I2C Bus Definitions and Control Methods .............................................................................. 557

18.5.1 Start conditions ............................................................................................................................557

18.5.2 Addresses....................................................................................................................................558

18.5.3 Transfer direction specification ....................................................................................................558

18.5.4 Acknowledge (ACK).....................................................................................................................559

18.5.5 Stop condition ..............................................................................................................................560

18.5.6 Wait..............................................................................................................................................561

18.5.7 Canceling wait..............................................................................................................................563

18.5.8 Interrupt request (INTIIC0) generation timing and wait control ....................................................563

18.5.9 Address match detection method ................................................................................................564

18.5.10 Error detection ...........................................................................................................................564

18.5.11 Extension code ..........................................................................................................................565

18.5.12 Arbitration ..................................................................................................................................566

18.5.13 Wakeup function ........................................................................................................................567

18.5.14 Communication reservation .......................................................................................................568

18.5.15 Cautions.....................................................................................................................................571

18.5.16 Communication operations ........................................................................................................572

18.5.17 Timing of I2C interrupt request (INTIIC0) occurrence .................................................................580

18.6 Timing Charts ........................................................................................................................... 601

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CHAPTER 19 MULTIPLIER/DIVIDER................................................................................................... 608

19.1 Functions of Multiplier/Divider................................................................................................ 608

19.2 Configuration of Multiplier/Divider ......................................................................................... 608

19.3 Register Controlling Multiplier/Divider...................................................................................612

19.4 Operations of Multiplier/Divider.............................................................................................. 613

19.4.1 Multiplication operation ................................................................................................................613

19.4.2 Division operation.........................................................................................................................615

CHAPTER 20 INTERRUPT FUNCTIONS ............................................................................................ 617

20.1 Interrupt Function Types ......................................................................................................... 617

20.2 Interrupt Sources and Configuration ..................................................................................... 617

20.3 Registers Controlling Interrupt Functions............................................................................. 622

20.4 Interrupt Servicing Operations ............................................................................................... 643

20.4.1 Maskable interrupt acknowledgment............................................................................................643

20.4.2 Software interrupt request acknowledgment ................................................................................645

20.4.3 Multiple interrupt servicing ...........................................................................................................646

20.4.4 Interrupt request hold ...................................................................................................................649

CHAPTER 21 KEY INTERRUPT FUNCTION .....................................................................................650

21.1 Functions of Key Interrupt ...................................................................................................... 650

21.2 Configuration of Key Interrupt ................................................................................................ 651

21.3 Register Controlling Key Interrupt ......................................................................................... 652

CHAPTER 22 STANDBY FUNCTION.................................................................................................. 653

22.1 Standby Function and Configuration..................................................................................... 653

22.1.1 Standby function ..........................................................................................................................653

22.1.2 Registers controlling standby function..........................................................................................654

22.2 Standby Function Operation................................................................................................... 656

22.2.1 HALT mode..................................................................................................................................656

22.2.2 STOP mode .................................................................................................................................661

CHAPTER 23 RESET FUNCTION........................................................................................................ 668

23.1 Register for Confirming Reset Source ................................................................................... 678

CHAPTER 24 POWER-ON-CLEAR CIRCUIT...................................................................................... 679

24.1 Functions of Power-on-Clear Circuit...................................................................................... 679

24.2 Configuration of Power-on-Clear Circuit ............................................................................... 680

24.3 Operation of Power-on-Clear Circuit ...................................................................................... 680

24.4 Cautions for Power-on-Clear Circuit ...................................................................................... 683

CHAPTER 25 LOW-VOLTAGE DETECTOR ....................................................................................... 685

25.1 Functions of Low-Voltage Detector........................................................................................ 685

25.2 Configuration of Low-Voltage Detector ................................................................................. 686

25.3 Registers Controlling Low-Voltage Detector......................................................................... 686

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25.4 Operation of Low-Voltage Detector........................................................................................ 689

25.4.1 When used as reset .....................................................................................................................690

25.4.2 When used as interrupt................................................................................................................695

25.5 Cautions for Low-Voltage Detector ........................................................................................ 700

CHAPTER 26 OPTION BYTE............................................................................................................... 703

26.1 Functions of Option Bytes ...................................................................................................... 703

26.2 Format of Option Byte ............................................................................................................. 704

CHAPTER 27 FLASH MEMORY.......................................................................................................... 708

27.1 Internal Memory Size Switching Register.............................................................................. 708

27.2 Internal Expansion RAM Size Switching Register ................................................................ 709

27.3 Writing with Flash Memory Programmer............................................................................... 710

27.4 Programming Environment..................................................................................................... 711

27.5 Communication Mode.............................................................................................................. 711

27.6 Connection of Pins on Board.................................................................................................. 713

27.6.1 FLMD0 pin ...................................................................................................................................714

27.6.2 Serial interface pins .....................................................................................................................714

27.6.3 RESET pin ...................................................................................................................................716

27.6.4 Port pins.......................................................................................................................................716

27.6.5 REGC pin.....................................................................................................................................716

27.6.6 Other signal pins ..........................................................................................................................717

27.6.7 Power supply ...............................................................................................................................717

27.7 Programming Method.............................................................................................................. 718

27.7.1 Controlling flash memory .............................................................................................................718

27.7.2 Flash memory programming mode ..............................................................................................718

27.7.3 Selecting communication mode ...................................................................................................719

27.7.4 Communication commands .........................................................................................................72027.8 Security Settings ...................................................................................................................... 721

27.9 Processing Time for Each Command When PG-FP4 or PG-FP5 Is Used (Reference)...... 723

27.10 Flash Memory Programming by Self-Programming........................................................... 725

27.10.1 Boot swap function.....................................................................................................................732

CHAPTER 28 ON-CHIP DEBUG FUNCTION (PD78F05xxDA ONLY).......................................... 734

28.1 Connecting QB-78K0MINI or QB-MINI2 to PD78F05xxDA.................................................. 734

28.2 Reserved Area Used by QB-78K0MINI and QB-MINI2 .......................................................... 736

CHAPTER 29 INSTRUCTION SET ...................................................................................................... 737

29.1 Conventions Used in Operation List ...................................................................................... 737

29.1.1 Operand identifiers and specification methods ............................................................................737

29.1.2 Description of operation column ..................................................................................................738

29.1.3 Description of flag operation column............................................................................................738

29.2 Operation List ........................................................................................................................... 739

29.3 Instructions Listed by Addressing Type ............................................................................... 747

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CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)................................... 750

CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS).................................... 775

CHAPTER 32 PACKAGE DRAWINGS................................................................................................ 800

32.1 78K0/KB2................................................................................................................................... 800

32.2 78K0/KC2................................................................................................................................... 802

32.3 78K0/KD2................................................................................................................................... 805

32.4 78K0/KE2................................................................................................................................... 806

32.5 78K0/KF2 ................................................................................................................................... 811

CHAPTER 33 RECOMMENDED SOLDERING CONDITIONS........................................................... 813

CHAPTER 34 CAUTIONS FOR WAIT................................................................................................. 814

34.1 Cautions for Wait...................................................................................................................... 814

34.2 Peripheral Hardware That Generates Wait ............................................................................ 815

APPENDIX A DEVELOPMENT TOOLS............................................................................................... 817

A.1 Software Package ...................................................................................................................... 821

A.2 Language Processing Software ...............................................................................................821

A.3 Control Software........................................................................................................................ 822

A.4 Flash Memory Programming Tools.......................................................................................... 823

A.4.1 When using flash memory programmer FG-FP5, FL-PR5, FG-FP4, FL-PR4, PG-FPL3, and

FP-LITE3 .......................................................................................................................................823

A.4.2 When using on-chip debug emulator with programming function QB-MINI2 .................................824

A.5 Debugging Tools (Hardware).................................................................................................... 824

A.5.1 When using in-circuit emulator QB-78K0KX2 ................................................................................824

A.5.2 When using on-chip debug emulator QB-78K0MINI ......................................................................826

A.5.3 When using on-chip debug emulator with programming function QB-MINI2 .................................827

A.6 Debugging Tools (Software)..................................................................................................... 827

APPENDIX B NOTES ON TARGET SYSTEM DESIGN ................................................................... 828

APPENDIX C REGISTER INDEX......................................................................................................... 835

C.1 Register Index (In Alphabetical Order with Respect to Register Names)............................835

C.2 Register Index (In Alphabetical Order with Respect to Register Symbol)........................... 839

APPENDIX D LIST OF CAUTIONS..................................................................................................... 843

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1.1 Differences Between Conventional-specification Products (PD78F05xx) and Expanded-

specification Products (PD78F05xxA)

This manual describes the functions of the expanded-specification products (PD78F05xxA) of the 78K0/Kx2microcontrollers.

The differences between the conventional-specification products (PD78F05xx) and expanded-specification

products (PD78F05xxA) of the 78K0/Kx2 microcontrollers are described below.

The number of flash memory rewrites and retention time of standard products and (A) grade products

Processing time of the self programming library

Interrupt response time of the self programming library

A/D conversion time

Remark For the conventional-specification products (PD78F05xx) of the 78K0/Kx2 microcontrollers, refer to the

manual of each product. For the manual name and document number of each product, refer to the

INTRODUCTION.

1.1.1 Number of flash memory rewrites and retention time of standard products and (A) grade products

Item Conventional-specification

Products (PD78F05xx)

Expanded-specification Products (PD78F05xxA)

When a flash memory programmer is used, and

the librariesNote 1

provided by NEC Electronics

are used

1,000 times

(15 years)

When the EEPROM emulation librariesNote 2

provided by NEC Electronics are used, and the

rewritable ROM size is 4 KB

10,000 times

(3 years)

Number of rewrites per chip

(retention time)

100 times (10 years)

Conditions other than the aboveNote 3

100 times

(10 years)

Notes 1. The sample library specified by the 78K0/Kx2 Flash Memory Self Programming Users Manual

(Document No.: U17516E) is excluded.

2. The sample program specified by the 78K0/Kx2 EEPROM Emulation Application Note(Document No.:

U17517E) is excluded.

3. These include when the sample library specified by the 78K0/Kx2 Flash Memory Self Programming

Users Manual(Document No.: U17516E) and the sample program specified by the 78K0/Kx2 EEPROM

Emulation Application Note(Document No.: U17517E) are used.

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1.1.2 Processing time for self programming library

(1) Conventional-specification products (PD78F05xx) (1/3)

When internal high-speed oscillation clock is used and entry RAM is located outside short direct

addressing range

Processing Time (s)

Normal Model of C Compiler Static Model of C Compiler/Assembler

Library Name

Min. Max. Min. Max.

Self programming start library 4.25

Initialize library 977.75

Mode check library 753.875 753.125

Block blank check library 12770.875 12765.875

Block erase library 36909.5 356318 36904.5 356296.25

Word write library 1214 (1214.375) 2409 (2409.375) 1207 (1207.375) 2402 (2402.375)

Block verify library 25618.875 25613.875

Self programming end library 4.25

Option value: 03H 871.25 (871.375) 866 (866.125)

Option value: 04H 863.375 (863.5) 858.125 (858.25)

Get information library

Option value: 05H 1024.75 (1043.625) 1037.5 (1038.375)

Set information library 105524.75 790809.375 105523.75 790808.375

EEPROM write library 1496.5

(1496.875)

2691.5

(2691.875)

1489.5

(1489.875)

2684.5

(2684.875)

When internal high-speed oscillation clock is used and entry RAM is located in short direct

addressing range

Processing Time (s)


Library Name

Min. Max. Min. Max.

Self programming start library 4.25Initialize library 443.5

Mode check library 219.625 218.875

Block blank check library 12236.625 12231.625

Block erase library 36363.25 355771.75 36358.25 355750

Word write library 679.75

(680.125)

1874.75

(1875.125)

672.75

(673.125)

1867.75

(1868.125)

Block verify library 25072.625 25067.625

Self programming end library 4.25

Option value: 03H 337 (337.125) 331.75 (331.875)

Option value: 04H 329.125 (239.25) 323.875 (324)


Option value: 05H 502.25 (503.125) 497 (497.875)


EEPROM write library 962.25

(962.625)

2157.25

(2157.625)

955.25

(955.625)

2150.25

(2150.625)

Remark Values in parentheses indicate values when a write start address structure is located other than in the

internal high-speed RAM.

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When high-speed system clock (X1 oscillation or external clock input) is used and entry RAM is

located outside short direct addressing range

Processing Time (s)


Library Name

Min. Max. Min. Max.

Self programming start library 34/fCPU

Initialize library 49/fCPU+ 485.8125

Mode check library 35/fCPU + 374.75 29/fCPU + 374.75

Block blank check library 174/fCPU + 6382.0625 134/fCPU + 6382.0625

Block erase library 174/fCPU+

31093.875

174/fCPU+

298948.125

134/fCPU+

31093.875

134/fCPU+

298948.125

Word write library 318 (321)/fCPU+

644.125

318 (321)/fCPU+

1491.625

262 (265)/fCPU+

644.125

262 (265)/fCPU+

1491.625

Block verify library 174/fCPU + 13448.5625 134/fCPU + 13448.5625

Self programming end library 34/fCPU

Option value: 03H 171 (172 )/fCPU + 432.4375 129 (130)/fCPU + 432.4375

Option value: 04H 181 (182)/fCPU + 427.875 139 (140)/fCPU + 427.875



Set information library 75/fCPU+

79157.6875

75/fCPU + 652400 67fCPU+

79157.6875

67fCPU + 652400

EEPROM write library 318 (321)/fCPU+

799.875

318 (321)/fCPU+

1647.375

262 (265)/fCPU+

799.875

262 (265)/fCPU+

1647.375

Remarks 1. Values in parentheses indicate values when a write start address structure is located other than in the


2. fCPU: CPU operation clock frequency

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located in short direct addressing range

Processing Time (s)


Library Name

Min. Max. Min. Max.


Initialize library 49/fCPU+ 224.6875

Mode check library 35/fCPU + 113.625 29/fCPU + 113.625

Block blank check library 174/fCPU + 6120.9375 134/fCPU + 6120.9375

Block erase library 174/fCPU+

30820.75

174/fCPU+

298675

134/fCPU+

30820.75

134/fCPU+

298675

Word write library 318 (321)/fCPU+

383

318 (321)/fCPU+

1230.5

262 (265)/fCPU+

383

262 (265)/fCPU+

1230.5

Block verify library 174/fCPU + 13175.4375 134/fCPU+ 13175.4375






Set information library 75/fCPU+

78884.5625

75/fCPU +

527566.875

67/fCPU+

78884.5625

67/fCPU +

527566.875

EEPROM write library 318 (321)/fCPU+

538.75

318 (321)/fCPU+

1386.25

262 (265)/fCPU+

538.75

262 (265)/fCPU+

1386.25

Remarks 1. Values in parentheses indicate values when a write start address structure is located other than in the



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(2) Expanded-specification products (PD78F05xxA) (1/3)

When internal high-speed oscillation clock is used and entry RAM is located outside short direct

addressing range

Processing Time (s)


Library Name

Min. Max. Min. Max.

Self programming start library 4.0 4.5 4.0 4.5

Initialize library 1105.9 1106.6 1105.9 1106.6

Mode check library 905.7 906.1 904.9 905.3

Block blank check library 12776.1 12778.3 12770.9 12772.6

Block erase library 26050.4 349971.3 26045.3 349965.6

Word write library 1180.1 + 203 w 1184.3 + 2241

w

1172.9 + 203 w 1176.3 + 2241

w

Block verify library 25337.9 25340.2 25332.8 25334.5

Self programming end library 4.0 4.5 4.0 4.5

Option value: 03H 1072.9 1075.2 1067.5 1069.1

Option value: 04H 1060.2 1062.6 1054.8 1056.6


Option value: 05H 1023.8 1028.2 1018.3 1022.1


EEPROM write library 1316.8 + 347 w 1320.9 + 2385

w

1309.0 + 347 w 1312.4 + 2385

w

When internal high-speed oscillation clock is used and entry RAM is located in short direct

addressing range

Processing Time (s)


Library Name

Min. Max. Min. Max.

Self programming start library 4.0 4.5 4.0 4.5

Initialize library 449.5 450.2 449.5 450.2

Mode check library 249.3 249.7 248.6 248.9



Word write library 445.8 + 203 w 449.9 + 2241 w 438.5 + 203 w 441.9 + 2241 w


Self programming end library 4.0 4.5 4.0 4.5

Option value: 03H 417.6 419.8 412.1 413.8

Option value: 04H 405.0 407.4 399.5 401.3


Option value: 05H 367.4 371.8 361.9 365.8


EEPROM write library 795.1 + 347 w 799.3 + 2385 w 787.4 + 347 w 790.8 + 2385 w

Remarks 1. The above processing times are those when a write start address structure is located in the internal

high-speed RAM and during stabilized operation of the internal high-speed oscillator (RSTS = 1).

2. RSTS: Bit 7 of the internal oscillation mode register (RCM)

3. w: Number of words in write data (1 word = 4 bytes)

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located outside short direct addressing range

Processing Time (s)


Library Name

Min. Max. Min. Max.


Initialize library 55/fCPU+ 594

Mode check library 36/fCPU+ 495 30/fCPU+ 495

Block blank check library 179/fCPU+ 6429 136/fCPU+ 6429

Block erase library 179/fCPU+ 19713 179/fCPU+

268079

136/fCPU+ 19713 136/fCPU+

268079

Word write library 333/fCPU+ 647 +

136 w

333/fCPU+ 647 +

1647 w

272/fCPU+ 647 +

136 w

272/fCPU+ 647 +

1647 w

Block verify library 179/fCPU+ 13284 136/fCPU+ 13284


Option value: 03H 180/fCPU+ 581 134fCPU+ 581

Option value: 04H 190/fCPU+ 574 144/fCPU+ 574



Set information library 80/fCPU+ 43181 80/fCPU+ 572934 72/fCPU+ 43181 72/fCPU+ 572934

EEPROM write library 333/fCPU+ 729 +

209 w

333/fCPU+ 729 +

1722 w

268/fCPU+ 729 +

209 w

268/fCPU+ 729 +

1722 w






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located in short direct addressing range

Processing Time (s)


Library Name

Min. Max. Min. Max.


Initialize library 55/fCPU+ 272

Mode check library 36/fCPU+ 173 30/fCPU+ 173

Block blank check library 179/fCPU+ 6108 136/fCPU+ 6108

Block erase library 179/fCPU+ 19371 179/fCPU+

267738

136/fCPU+ 19371 136/fCPU+

267738

Word write library 333/fCPU+ 247 +

136 w

333/fCPU+ 247 +

1647 w

272/fCPU+ 247 +

136 w

272/fCPU+ 247 +

1647 w

Block verify library 179/fCPU+ 12964 136/fCPU+ 12964







EEPROM write library 333/fCPU+ 516 +

209 w

333/fCPU+ 516 +

1722 w

268/fCPU+ 516 +

209 w

268/fCPU+ 516 +

1722 w






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1.1.3 Interrupt response time for self programming library


When internal high-speed oscillation clock is used

Interrupt Response Time (s (Max.))


Library Name

Entry RAM location

is outside short

direct addressing

range

Entry RAM location

is in short direct

addressing range

Entry RAM location

is outside short

direct addressing

range

Entry RAM location

is in short direct

addressing range



Word write library 2505.8 1942.8 2497.8 1934.8



EEPROM write library 2760.8 2168.8 2759.5 2167.5

Remarks 1. The above interrupt response times are those during stabilized operation of the internal high-speed

oscillator (RSTS = 1).


When high-speed system clock is used (normal model of C compiler)


RSTOP = 0, RSTS = 1 RSTOP = 1

Library Name

Entry RAM location

is outside short

direct addressing

range

Entry RAM location

is in short direct

addressing range

Entry RAM location

is outside short

direct addressing

range

Entry RAM location

is in short direct

addressing range

Block blank check library 179/fCPU+ 507 179/fCPU+ 407 179/fCPU+ 1650 179/fCPU+ 714

Block erase library 179/fCPU+ 559 179/fCPU+ 460 179/fCPU+ 1702 179/fCPU+ 767

Word write library 333/fCPU+ 1589 333/fCPU+ 1298 333/fCPU+ 2732 333/fCPU+ 1605

Block verify library 179/fCPU+ 518 179/fCPU+ 418 179/fCPU+ 1661 179/fCPU+ 725


29/fCPU+ 1759 29/fCPU+ 1468 29/fCPU+ 1759 29/fCPU+ 1468EEPROM write libraryNote

333/fCPU+ 834 333/fCPU+ 512 333/fCPU+ 2061 333/fCPU+ 873

Note The longer value of the EEPROM write library interrupt response time becomes the Max. value, depending

on the value of fCPU.

Remarks 1. fCPU: CPU operation clock frequency

2. RSTOP: Bit 0 of the internal oscillation mode register (RCM)3. RSTS: Bit 7 of the internal oscillation mode register (RCM)

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When high-speed system clock is used (static model of C compiler/assembler)


RSTOP = 0, RSTS = 1 RSTOP = 1

Library Name

Entry RAM location

is outside short

direct addressing

range

Entry RAM location

is in short direct

addressing range

Entry RAM location

is outside short

direct addressing

range

Entry RAM location

is in short direct

addressing range

Block blank check library 136/fCPU + 507 136/fCPU + 407 136/fCPU + 1650 136/fCPU + 714

Block erase library 136/fCPU + 559 136/fCPU + 460 136/fCPU + 1702 136/fCPU + 767

Word write library 272/fCPU + 1589 272/fCPU + 1298 272/fCPU + 2732 272/fCPU + 1605

Block verify library 136/fCPU + 518 136/fCPU + 418 136/fCPU + 1661 136/fCPU + 725

Set information library 72/fCPU + 370 72/fCPU + 165 72/fCPU + 1513 72/fCPU + 472

19/fCPU + 1759 19/fCPU + 1468 19/fCPU + 1759 19/fCPU + 1468EEPROM write libraryNote

268/fCPU + 834 268/fCPU + 512 268/fCPU + 2061 268/fCPU + 873

Note The longer value of the EEPROM write library interrupt response time becomes the Max. value, depending

on the value of fCPU.

Remarks 1. fCPU: CPU operation clock frequency

2. RSTOP: Bit 0 of the internal oscillation mode register (RCM)


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When internal high-speed oscillation clock is used



Library Name

Entry RAM location

is outside short

direct addressing

range

Entry RAM location

is in short direct

addressing range

Entry RAM location

is outside short

direct addressing

range

Entry RAM location

is in short direct

addressing range



Word write library 1247.2 579.2 1239.2 571.2

Date post:	01-Jun-2018
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