1 January 2008

UPF Solutions Guide

2 January 2008

UPF is a Copyright of Accellera. All other trademarks and copyrights belong to their respective owners. There is no intent to violate anyone’s rights. Original Version: July 2007 Current Version: January 2008 All the information contained in this solution guide about products and contacts is provided by respective vendors. The user of this solution guide is requested to check the latest product information by contacting the respective vendor. This solution guide should not be used as the sole source of information for making decisions regarding suitability of UPF or any UPF related products for any purpose.

Latest UPF Solutions Guide can be downloaded from: http://www.accellera.org/upf/SolutionsGuide.pdf

3 January 2008

Table of Contents

UPF Solutions Providers 4

UPF Solutions At-A-Glance 5

ARM Artisan Physical IP 6

Atrenta SpyGlass-Power 7

Axiom MPSIM 8

Azuro PowerCentric 10

Interra Systems 11

Magma Talus Power 12

Magma Quartz Rail 13

Mentor Graphics Questa 14

Mentor Graphics FormalPro 14

Mentor Graphics Catapult C 16

Mentor Graphics Olympus-SoC 17

Synopsys System to GDSII 19

Virage Low Power Library 22

Springer Synopsys/ARM Low Power Methodology Manual (LPMM) 23

What is UPF? Back Cover

UPF 1.0 Quick Reference Guide Center Pull-Out

4 January 2008

UPF Solutions Providers

5 January 2008

UPF Solutions At-A-Glance

Company Product Usage

ARM Physical IP Low Power Management Solutions

Atrenta Spy Glass-Power Analysis

Axiom MPSim Verification

Azuro PowerCentric Implementation

Interra Systems UPF Analyzer Analyzer

Magma Talus Power Implementation

Magma Quartz Rail Analysis

Mentor Questa Verification

Mentor FormalPro Verification

Mentor Catapult C Implementation

Mentor Olympus-SoC Implementation

Springer Synopsys/ARM Low Power Methodology Manual

How-to Book

Synopsys DesignWare IP IP blocks

Synopsys VCS, MVSIM Verification

Synopsys Design Compiler Ultra Implementation

Synopsys Power Compiler Implementation

Synopsys DFT Compiler/MAX Implementation

Synopsys MVRC Analysis

Synopsys Formality Verification

Synopsys IC Compiler Implementation

Synopsys PrimeTime/PX,SI Analysis

Virage Silicon Aware IP Low Power Libraries

6 January 2008

ARM is a recognized leader in low power. ARM designs the technology that lies at the heart of advanced digital products, from wireless, networking and consumer entertainment solutions to imaging, automotive, security and storage devices. The ARM® product family of Artisan® Physical IP solutions provides the building blocks to create highly optimized system-on-chip (SoC) designs and includes

• Standard Cells and Power Management Kits

• Memories with and without Integrated Power Gating

• I/Os • DDR • PHYs

The products are offered in multiple platforms targeting high performance, high density, and mainstream applications. Additional products are provided to support various power management techniques. With the scale of the ARM platforms and program offering, designers have the flexibility to optimize their designs as needed for a given application. Products are available now that support UPF-enabled flows.

Combined with the company’s broad Partner community, ARM provides a total system solution that offers a fast, reliable path to market for leading electronics companies. More information on ARM is available at http://www.arm.com. . Company Website: http://access.arm.com

Contact: upf@arm.com

Availability: Now

Memory

Low Power Memory

Memory

Standard Cells+ PMK

I/O Cells

Pervasive SoC IP

DDR Serial PHYs

7 January 2008

SpyGlass-Power™ SpyGlass-Power delivers a comprehensive low power solution to jumpstart power savings at RTL, and sustains power goals throughout the flow. For Power Verification, SpyGlass-Power provides designers consistent validation that the power design intent is met at RTL, early gate-level, and late gate-level design stages. This prevents costly re-spins due to incorrectly inserted level shifters or isolation logic, incorrectly connected power/ground, or unexpected power-up/power-down sequencing. For Power Estimation, SpyGlass-Power calculates ‘power numbers’, which gives designers the opportunity to achieve power goals early, at RTL. For Power Reduction, SpyGlass-Power improves effectiveness of clock gating and identifies new clock gating opportunities, which bridges the existing power-results gap between a power-expert and a power-novice. Use of UPF SpyGlass- Power can read UPF as the power design intent, used in Power and Voltage Domain Verification and Power Domain Sequencing. Also, since Power Estimation and Power Reduction are power-domain-aware, information contained in UPF is read and appropriately applied.

Flow Diagram

Company Website: www.atrenta.com Contact: upf@atrenta.com Availability: Now available in support of customer engagements.

SpyGlass Power

Power & Voltage Domain VerificationVerify and fix level shifter, isolation logic, SRPG, MTCMOS

RTL, gates, layout

Power Domain SequencingFormally prove power up/down sequencing

Power EstimationTiming-aware power estimation at RTL, gates, layout

Power Reduction and PlanningIntelligent power reduction and domain planning at RTL

UPF

Library dataSuppliesScope

DomainsSignals

SpyGlass Power

Power & Voltage Domain VerificationVerify and fix level shifter, isolation logic, SRPG, MTCMOS

RTL, gates, layout

Power Domain SequencingFormally prove power up/down sequencing

Power EstimationTiming-aware power estimation at RTL, gates, layout

Power Reduction and PlanningIntelligent power reduction and domain planning at RTL

UPF

Library dataSuppliesScope

DomainsSignals

8 January 2008

AXIOM offers an integrated functional verification solution that leverages multi-CPU technology to significantly improve performance, productivity and predictability. AXIOM MPSim simulation platform consists of

• MPSim – Highest performance multi-cpu simulator in the supporting SystemVerilog/Verilog/OpenVera/SystemC and UPF

• Designer – Advanced debugging environment for design, testbench, assertions and protocols to help locate and fix the most complex design bugs

• Protometer – Advanced protocol coverage technology that is testbench language and implementation independent. Many standard protocols are already available and many are under development

• MCDV - Multi-Clock Domain Verification and analysis

UPF Support with MPSIM

PROTOMETER

9 January 2008

MPSim provides complete support of the simulation semantics of the UPF low power specification. Correctly implementing the UPF capabilities within the simulation allows the users to verify these capabilities which are specified outside of their normal RTL verification environments. Proper modeling of retention, isolation and power down corruption facilitates low power design and identify potential power-down problems. In addition to the simulation capabilities, low power design capabilities are fully integrated into the powerful MPSim Designer debug environment. These capabilities include the ability to graphically track the complete power network, visualize the state of all the power switches as well as the power on/off status of every block in the design through both the source as well as the schematic at any point in the simulation. MPSim through it’s unique ProtoMeter technology also provides complete information about the coverage for the various power options within the UPF specifications through your complete verification. MPSim not only generates the correct results and helps debug low power design, it also helps the user verify that the various different power modes and specifications were actually verified as part of the verification process. Company Website: www.axiom-da.com Company Contact: upf@axiom-da.com UPF Support: Now

MPSim Multi-CPU

Simulation

Test bench

RTL

Designer Debug

ProtoMete

r Coverage

UPF Specification Simulate power off corruption

Simulate retention and save/restore of states

Simulate isolation and clamping

Trace complete power network and switches

Visualize power switch states

Visualize the states of powered off blocks throughout simulation

Automate power verification combinations

Verify all possible power combinations

Power verification closure

MPSim

Designer

ProtoMeter

10 January 2008

Placed gates (Balanced clocks)

Placed gates (UPF Q4-07)

Gate level netlist

GDSII

PowerCentric™ Low Power Clock Implementation

Physical Synthesis

Routing

PowerCentric Solution Azuro’s PowerCentric™, targets the clock power problem in digital chip design. Without careful power management the clock network can account for as much as 80% of on-chip switching power. PowerCentric significantly reduces on-chip switching power above and beyond existing low power industry design flows. Azuro’s customers can translate this power saving advantage directly into enhanced functionality, talk time or play time on their devices. Azuro's PowerCentric operates as a complete replacement for clock tree synthesis and post-CTS optimization within digital design flows, comprehensively addressing power, timing, and variability within one unified optimization environment. PowerCentric brings together unique algorithms for clock tree buffering, gate-level clock gate logic synthesis, and statistical average-case dynamic power analysis, to deliver a completely unified clock implementation solution for advanced nanometer designs. PowerCentric will support reading pertinent UPF constructs in Q4-07. Company Website: www.azuro.com Company Contact: upf@azuro.com UPF Support: Q4-2007.

11 January 2008

Interra Systems is a leading provider of products and services for memory, ASIC, SoC and design automation. Interra offers support for System Verilog, Verilog, VHDL and other standards, including UPF, for EDA tools, memory design automation, design flow and methodologies, compliance for digital audio video standards, encoders, decoders, automated digital content verification, and platform specific embedded software development to accelerate product deployment. Adaptive solutions from Interra Systems provide significant time to market and cost effectiveness. Support of EDA standards from Interra such as Cheetah, the Verilog and System Verilog analyzer, Jaguar, the VHDL analyzer and Concorde, synthesis elaborator are used as language front-ends by several well known industry tools from major EDA vendors, such as Synopsys, Cadence, Mentor, as well as startups. Robust field proven quality, professional support and customization services enable EDA tool developers and SoC companies to reduce time-to-market and development cost. Interra provides latest support for VHDL standard IEEE 1076, Verilog standard IEEE 1364 and System Verilog standard IEEE 1800. Interra provides analyzers for EDA standards like UPF, SDF, SPEF, DEF, LEF, HSPICE, and Liberty. BeaconTM test suites ensure compliance, coverage and quality of tool’s support for EDA standards such as System Verilog, Verilog 2001, Synthesizable Verilog and VHDL, Verilog/VHDL mixed interface and PSL. Several EDA tool companies use Beacon test suites today to improve quality of their products for designers. UPF Analyzer

UPF

User Power Application

UPF Analyzer

Analysis

OM

API

Interra’s UPF analyzer provides a customizable framework for annotating power intent into the design at any stage in the design flow. UPF analyzer has a flexible and easy to integrate C++ interface based on object oriented design with completely editable and extensible underlying database. It is an essential building block for EDA solutions that need to support UPF standard for power information. Key Features of UPF Analyzer

• Supports Accellera standard UPF 1.0 • Flexible C++ interface • Easy to integrate in TCL as well as C++ environment • Completely editable and extensible object model • Can be used at any stage in the design flow • Accelerates time to market

UPF Analyzer is now available on Solaris 32/64, Linux 32/64 and Windows Company website: www.interrasystems.com Company contact: info@interrasystems.com

12 January 2008

Talus Power™ Talus Power provides a comprehensive RTL-to-GDSII solution for power optimization and management. Optimal power management is enabled throughout the implementation flow with power-aware synthesis, physical optimization, clock tree synthesis and routing, enabling designers to minimize power and ensure uniform power distribution. Talus Power is fully integrated with Magma’s RTL-to-GDSII implementation flow to enable continuous power, timing, area tradeoffs throughout the design flow. Talus Power addresses power early in the design flow through power-aware synthesis using power gating, advanced clock gating, and other supporting techniques. Talus Power supports power aware physical synthesis for the backend design flow using advanced techniques such as an automated Multi-VDD flow with gas station methodology, MTCMOS for aggressive leakage savings and power aware CTS to optimize clock tree power. UPF Support Talus Power reads in UPF at the beginning of RTL2GDS flow to read in the power constraints for the low power flow. Power constraints such as clock gating, retention flop synthesis and Multi-VDD domain definitions can be defined for dynamic power reduction. Special cells such as level shifters and isolation cells can be inferred during the synthesis stage for supporting Multi-VDD flows. For powered down domains, switches can be inferred at the RTL stage to facilitate simulation. State tables can be used to define the relationship between the different domains that have been created. Talus Power can write out UPF at any point of the design flow for easy inter-operability. Company Website: www.magma-da.com Contact: upf@magma-da.com Availability: Talus Power is available now.

13 January 2008

Quartz Rail™ Quartz Rail provides a power solution that is integrated within Magma’s RTL-to-GDSII implementation flow. It enables accurate analysis and management of power integrity throughout the design implementation flow, thereby ensuring rapid convergence. Quartz Rail provides a complete methodology for power and rail analysis throughout the design flow minimizes power integrity problems and limits post-layout analysis and repair.

Transient analysis accounts for sudden changes in power consumption by considering decoupling capacitors and package inductance. The Embedded power analysis engine accounts for static, dynamic and short circuit power. Quartz Rail can also perform thermal analysis to account for temperature impact on leakage power. The embedded characterization capability for switching current waveform and intrinsic de-coupling capacitance greatly improves accuracy. Accurate memory modeling flow facilitates full chip dynamic IR drop analysis. Intelligent guidance for de-cap insertion based on transient analysis helps optimize leakage power and improve yield. Quartz Rail interfaces with industry-standard simulators and supports standard file formats including pre-characterized libraries.

Quartz Rail reads in UPF at the beginning of the flow to read in the power constraints for power analysis. Activity information can be read in the form of SAIF file for power analysis. VDD domain definitions can be used for domain specific IR drop analysis based on domain voltages. Leakage power and switching power data can be directly read in from the library for accurate power analysis. Company Website: www.magma-da.com Contact: upf@magma-da.com Availability: Quartz Rail is available now.

14 January 2008

Questa is Mentor Graphic's Advanced Verification Environment and is the only integrated verification platform that can improve quality, productivity, and predictability for any verification flow. Questa provides an integrated standards-based platform with leading support for SystemVerilog, SystemC, VHDL, Verilog and PSL. System to gate-level verification is supported with verification environments built on the Advanced Verification Methodology framework. Questa delivers advanced verification technology with assertion-based verification and the Questa Verification Library to improve time-to-quality, automated test generation with powerful, fast constraint solver technology and integrated verification management based on the industry’s only unified coverage database for coverage-driven management of verification against plan. Questa supports verification of designs incorporating UPF power specifications to capture the power management architecture. Through accurate modeling and support of the effects of power shut-off of power domains as well as powerful capabilities of accurate modeling of retention and isolation functionality at RTL, Questa provides the ability to find and fix problems in the power management design before it is committed to implementation.

FormalPro provides high performance and high capacity logic equivalence verification. FormalPro ensures that implemented designs are functionally equivalent to the verified RTL design, gate-level design, or RTL plus UPF. FormalPro ensures that a low power design gate level implementation is equivalent to the RTL logic specification constrained by a UPF power specification. FormalPro provides power management-specific equivalency checks for retention, isolation and level shifting.

15 January 2008

Flow Diagram

16 January 2008

Mentor Graphics Catapult C Synthesis - UPF Support Mentor Graphics Corp. has made significant investments in the field of high-level synthesis resulting in the wide adoption of Catapult® C Synthesis. With Catapult, algorithms written in industry-standard ANSI C++ are synthesized into high-performance, concurrent hardware with results equivalent to and often better than hand-coded RTL. This results in productivity gains from 10-100x over traditional RTL methodologies. This single source methodology also results in fewer design errors and a significant reduction in overall verification burden. As a result of these major benefits, many of today’s top semiconductor companies have adopted high-level synthesis as a critical component of their design flow. Catapult integrates into implementation and verification flows using the UPF power specifications by generating targeted RTL and through integrated standards-based flows. Catapult enables users to develop pure ANSI C++ source code that is easily retargeted at different clock speeds, voltages, memory architectures and ASIC libraries. Catapult's integrated flows run industry standard RTL synthesis and power optimization tools enabling an integrated verification and power exploration methodology. All data from the flows is back annotated to Catapult for further analysis, allowing users to easily select the architecture that best meets their power, performance and area goals.

Memory Architecture

Quality Requirements and Synthesis Style

Performance, Area, Power and Interface

Requirements

Floating-Point Algorithm

Floating-Point C++ Model

Fixed-Point C++ Model

Hardware ASIC/FPGA

CatapultInterface

Constraint

Micro-Architecture Constraint

Area + Static Performance

Estimates

Dynamic Performance

Data RTL + Flow Scripts

Formal Verification Simulation

Accurate Timing and Area RTL Synthesis

+ Place and RoutePower

ConsumptionPower Analysis

Memory Architecture

Quality Requirements and Synthesis Style

Performance, Area, Power and Interface

Requirements

Floating-Point Algorithm

Floating-Point C++ Model

Fixed-Point C++ Model

Hardware ASIC/FPGA

Catapult

Interface Constraint

Micro-Architecture Constraint

Area + Static Performance

Estimates

Dynamic Performance

Data RTL + Flow Scripts

Formal Verification Simulation

Accurate Timing and Area RTL Synthesis

+ Place and RoutePower

ConsumptionPower Analysis

17 January 2008

Mentor Graphics Olympus-SoC™ Place and Route System The Mentor Graphics Olympus-SoC place and route system is unique in providing low power layout optimization based on a Multi-Corner-Multi-Mode timing engine. MCMM analysis allows designers to answer tough design questions such as: How will voltage islands affect my signoff checks? What corners will we use to optimize for leakage power? What corners will we use for setup/hold optimization? What about common paths?

Multi-Voltage designs require concurrent MCMM timing and optimization to prevent the classic “ping-pong battle” between leakage and timing closure. Designers can specify any number of modes and corners to be considered during routing optimization to ensure closure in a single pass. Olympus-SoC provides features to enable complete graphical analysis, optimization and verification of power domain cells and connectivity through the entire place-and-route flow. It provides support for level shifter insertion, and TCL commands for level shifter and isolation cell analysis and reporting before implementation in the netlist. Olympus-SoC also provides full support for voltage islands including a native row-cutter that “sees” legal rows and islands, properties for island-aware routing, eco-route and buffering for nets crossing islands. Olympus-SoC also supports multi-VDD route-based optimization including the ability to maintain a single port of entry for boundary nets, respecting

18 January 2008

voltage island boundaries. The Olympus-SoC optimizer can directly control route topology to detour around an island in order to buffer a signal integrity (SI) violation. Critical nets can be allowed to cross an island while non-critical nets buffer around an island.

Company Website: www.mentor.com Scalable Verification Website: www.mentor.com/products/fv Olympus Product Information: http://www.mentor.com/products/ic_nanometer_design/cl_floorplan/olympus/index.cfm Contact: upf@mentor.com Availability: Olympus-SoC, Questa and FormalPro power aware verification capabilities with UPF support are available immediately.

19 January 2008

System to GDSII Complete “system to GDSII” solution for SoC verification, design and signoff that leverages industry standards such as UPF, SystemVerilog, Liberty and VHDL to provide a complete and interoperable flow. Synopsys’ low-power tools are founded on advanced technology and automation that implements a completely correlated end-to-end solution. The complete UPF flow is based on a tooling that has seen over 25 multi-voltage and power-gated tapeout successes over the past two years. Innovator Integrated development environment (IDE) that enables designers to develop, run and debug Virtual Platforms. Innovator allows designers to rapidly build Virtual Platforms and instantiate, configure and connect low-power DesignWare IP and other components for early and accurate exploration of low-power architecture. DesignWare® IP Broad portfolio of implementation IP, verification IP and hardened PHYs including popular protocols such as USB, PCI Express™, DDR2, Serial ATA, Certified Wireless USB, Ethernet and AMBA®. Synopsys IP is highly optimized for low power using a variety of leading techniques, yielding power dissipation numbers that are often 30-50 percent lower than others. VCS® Comprehensive functional verification solution with built-in testbench, coverage, assertion and debug technology. VCS supports power-aware verification, including correct handling of retention registers and power-up/power-down sequences. MVSIM and MVRC MVSIM is a Voltage-Aware simulator and MVRC is a Voltage-Aware static checker. Together, they provide maximum accuracy for verification of power-managed designs. The solutions detect power management bugs for all voltage-control techniques and are production proven with over 50 tape-outs. Design Compiler Ultra™ Comprehensive RTL synthesis solution delivering best QoR and productivity. Design Compiler Ultra includes power- and test-aware Topographical Technology that delivers early, accurate power estimates for predictability and fast time-to-results.

Predictable Success

20 January 2008

Power Compiler Complete power management synthesis solution for achieving the lowest power design. Supports multi-voltage, MTCMOS power gating, multi-threshold leakage, gate-level power optimization, clock gating and operand isolation. DFT Compiler/DFT MAX Power-aware adaptive scan compression DFT solution that adds testability to designs while reducing test vectors and test time. DFT MAX/DFT Compiler performs intelligent test structure insertion optimized for power domains and test power constraints. Formality® Advanced equivalence checker that formally verifies multi-voltage and power-gated designs. Formality ensures the gate-level implementation of a power-gated, multi-voltage design with state retention is equivalent to the original RTL. IC Compiler Complete physical implementation solution with hierarchical design planning with automated power network synthesis and analysis. IC Compiler includes XPS technology which provides a single convergent flow from netlist to silicon with support for multi-voltage designs, multi-threshold leakage, low-power placement and CTS, and state retention power gating. PrimeTime Suite (including PX, SI) Concurrent timing, signal integrity and power analysis in a single environment. PrimeTime enables complete signoff of low-power designs in a single step. PrimeRail Power integrity sign-off with full-chip dynamic power integrity solution. PrimeRail delivers highly accurate cell- and transistor-level dynamic voltage-drop and electromigration analysis. TetraMAX Power-aware manufacturing test pattern generation for designs incorporating scan design-for-test (DFT) techniques including compression. TetraMAX optimizes and compresses test vectors for minimal test time while remaining within test power constraints.

21 January 2008

Company Website: www.synopsys.com Contact: upf@synopsys.com

UPF Availability: Now

Pow

er-A

war

eS

igno

ff

PrimeRailPrimeTime

UPF

Pow

er-A

war

eIm

plem

enta

tion

IC CompilerDFT MAX/TetraMAX

Design Compiler

RTL

Pow

er-A

war

eV

erifi

catio

nMVRC

VCS+MVSIM

Formality

Pow

er-A

war

eS

igno

ff

PrimeRailPrimeTime

UPF

Pow

er-A

war

eIm

plem

enta

tion

IC CompilerDFT MAX/TetraMAX

Design Compiler

RTL

Pow

er-A

war

eV

erifi

catio

nMVRC

VCS+MVSIM

Formality

22 January 2008

The Industry’s Trusted Semiconductor IP Vendor for Low Power Description: Virage Logic is a technology market leader providing advanced embedded memory IP for designing complex integrated circuits. The company is a global leader in IP platforms comprising embedded memories, logic, and I/Os, and is pioneering Silicon Aware IP™ which integrates Physical IP with embedded test, diagnostic, and repair capabilities of Infrastructure IP to help ensure manufacturability and optimized yield at advanced process nodes. As a leading supplier of low power Semiconductor IP for nearly a decade, Virage Logic collaborates with the leading EDA vendors for integration into UPF-enabled RTL2GDS flows.

Wide Breadth of Semiconductor IP Meets SoC Design Requirements:

Company Website: www.viragelogic.com Contact: upf@viragelogic.com Availability: Now

IPrima Foundation High-Density Logic

High-Density Memory

Base I/O

AASSAAPP LLooggiicc

MMeettaall PPrrooggrraammmmaabbllee High-Speed High-Density

SSttaannddaarrdd CCeellllss

High-Speed Ultra-High-Density Ultra-Low-Power

ECO

SSTTAARR MMeemmoorryy SSyysstteemm Star Memories

BIST & Repair IP

AASSAAPP MMeemmoorryy High-Speed

Ultra-Low-Power

NNOOVVeeAA Non Volatile Memory

SSppeecciiaallttyy II//OOss

SSTL-2 HSTL-2

PCI and PCI-X USB1.1

*all included in Base I/O package

VVaalluuee AAddddeedd IIPP

23 January 2008

Low Power Methodology Manual (LPMM) Authored by low power experts at ARM and Synopsys, the LPMM is a practical & immediately useful guide to low power methodology aimed at enabling mainstream designers to adopt the latest power management techniques. The LPMM is based on extensive experience and silicon examples with real data and offers balanced content spanning theory and practical implementation. The LPMM methodology is demonstrated through a tool- and IP-independent flow and includes UPF examples. Company Website: http://www.springer.com http://www.lpmm-book.org Contact: Alex.Greene@springer.com Availability: NOW

24 January 2008

What is UPF?

Unified Power Format (UPF), a format to describe low power intent for design implementation, analysis and verification, is the latest standard developed by Accellera. It enables open, multi-vendor tool flows and solutions for low-power ASIC and SoC design. The true value of a single, widely adopted standard is demonstrated by interoperability of products from a range of EDA suppliers who support the UPF standard. Designers of modern, low-power ICs are the ultimate beneficiaries of UPF.

UPF 1.0 standard from Accellera is accessible to everyone. The latest version of the standard can be downloaded from Accellera’s website at: http://www.accellera.org.

UPF is a key technology donation to the proposed IEEE 1801 standard, which is currently being developed by the IEEE Working Group for Design and Verification of Low Power Integrated Circuits. For more details on the IEEE P1801 Working Group activity, you can sign up for P1801 email group by sending an email to owner-p1801@eda.org.