USB 3.0 Architecture 1

A.D Usama Bin NajamResearch Associate

Muhammad UmerResearch Assistant

June, 2009

Centre of Excellence for FPGA/ASIC ResearchNUST School of Electrical Engineering and Computer Sciences

Motivation for USB 3.0

Overview

USB 3.0 System Description

Architectural Overview Architectural Overview

Super Speed Communication Layers

Super Speed Power Management

Comparison b/w Super Speed USB and USB 2.0

Conclusion

References

3USB 3.0 Architecture

To increase data transfer rate

To decrease power consumption

To enable Swift and seamless integration of USB 3.0 into various devices

4USB 3.0 Architecture

On Nov 17th,2008 USB 3.0 specifications were released by USB 3.0 promoter

Group

USB 3.0 is also known as Super Speed USB (SS USB)

10 times performance increase over USB 2.0 (480 Mbps) 10 times performance increase over USB 2.0 (480 Mbps)

Supports transfer rates up to 5 Gbps (600 GBps)

Provide better power management features

Provides backward compatibility with earlier standards

Supports127 devices per host controller/ Bus

Full support for real-time data for voice, audio, and video

5USB 3.0 Architecture

USB 3.0 uses Dual Bus Architecture

Provides concurrent operation of SS and non-SS info exchange

Electrically/Mechanically backward and forward compatibleforward compatible

Main Architectural components include:

USB 3.0 interconnect

USB 3.0 devices

USB 3.0 host

6USB 3.0 Architecture

USB Interconnect

The manner in which USB devices are connected to and communicate with the host over the SS bus

Includes:Includes:

Bus Topology: Connection model b/w Usb Devices and the host

Inter-layer Relationship: Usb tasks performed at each layer in the system and

its relationship

Data Flow Models: Information exchange b/w host and devices over the USB

USB Schedule: Scheduling of shared interconnects in order to support isochronous

data transfer and to eliminate arbitration overheads

7USB 3.0 Architecture

USB Host

There is only one host in any USB system, which acts as a source or sink of

information

The USB interface to the host system is referred to as the Host Controller

A root hub is integrated within the host system to provide one or more

attachment points

Manages the SS bus and all devices connected to it

Manages Control and Data flow between host and USB devices

USB 3.0 Architecture 8

USB Devices

Includes Hubs, peripheral devices, functions

Act as a source or sink of information exchange

Each device supports one or more pipes through which the host may

communicate with the device

Simultaneous operation of SS and non-SS modes is not allowed for peripheral

devices

9USB 3.0 Architecture

USB 3.0 hub architecture includes logical USB

2.0 and Super Speed USB hubs

USB 3.0 hub provides bus expansion upto 5 levels of hubs and 127 devices

Different kinds of Hubs include:

Root port hubs: Directly attached to the USB Host Controller. Hub power is derived from the same source as

the Host Controller

Bus-powered hubs: Draw all of their power for any internal functions and

downstream

Self-powered hubs: Separate power supply available

10USB 3.0 Architecture

USB 3.0 Architecture 11

12USB 3.0 Architecture

13USB 3.0 Architecture

HOST HUB DEVICE

14USB 3.0 Architecture

The physical layer defines the PHY portion of a port andthe physical connection between a downstream port andthe upstream port on a device (chip to Chip delivery)

Unidirectional differential link Each differential link is initialized by enabling its receiver

termination.

Transmitter managing the status of the receiver termination

15USB 3.0 Architecture

Low frequency periodic signal(LFPS)

Spread Clock CDR

8b/10b encode/ decode8b/10b encode/ decode

Scrambled/Descrambled

Elasticity Buffer/skips

USB 3.0 Architecture 16

Low frequency periodic signal(LFPS) Used for signal initialization and power management information

Spread Clock CDR Each PHY has its own clock domain with spread spectrum clocking

(SSC) modulation

No reference clock Synchronization between transmitter & receiver clock by phase locking

USB 3.0 Architecture 17

8b/10b encode/ decode The transmitter encodes data and control characters into symbols using

8b/10b code

Control symbols are used to achieve byte alignment and are used for framing data and managing the linkframing data and managing the link

Scrambler/Descrambler Physical layer receive 8 bit data from the link layer and scrambles the

data to reduce EMI emissions.

Encodes 8 bit scrambled data into 10 bit symbols for transmission over the physical connection

Receiver decode 10 bit symbols and descrambles, producing 8 bit data and sent to link layer for further processing

18USB 3.0 Architecture

HOST HUB DEVICE

19USB 3.0 Architecture

The link layer provides the link connectivity Packets are prepared in the link layer to carry data and

control information between the host and a device Packet framing Link command definition and usage Link command definition and usage Link initialization and flow control Link power management Link error rules /recovery Resets LTSSM specifications

20USB 3.0 Architecture

Packets delimiters Packets delimiters describes packet types, packet structures, and CRC

requirements for each packet i-e LMP, TP, ITP & DP e.t.c

Link Commands Link Commands The link command section defines special link command structures,

that control various functionalities at the link layer

Link Control/Management Power management, Link level data integrity, flow control and error

control

21USB 3.0 Architecture

HOST HUB DEVICE

22USB 3.0 Architecture

Defines the end to-end communication rules between a host and device

Protocol layer provide uni cast communication between host and deviceand device

Super Speed protocol provides for application datainformation exchanges between a host and device end point

It is host directed protocol which means the host determines when application data is transferred between host and device

23USB 3.0 Architecture

The protocol layer supports reliable delivery of data packets via explicit acknowledgement packets and retransmission of lost or corrupt data

The protocol layer allows efficient bus utilization by concurrently transmitting and receiving over the link.

The protocol provides flow control

24USB 3.0 Architecture

Notifications

Transactions

Transaction packetsTransaction packets

Data Packets

Link Management Packets

25USB 3.0 Architecture

Super Speed power management at distinct areas in the bus architecture, link , device and function

Device sends asynchronous ready notifications to the host Packets are routed , allowing links that are not involved in data Packets are routed , allowing links that are not involved in data

communication to transition to and/or remain in a low power state Packets that encounter ports in low power states cause those ports to

transition out of the low power state with indications of the transition event

Multiple host or device driven link states with progressively lower power at increased exit latencies

26USB 3.0 Architecture

Logical Idle U0 Period of one or more symbols period when no information is being

transferred on the link

U1/U2 entry flow Low power states Either a downstream port or upstream port can initiate request U1/U2 link state is accomplished using link commands

U3 entry flow Suspended states (device disconnected) Only downstream port can initiate U3 entry Upstream port cannot reject U3 request

27USB 3.0 Architecture

Link Layer Power Management

28USB 3.0 Architecture

USB 3.0 Architecture 29

Data Rate

Super speed USB supports data rates upto 5 Gbps (600 MBps)

USB 2.0 supports data rates upto

480Mbps (high speed USB)

12 Mbps (full speed USB)

1.5 Mbps (low speed USB)

30USB 3.0 Architecture

Data Interface and Primary Conductors

USB 2.0 Cable USB 3.0 Cable Half Duplex two-wire differential signaling

Unidirectional Data flow

Power Pair: VBUS and GND

Signal Pair (1 Twisted pair):

D+ and D-

Dual Simplex, four wire differential signaling

Simultaneous bi-directional data flows

Power Pair: VBUS and GND

Signal Pairs (3 Twisted pairs):

D+ and D-SSTX+ and SSTX- (transmit path)SSRX+ and SSRX- (Receive Path)

31USB 3.0 Architecture

Super Speed USB:

Uses host directed protocol (host determines when to transfer application data) Asynchronous traffic flow (Device can asynchronously request service from host)

Bus Transaction Protocol

Asynchronous traffic flow (Device can asynchronously request service from host) Packet traffic is explicitly / directly routed (Unicast, not broadcast)

USB 2.0:

Uses host directed protocol Polled traffic flow (Host use polling to request info from the endpoints) Packet traffic is broadcasted to all devices

32USB 3.0 Architecture

Power Management

Super Speed USB:

Multi-level link power management supporting idle, sleep, and suspend states

USB 3.0 Architecture 33

Multi-level link power management supporting idle, sleep, and suspend states

Link-, Device-, and Function-level power management

USB 2.0:

Port-level suspend with two levels of entry/exit latency

Device-level power management

Bus Power

Super Speed USB:

Increased supply budgets for devices operating at Super Speed 50% increase for unconfigured power 80% increase for configured power

USB 3.0 Architecture 34

USB 2.0:

Support for low/high bus-powered devices

Super Speed USB:

keeps all the four USB 2.0 transfer types with SS constraints

Bulk transfer has streams capability

Data Transfer types

Bulk transfer has streams capability

USB 2.0:

Four transfer types include: Control, Bulk, Interrupt, Isochronous

USB 3.0 Architecture 35

USB 3.0 compliant devices will bring a revolution in the industry in terms of speed and power efficiency

Backward compatibility will help in reducing the effects to end users Backward compatibility will help in reducing the effects to end users

USB 3.0 Architecture 36

1. USB 3.0 Specifications (Revision 1.0)

2. USB 2.0 Specifications (Revision 2.0)

3. USB Complete Developers Guide, Book3. USB Complete Developers Guide, Book

4. http://www.usb.org

5. www.wikipedia.com

USB 3.0 Architecture 37

Questions????

USB 3.0 Architecture 38

Questions????