USB Link Layer Protocol Sunggu Lee Department of Electrical Engineering Pohang University of Science...

USB Link Layer ProtocolUSB Link Layer Protocol

Sunggu LeeDepartment of Electrical Engineering

Pohang University of Science and Technology (POSTECH)

(Assistants: Young-Wook Park, Jung-Hwa Shim, Dong-Hak Pyo, Joon-Hyuk Kang)

2003-05-29 POSTECH CA Lab 2/59

Outline of TutorialOutline of Tutorial

Tutorial Scope and OverviewUSB Communication Protocol

– The Big Picture– Initialization Steps– Packet Transfers

Hardware Implementation Examples– Protocol Analyzer– USB Device Interface


Scope and OverviewScope and OverviewUSB Communication ProtocolUSB Device Interface Circuit

USB2.0USB2.0PCPC

DeviceDeviceHardwareHardware

USB2.0USB2.0TransceiverTransceiver

USB2.0USB2.0TransceiverTransceiver

SerialSerialInterfaceInterfaceEngineEngine

SerialSerialInterfaceInterfaceEngineEngine

Device Device Specific Specific

LogicLogic

Device Device Specific Specific

LogicLogic

TransceiverTransceiver

Peripheral ComponentPeripheral Component

Custom ASICCustom ASIC

Physical LayerPhysical LayerPhysical LayerPhysical Layer Link LayerLink LayerLink LayerLink Layer


USB Communication USB Communication ProtocolProtocol

Initialization Phase– Device identifies itself to PC host– PC host establishes communication channel

with device Configuration Uses control transfers

Data Communication Phase– Interrupt transfer (e.g., keyboard)– Bulk transfer (e.g., printer, hard disk)– Isochronous transfer (e.g., speaker)


The Big PictureThe Big Picture

Primary H/W and S/W Elements– USB H/W

USB Host Controller/Root Hub USB Hub USB Device

– USB S/W USB Device Driver

– Driver dedicated to specific device (or class of devices)

USB Driver– Driver dedicated to support of USB protocol at host

Host Controller Driver


Communication FlowCommunication Flow

[Anderson 1997]

Host S/W

Host H/W Device H/W

DeviceS/W or H/W

Example: Olympus Digital Camera S/W


[Anderson 1997]

Example ofUSB Host andDeviceConnections

USBConnections


USB Device DriverUSB Device Driver

Issues requests to the USB driver via IO Request Packets (IRPs)– IRPs initiate transfer to/from device– Examples

Olympus digital camera S/W initiates bulk transfer with an IRP and a memory buffer

USB keyboard driver initiates interrupt transfer with an IRP and a memory buffer (for sending the depressed “key” data)


USB Driver (typically USB Driver (typically shipped with O.S.)shipped with O.S.)

Knows characteristics of USB target device and how to communicate with device via USB– Based on device descriptors passed to it

during device configuration Upon receiving an IRP,

– USB driver organizes request into several transactions to be executed during a series of 1 ms. frames (full-speed)

2003-05-29 POSTECH CA Lab 10/59

USB Host Controller DriverUSB Host Controller Driver

Schedules transactions by building transaction lists

Executes transaction lists at 1 ms intervals (low, full-speed) or 125 s intervals (high-speed) – Each 1 ms frame begins with a start-

of-frame (SOF) transaction followed by the serial broadcast of transactions in the frame

2003-05-29 POSTECH CA Lab 11/59

USBSoftware

Allcommunicationoccurs viapackets

[Anderson 1997]

2003-05-29 POSTECH CA Lab 12/59

USB Host Controller and USB Host Controller and Root HubRoot Hub

All communications on USB originates at the host under S/W control

Host Controller– Responsible for generating the

transactions scheduled by host S/WRoot Hub

– Provides connection points for USB devices

2003-05-29 POSTECH CA Lab 13/59

Host ControllerHost Controller

Transfer descriptors (data structures built by host controller driver S/W) contain all info. needed to generate transactions– USB device address– Type of transfer– Direction of transfer– Address of device driver’s memory buffer

2003-05-29 POSTECH CA Lab 14/59

Write Transfer– Reads data from memory buffer

(location supplied by USB device driver)– Performs parallel to serial conversion of

data– Creates the USB transaction– Forwards it to the root hub to send over

the USB “bus”NOTE:

– Error checks performed by USB root hub and devices during each transaction

2003-05-29 POSTECH CA Lab 15/59

Read Transfer– Host controller builds read transaction– Sends read transaction to root hub– Root hub transmits read transaction over

USB– Target device recognizes that it is being

addressed, and responds with data– Root hub forwards data to host controller– Host controller: serial to parallel conversion– Host controller transfers data to device

driver’s memory buffer

2003-05-29 POSTECH CA Lab 16/59

Root HubRoot Hub

Every USB transaction originates at the root hub (H/W 측면에서 )

Root Hub Functions:– Controls power to its USB ports– Enables and disables ports– Recognizes devices attached to each port– Sets and reports (when polled by host S/W)

status events (e.g., errors) associated with each port

2003-05-29 POSTECH CA Lab 17/59

USB HubUSB Hub

Permits extension of USB system by providing one or USB ports

Can be embedded into a device or provided as a separate device

Basic Functions– Hub controller USB interface

function– Repeater forwards bus traffic

2003-05-29 POSTECH CA Lab 18/59

USB DevicesUSB Devices

Contain descriptors that specify the devices’ attributes and characteristics– Device Framework

Types– High-Speed Devices (480 Mbps)

Indicated by special initial handshaking sequence Supported in USB2.0 spec. only

– Full-Speed Devices (12 Mbps) Indicated by initial values of D+ = high and D- =

low

2003-05-29 POSTECH CA Lab 19/59

– Low Speed Devices (1.5 Mbps) Indicated by initial values of D+ = low

and D- = high Only sees USB transactions that follow a

special preamble packet Low-speed hub ports remain disabled

during high-speed and full-speed transactions

Hubs enable their low-speed ports after detecting a preamble packet

2003-05-29 POSTECH CA Lab 20/59

Comparison of USB1.1 and Comparison of USB1.1 and USB2.0USB2.0

Item USB1.1 USB2.0

Signal amplitude 3.3V 3.3V / 400mV

Transfer rate FS(12Mbps), LS(1.5Mbps) HS(480Mbps)

Idle stateJ state(D+ =High, D- =Low)

SEO(Single Ended 0)(D+ = D- =Low)

Sync bit 8 개의 KJKJKJKJ 32 개의 KJKJ….KJKK

EOP SE0 + SE0 + J 01111111

Connection detectionFS device : D+ line pull upLS device : D- line pull up

Chirp handshake

Token PID SOF, SETUP, IN,OUT

Data PID DATA0, DATA1 DATA0,DATA1, DATA2,MDATA

Handshake PID ACK, NAK, STALL ACK, NAK,STALL,NYET

Special PID PRE PRE,ERR,SPLIT,PING

Frame 1ms 125s

Control data 8,16,32,64 bytes 64bytes

Bulk data 8,16,32,64 bytes 512bytes

Interrupt data 1to 64 bytes 1 to 1024 bytes

Isochronous data 1 to 1023 bytes 1 to 1024 bytes

2003-05-29 POSTECH CA Lab 21/59

USB Communications USB Communications ModelModel

USB devices are not mapped into memory or I/O space, and do not use IRQ lines or DMA channels

All transactions originate from the host system

System resources required by USB:– Memory locations used by USB system S/W– Memory and/or I/O address space and IRQ

line used by USB host controller

2003-05-29 POSTECH CA Lab 22/59

Communications FlowCommunications Flow

USB client initiates a transfer when it calls USB system S/W– Supplies memory buffer (address)

Each transfer between a given endpoint (register within a USB device) and the client driver (S/W in the host system) occurs via a communication pipe (logical communication channel) that USB system S/W establishes during device configuration

2003-05-29 POSTECH CA Lab 23/59

USB system S/W splits the client’s request into individual transactions consistent with device’s requirements– Requests passed to USB host controller

driver, and then, … (same as earlier info)Key information contained within a

transfer descriptor include– Address of target USB device– Type of transfer to be performed– Size of the data packet– Location of the client’s memory buffer

2003-05-29 POSTECH CA Lab 24/59

Host controller (H/W) may have registers that are mapped into the processor’s I/O or memory address space– These registers control the operation of the

host controller Loaded by host controller driver (S/W)

Host controller communicates with endpoints in USB devices– Endpoints correspond to separate

communication buffers (registers)– Unique address assigned to each endpoint

Address = endpoint number and direction Direction is always from the host’s viewpoint

2003-05-29 POSTECH CA Lab 25/59

EndpointsEndpoints

Endpoint 0– Initial default endpoint used– Control endpoint

Must transfer data in both directions Thus, consists of Endpoint 0 IN, Endpoint 0 OUT

Full-speed devices– Can have up to 30 additional endpoints

Low-Speed devices– Limited to 2 additional endpoints

2003-05-29 POSTECH CA Lab 26/59

Transaction TypesTransaction Types

Type Source of Data

Transfers Supported

Contents

IN Device All Data

OUT Host All Data

SETUP Host Control A request

2003-05-29 POSTECH CA Lab 27/59

USB PipesUSB Pipes

Before a transfer can occur, the host and device must establish a pipe

USB pipe: an association between a device’s endpoint and host controller software– Not a physical object

Pipes established on device establishment

Default control pipe uses endpoint 0

2003-05-29 POSTECH CA Lab 28/59

[Anderson 1997]

MemoryAddressSpace

I/OAddressSpace

2003-05-29 POSTECH CA Lab 29/59

USB Device InitializationUSB Device Initialization

Enumeration Steps– User plugs device into USB port

May be connected to a root hub or a hub Hub provides power to the port Device changes to “powered” state

– Hub detects device Monitors D+ and D- (with 15-Kohm pull-

down resistors) lines– Device pulls D+ high (high- or full-speed) or D-

high (low-speed)

2003-05-29 POSTECH CA Lab 30/59

Host learns of new device– Hub uses its interrupt pipe to report

events at the hub Hub sends an event report to host Host sends hub Get_Port_Status request Hub sends reply to host

Hub detects device speed– Low-speed: D+ low, D- high– Full-speed: D+ high, D- low– High-speed: initially recognized as full-

speed device D+ high, D- low

2003-05-29 POSTECH CA Lab 31/59

Hub resets device– Host controller sends hub Set_Port_Feature

request– Hub resets device (>= 10 msec)

D+ low, D- low for >= 10 msec– Hub sends reset only to new device

Host learns if full-speed device supports high-speed communication– Handshaking using Chirp K and Chirp J duri

ng reset

2003-05-29 POSTECH CA Lab 32/59

Hub establishes signal path between device and USB bus– Host verifies that device has exited reset

state by sending Get_Port_Status request

– When hub removes reset, device is in Default state

Host sends Get_Descriptor request– To learn maximum packet size of default

pipe (device address 0, endpoint 0)Host assigns an address to device

– Sends Set_Address request

2003-05-29 POSTECH CA Lab 33/59

Host learns about device’s abilities– Host sends Get_Descriptor to new address– Device returns entire device descriptor– Host requests >= 1 configuration descriptor

s using Get_Config_Descriptor Sends request twice (once to get size)

– Device returns configuration descriptorsHost assigns and loads device driver

– Windows matches info in system’s INF files with info retrieved from device

2003-05-29 POSTECH CA Lab 34/59

Host’s device driver selects a configuration– Device driver requests a configuration

using a Set_Configuration request with desired configuration number

– Device read request and sets its configuration

Device in “configured” state Device’s interfaces enabled

– Host assigns drivers for the interfaces– Device ready for use

2003-05-29 POSTECH CA Lab 35/59

High-Speed Chirp High-Speed Chirp SequenceSequence

J and K defined with respect to initial default values of D+ and D-– For full, high-speed: J = (D+ high, D- low)

and K = (D+ = low, D- = high)– For low-speed: J = (D+ low, D- high) and K =

(D+ = high, D- = low) Chirp Sequence

– Sequence of J and K states (Chirp J, Chirp K)– Require KJKJKJKJ (8 states) to detect high-

speed

2003-05-29 POSTECH CA Lab 36/59

High-Speed Device High-Speed Device DetectionDetection

[Kawasaki 2002]

2003-05-29 POSTECH CA Lab 37/59

DescriptorsDescriptors

Data structures (formatted blocks of information) that enable host to learn about device

Types– Device descriptors– Configuration descriptors– Interface descriptors– Endpoint descriptors

2003-05-29 POSTECH CA Lab 38/59

Device DescriptorDevice Descriptor

[Axelson 2001]

2003-05-29 POSTECH CA Lab 39/59

Configuration DescriptorConfiguration Descriptor

[Axelson 2001]

2003-05-29 POSTECH CA Lab 40/59

Interface DescriptorInterface Descriptor

[Axelson 2001]

2003-05-29 POSTECH CA Lab 41/59

Endpoint DescriptorEndpoint Descriptor

[Axelson 2001]

2003-05-29 POSTECH CA Lab 42/59

Control TransfersControl Transfers

Setup Stage– SETUP packet for “requests”

Uses 5-bit CRC for error checking

Data Stage– DATA0, DATA1, DATA2, MDATA packet

Status Stage– ACK packet– NAK packet– Etc.

2003-05-29 POSTECH CA Lab 43/59

Standard RequestsStandard Requests

Get_Status Clear_Feature Set_Feature Set_Address Get_Descriptor Set_Descriptor Get_Configuration Set_Configuration Get_Interface Set_Interface Synch_Frame

2003-05-29 POSTECH CA Lab 44/59

Data TransfersData Transfers

IN packet requests that device send requested data to host

OUT packet requests that device receive data from host

Data packet sent following IN or OUT– DATA0, DATA1, DATA2, MDATA– Toggle between different types for

sequencing and error control– Uses 16-bit CRC for error checking

2003-05-29 POSTECH CA Lab 45/59

Error CheckingError Checking

Toggling between DATA0 and DATA1– Can be used to detect missed packets

CRC– Cyclic Redundancy Check– Based on LFSR (Linear Feedback Shift

Register) structure Based on theory of division of polynomials

2003-05-29 POSTECH CA Lab 46/59

Packets (1/2)Packets (1/2) Packets

– Sync – 32bit– Packet ID –8bit– Packet information-device address, endpoint

number,frame number,data– CRC – 5bit or 16bit– EOP – 8bit

Token Packets– SOF, SETUP, OUT, IN

DATA Packets– DATA0, DATA1, DATA2, MDATA

2003-05-29 POSTECH CA Lab 47/59

Packets (1/2)Packets (1/2)

Handshake Packets– ACK– NAK– STALL

Special Packets– PRE– ERR– SPLIT– PING

2003-05-29 POSTECH CA Lab 48/59

Example Setup Transaction Host sends 8-byte SETUP packet to Endpo

int0 to which device responds.

Sequence

Stage Packet Contents# of byte

sSource

Setup Token

Setup PID, address, endpoint, CRC5

3 HOST

DataDATA0 PID, 8 bytes

data, CRC1611 HOST

Status ACK 1 DEVICE

2003-05-29 POSTECH CA Lab 49/59

Control TransferControl Transfer

Setup Phase

[Hyde 1999]

2003-05-29 POSTECH CA Lab 50/59

Control Read Data Phase

[Hyde 1999]

2003-05-29 POSTECH CA Lab 51/59

Control Write Data Phase [Hyde 1999]

2003-05-29 POSTECH CA Lab 52/59

Handshake Phase of Control Transfer

[Hyde 1999]

2003-05-29 POSTECH CA Lab 53/59

High-Speed TransfersHigh-Speed Transfers

HS Isochronous Transfer– Packet size = 1024byte– Maximum bandwidth 57MB/s ( 7frame

)HS Interrupt Transfer

– Packet size = 1024byte– Maximum bandwidth 53MB/s

( 13frame )

2003-05-29 POSTECH CA Lab 54/59

Bulk IN Transaction Transaction for transferring data from DEV

ICE to HOST

Sequence

Stage Packet Contents # of bytes

Source

IN Token

IN PID, address, endpoint, CRC5

3 HOST

Data(1/0)

DATA PID, N data packet, CRC16, or NAK

or STALLN+3 DEVICE

Status ACK 1 HOST

2003-05-29 POSTECH CA Lab 55/59

Bulk OUT Transaction Transaction for transferring data from HOS

T to DEVICE

Sequence

Stage Packet Contents# of byte

sSource

IN Token

OUT PID, address, endpoint, CRC5

3 HOST

Data(1/0)

DATA PID, N data packet, CRC16

N+3 HOST

Status ACK or NYET or NAK 1 DEVICE

2003-05-29 POSTECH CA Lab 56/59

USB Implementation USB Implementation ExamplesExamples

USB1.1 Protocol Analyzer– Developed in 2001 to demonstrate

proper understanding of USB protocol– Simple version of commercial USB

protocol analyzer HW/SW kitsUSB2.0 Device Interface

– A custom device developed for demonstration purposes

– A “pixel inverter” device

2003-05-29 POSTECH CA Lab 57/59

Protocol Analyzer Block Diagram

ComputerUSB

Camera

Packet Analyzer

NRZI Decoder/

Bit destuffer

Transaction & Packet Type,Error Status, Data

(monitored output)

(Display on PC monitor)

Protocol Analyzer

2003-05-29 POSTECH CA Lab 58/59

Output from Implemented Circuit

Time Step Type Contents CRC Check

0 PACKET SETUP1 DATA 0x22 DATA 0x8 NORMAL

3 PACKET DATA04 DATA 0x80. . . . . .14 DATA 0x94 NORMAL

15 PACKET ACK

2003-05-29 POSTECH CA Lab 59/59

ReferencesReferences

Anderson, D., Universal Serial Bus System Architecture, Addison-Wesley, Reading, 1997.

Axelson, J., USB Complete, 2nd Ed., Lakeview Research, Madison, 2001.

Hyde, J., USB Design By Example, Wiley Computer Publishing, New York, 1999.

Kawasaki Microelectronics, Inc., KL5KUSB200/1-USB2.0 Compliant Transceiver Chip Datasheet, 2002.

www.usb.org, Universal Serial Bus Specification, 2000.

Date post:	11-Jan-2016
Category:	Documents
Upload:	julia-robertson
View:	213 times
Download:	0 times

USB Link Layer Protocol Sunggu Lee Department of Electrical Engineering Pohang University of Science...

Documents