User guide --dadda16.pdf

7/28/2019 User guide --dadda16.pdf

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.ADDA16

Doc #1.0

User's Guide

Digital Signalprocessing Technology

Norbert Nlker & Adolf Klemenz GbR

Gelderner Strae 36

D - 47647 Kerken

phone +49 (0) 2833 / 570 977

fax +49 (0) 2833 / 33 28

email [email protected]

www http://www.dsignt.de


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D.Module.ADDA16 User's Guide Revision History

D.SignT 2004 Doc #1.0 1

D.Module.ADDA16 Revision History

1.0 July 2004


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D.Module.ADDA16 User's Guide Contents

D.SignT 2004 Doc #1.0 2

1 INTRODUCTION............................................................................................. 4

2 DSP INTERFACE............................................................................................ 6

2.1 Address Decoding..............................................................................6

2.2 Registers ...........................................................................................8

2.2.1 FS Register............................................................................................ 9

2.2.2 CONFIG Register................................................................................... 9

3 A/D CONVERTER......................................................................................... 11

3.1 Analog Inputs................................................................................... 11

3.2 Sampling Clock................................................................................ 12

4 D/A CONVERTER......................................................................................... 14

4.1 DAC Updates (LDAC) ......................................................................17

4.2 Analog Outputs................................................................................ 18

5 POWER SUPPLY.......................................................................................... 19

6 PINOUT........................................................................................................ 20

7 MECHANICS ................................................................................................ 22

8 ELECTRICAL CHARACTERISTICS.............................................................. 23


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D.Module.ADDA16 User's Guide Contents

D.SignT 2004 Doc #1.0 3

List of Tables and Figures:

Table 2-1 DSP Bus Interface Signals................................................................. 6

Table 2-2 Address Decoding: 64K bank select ................................................... 7

Table 2-3 Address Decoding, 16 word sub-bank select ...................................... 7

Table 2-4 ADDA16 Registers............................................................................. 8

Table 3-1 Analog Input Signals........................................................................ 11

Table 3-2 Sampling Clock Signals................................................................... 13

Table 4-1 Analog Output Signals ..................................................................... 18

Table 6-1 D.Module.Connector, blank fields are not connected ........................ 20

Table 6-2 Analog Input Connector Pinout ........................................................ 21

Table 6-3 Analog Output Connector Pinout...................................................... 21

Figure 1-1 D.Module.ADDA16 Block Diagram..................................................... 4

Figure 1-2 Location of Jumpers.......................................................................... 5

Figure 3-1 Sampling Clock Circuit .................................................................... 12

Figure 4-1 DAC Interface.................................................................................. 14

Figure 5-1 D.Module.ADDA16 Mechanics ......................................................... 22


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D.Module.ADDA16 User's Guide Introduction

D.SignT 2004 Doc #1.0 4

1 Introduction

The D.Module.ADDA16 is a 16 bit, 250 KSPS, 4-channel A/D and D/A converter

board, suitable for the D.Module family of DSP Computer Modules.

Four A/D channels are converted synchronously using Successive Approximation

Converters (SAR). This architecture provides a very short delay from sampling to

availability of the digital output word, and is best suited for control loops, where

any delay will result in increased dead time, complicating the control algorithm.

Synchronous sampling preserves the phase information of the input channels.

The analog inputs are high-impedance differential inputs, but can also be driven

from single-ended sources by grounding the IN- input.

The D/A converters are followed by a second order smoothing filter and provide a

single-ended bipolar output. The DACs can be updated synchronously with the

ADC sampling frequency, or operate in free running mode, i.e. the output is up-

dated immediately after a write to the corresponding DAC. A third mode com-

bines unsynchronized writes to the DACs with simultaneous update of 2, 3 ,or all

four channels.

+

-AD7663

ADC0 In+

ADC0 In-

+

-AD7663

ADC1 In+

ADC1 In-

+

-AD7663

ADC2 In+

ADC2 In-

+

-AD7663

ADC3 In+

ADC3 In-

Vref

CNVST

AD5544

DAC0

DAC1

DAC2

DAC3

Vref

LDAC(DAC Update)

LDAC Config

FS_Register

int. Clock

EXT_CLKIN

EXT_CLKOUT

progr.Divider

ADC

and

DAC

Registers

Figure 1-1 D.Module.ADDA16 Block Diagram


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D.Module.ADDA16 User's Guide Introduction

D.SignT 2004 Doc #1.0 5

AB

C

1 3216

U

V

T

F

G

H

I

J

K

L

M

N

O

P

JPGND

JPA4

JPA5

JPA16

JPA17

JPA18

Figure 1-2 Location of Jumpers

JPGND connects the analog to the digital ground. It is closed by default using a 0

ohms resistor. If your system already provides a AGND-DGND connection you

must open this jumper to avoid a GND loop.

JPA4,5,16,17, and 18 select the ADDA16 base address.


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D.Module.ADDA16 User's Guide DSP Interface

D.SignT 2004 Doc #1.0 6

2 DSP Interface

The D.Module.ADD16 is memory-mapped to the DSP module's IOSEL memory

space. It occupies a contiguous address space of 16 addresses. The base ad-

dress is determined by five address jumpers on the board.

The data bus is connected to the upper 16 data bits of the DSP. Data format is

2's complement, hence the sign bit (MSB) of the converters and the DSP sign bit

match, independent of the DSP data bus width.

Two interrupt outputs can be configured to request exception handling for ADC or

DAC from the DSP. Many DSP boards also allow to use these interrupts as DMA

trigger events for background data acquisition with minimum DSP load.

Pin Signal Type Comment

U2 nRD input read strobe, active low

U3 nINT0 output, o.d. Interrupt line 0 to DSP, active low

U4 nINT1 output, o.d. interrupt line 1 to DSP, active low

U5 nWR input write strobe, active low

U6 BUSCLK input DSP external bus clock

U7 nRESET input reset input, active low

U8 nIOSEL input DSP memory area select signal

U9..U14 A0..A5 input DSP address bus

U15..U30 D15..D31 bidir, hi-z DSP data bus

V12..V14 A16..A18 input DSP address bus

Type: o.d = open drain output, hi-z = high impedance, bidir = bidirectional

Table 2-1 DSP Bus Interface Signals

2.1 Address Decoding

Five address jumpers on the D.Module.ADDA16 allow to select the base address

of the board. If a jumper is closed, the corresponding DSP address line must be

'1' to decode the board, if a jumper is open, the corresponding address line must

be '0'. jumper.

Jumper JPA18 .. JPA16 decode a 64K address block, jumper JPA5 and JPA4

decode a 16 words sub-block. This allows to select one of 32 possible address

blocks.


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D.SignT 2004 Doc #1.0 7

The following tables shows the possible address offsets from IOSEL base ad-

dress. Please note that Texas Instruments C6000 processors use a different

addressing scheme (byte addressing), and always drive A18 high in IOSEL

memory area.

64 K Bank Select Base Address

JPA18 JPA17 JPA16 C6000 DSP

Modules

other

open open open not possible nIOSEL + 0

open open closed nIOSEL + 0x01.0000

open closed open nIOSEL + 0x02.0000

open closed closed nIOSEL + 0x03.0000closed open open nIOSEL + 0 nIOSEL + 0x04.0000

closed open closed nIOSEL + 0x04.0000 nIOSEL + 0x05.0000

closed closed open nIOSEL + 0x08.0000 nIOSEL + 0x06.0000

closed closed closed nIOSEL + 0x0C.0000 nIOSEL + 0x07.0000

Table 2-2 Address Decoding: 64K bank select

Inside this 64 K block, address jumpers A4 and A5 allow to select one 16 word

area out of a 64 word block:

16 Word Sub-Bank Select Base Address Offset

JPA5 JPA4 C6000 DSP Modules other

open open 0x00 0x00

open closed 0x40 0x10

closed open 0x80 0x20

closed closed 0xC0 0x30

Table 2-3 Address Decoding, 16 word sub-bank select

The default settings are JPA18 closed, JPA17 and JPA16 open, JPA5 and JPA4

open, hence the factory setting base address is IOSEL + 0x00000 on C6000 DSP

modules, and IOSEL + 0x40000 on other DSP modules.


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D.SignT 2004 Doc #1.0 8

2.2 Registers

Six registers provide access to the A/D and D/A converters and to the board con-

figuration. Address Offsets in () brackets are valid for C6000 DSPs:

Offset Register Width Comment

0x00 (0x00) ADDA0 16 bits read: ADC channel 0write: DAC channel 0

0x01 (0x04) ADDA1 16 bits read: ADC channel 1write: DAC channel 1

0x02 (0x08) ADDA2 16 bits read: ADC channel 2

write: DAC channel 20x03 (0x0C) ADDA3 16 bits read: ADC channel 3

write: DAC channel 3

0x04 (0x10) FS 8 bits read/write: sampling frequencyselection

0x05 (0x14) CONFIG 8 bits read/write: configuration register

Table 2-4 ADDA16 Registers

The 16 bit wide ADDA0..ADDA3 registers provide direct access to the A/D and

D/A converters. Data from the A/D converters is serially transmitted to the bus

interface. A shift register for each ADC performs serial-parallel conversion, and a

state machine starts ADC readout as soon as the ADC signals conversion com-

plete. This scheme minimizes system noise, especially during the ADC sampling

period. The ADC interface is buffered, hence data can be read while the next

conversion result has already started to shift in. An interrupt is generated as soon

as the ADC data is copied from the shift register to the buffer.

Data is written to the D/A converters via a serial interface too. The bus interface

provides parallel to serial conversion. The DAC interface is buffered, but only one

level deep. If the first DAC has been written, the data is immediately copied to the

shift register and transferred to the DAC. Now the second DAC value can be

written. This data is held in the buffer and not copied to the shift register before

the first DAC transmission is completed. During this time the buffer is not avail-

able for new data, hence you have to wait for the first transmission to finish be-

fore the third DAC value can be written. Each time the DAC buffer is ready for a

new transfer, an interrupt is generated. You may also poll the DAC_READY flag

in the CONFIG register to determine if the interface is ready to accept new data.


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D.SignT 2004 Doc #1.0 9

For a detailed description of DAC access methods please refer to chapter 4, D/A

Converter.

The FS register allows to select the sampling frequency, either generated on-

board via a programmable divider, or an external clock fed to EXT_CLKIN.

The CONFIG register selects the interrupt mapping and the D/A converter update

scheme (LDAC). The sampling clock output EXT_CLKOUT can be enabled for

cascading multiple ADDA16 boards, or synchronizing other peripherals, and the

status of the D/A converter data transfer can be read.

2.2.1 FS Register

Bit 15..8 undefined on read operations, don't care on writes

Bit 7. 0 ADC Sampling Frequency

0x00 selects external sampling clock provided from EXT_CLKIN

0x0F .. 0xFF select an internally generated sampling clock. The

clock is generated from a 4 MHz quarz oscillator by this equa-

tion: fs = 4MHz / (FS_REG + 1)

values < 0x0F result in a sampling clock > 250 kHz and are not

supported.

The reset value of this register is 0x00

2.2.2 CONFIG Register

Bit 15..8 undefined on read operations, don't care on writes

Bit 7 write: EXT_CLKOUT_ENABLE

a 1 written to this bit will enable the EXT_CLKOUT output, a 0

will disable this output and put it into high impedance.

read: DAC_READY

a 1 signals the DAC buffer is ready to accept new data, if 0, the

DAC buffer is full and new data cannot be accepted.


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D.SignT 2004 Doc #1.0 10

Bit 6, 5 read/write: INT1_DAC, INT1_ADC

these bits determine the nINT1 interrupt output usage:

00 - not used, high impedance

01 - ADC interrupt10 - DAC interrupt

11 - not allowed

Bit 4, 3 read/write: INT0_DAC, INT0_ADC

these bits determine the nINT0 interrupt output usage:

00 - not used, high impedance

01 - ADC interrupt10 - DAC interrupt

11 - not allowed

Bit 2 .. 0 read/write LDAC

these bits determine the DAC update mode:

000 - DAC is updated following each write to any DAC

001 - DAC update after writing to DAC 1



100 - DAC update synchronous with ADC conversion start

101, 110, 111 - reserved, not allowed

Please refer to chapter 4.1, DAC Updates (LDAC) for a detailed

description of DAC update modes.

The reset value of the CONFIG register is 0x00.


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D.Module.ADDA16 User's Guide A/D Converter

D.SignT 2004 Doc #1.0 11

3 A/D Converter

The analog-to-digital converters are successive approximation converters with 16

bit resolution and a maximum sampling frequency of 250 kHz. Conversion time is

1.25 s, acquisition time is 2.75 s, independent of the sampling clock. The digi-

tal output is serially transmitted to the DSP bus interface, where it is converted

into a parallel output word. Data format is 2's complement . A 0V input converts

to a 0x0000 output word, -2.5V input converts to 0x8000, and the maximum posi-

tive input voltage of 2.4999V converts to 0x7FFF. An LSB is 76.3 V.

The serial transmission from ADC to the bus interface is clocked with 40 MHz.

The transmission and loading of the parallel buffer takes 18 clock cycles = 450ns.

Hence, the ADC latency time is 2.75s + 1.25s + 450 ns = 4.45s.

3.1 Analog Inputs

The analog input interface is a buffered differential amplifier which accepts input

voltages of +/- 2.5V. Single-ended inputs can be connected by grounding the IN-

input. The output of the differential amplifier is fed to the A/D converter input.

Pin Signal Comment

G1 ADC0 IN+ Channel 0 non-inverting input

G2 ADC0 IN- Channel 0 inverting input

H1 AGND Analog Ground

H2 AGND Analog Ground

I1 ADC1 IN+ Channel 1 non-inverting input

I2 ADC1 IN- Channel 1 inverting input

J1 AGND Analog Ground


K1 ADC2 IN+ Channel 2 non-inverting inputK2 ADC2 IN- Channel 2 inverting input

L1 AGND Analog Ground


M1 ADC3 IN+ Channel 3 non-inverting input

M2 ADC3 IN- Channel 3 inverting input

Table 3-1 Analog Input Signals

No anti-aliasing filters are provided on the D.Module.ADDA16. If the input signal

contains spectral components above the Nyquist frequency (1/2 sampling fre-


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D.SignT 2004 Doc #1.0 12

quency), external band limiting filters are required. The required filter order de-

pends on the out-of-band energy levels: the filter should ideally attenuate any out-

of-band signals to be 90 dB below the full-scale input. i.e. if out-of-band signals

are present at 30dB below full-scale, the filter should provide additional 60 dBattenuation.

The wide analog input bandwidth (800 kHz) of the converters allows to use the

ADDA16 in a sub-sampling configuration if the input signal is inherently band-

limited, like in the intermediate frequency stage of a receiver.

3.2 Sampling Clock

The A/D converter conversion start signal is generated from an on-board oscilla-

tor or provided externally via EXT_CLKIN. The FS Register is used to set the

sampling clock source and frequency.

40 MHzClock Source

div 10

LOAD

CLK

CNT == 0

FS

Reg.

CLK

1 D

CNVST

FS_REG == 0

EXT_CLKIN

EXT_CLKOUT_ENABLE

EXT_CLKOUT

Figure 3-1 Sampling Clock Circuit

The 40 MHz internal clock source is pre-divided by 10, and fed to a preset-able

down counter, which is preset from the module's FS register. If the FS register is

programmed to a value different from 0, the counter output is used as the con-

version start signal. If the FS register is 0, the external sampling clock from

EXT_CLKIN is used. The conversion start signal is re-synchronized to the 40

MHz master clock. This synchronization flip-flop is powered from the analog

supply voltage to minimize jitter and noise on the conversion start signal.


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D.SignT 2004 Doc #1.0 13

The EXT_CLKOUT output can be enabled and used to feed slave ADDA16

boards if more than four input channels are required, or synchronize other pe-

ripheral devices to the sampling clock.

For an eight-channel system, stack two ADDA16 boards and configure as follows:

Board 1 is the master, it generates the sampling frequency. Set the desired sam-

pling frequency and enable this board's EXT_CLKOUT output.

Board 2 is the slave board. It is configured for external sampling clock. Leave this

board's EXT_CLKOUT disabled. (also remember to select a different base ad-

dress for Board2)

Finally connect EXT_CLKOUT to EXT_CLKIN. This will route Board1

EXT_CLKOUT to Board 2 EXT_CLKIN.

Pin Signal Comment

C22 EXT_CLKIN external sampling clock input

C23 EXT_CLKOUT external sampling clock output

Table 3-2 Sampling Clock Signals


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D.Module.ADDA16 User's Guide D/A Converter

D.SignT 2004 Doc #1.0 14

4 D/A Converter

The digital-to-analog converters use a serial data interface too. The DSP bus

interface logic provides the parallel-to serial converter. Data is clocked into the

DAC with a 40 MHz clock. A transmission takes 20 clock cycles.

The DAC settles to 1 LSB accuracy in 2 s. Adding the 500 ns for serial trans-

mission, the DAC latency is 2.5 s, which must be taken into account as dead-

time in control loops.

The DACs itself use straight binary coding, but the bus interface logic converts

2's complement into straight binary, so the DSP can write it's native 2's comple-

ment data to the DAC. A 0x8000 translates to -2.5V on the output, a 0x0000 to0V output, and 0x7FFFF to +2.4999V.

The software designer must take care to avoid 2's complement overflows, as this

will generate full-scale signal spikes on the DAC output. Most DSPs provide in-

ternal saturation logic to prevent 2's complement overflow.

The DAC interface is single-buffered. The buffer can be written by the DSP while

a serial transmission to the DAC is in progress. This allows to write two DACs

almost immediately following each other, but if 3 or 4 DACs should be written, the

DSP program must wait for the buffer to be free before the data for DAC2 and

DAC 3 is written.

DSP Data

DSP Addr 0 and 1

DSP Write

DAC-Buffer

DAC-Shifter

40 MHz

DAC Serial Data In

Control Logic

ShiftComplete

TransmissionRequest

Load

Interrupt, DAC_READY

Figure 4-1 DAC Interface


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D.SignT 2004 Doc #1.0 15

On a write to one of the four DAC registers the bus interface latches the 16 data

bits and the two least significant address lines, which determine the DAC to write

to. A transmission request signal is generated. If no shift operation to the DAC is

currently in progress, the shifter is loaded with the buffer content and immediatelystarts shifting out the data to the DAC. Simultaneously with the shifter load sig-

nal, an interrupt is generated, rsp. the DAC_READY flag is set. The DSP can then

write the next data word to the DAC buffer. Again, a transmission request is gen-

erated, but now the control logic delays the shifter load until the current shift is

completed.

The DAC interface will generate an interrupt every time a shift is completed,

hence every 500 ns. This corresponds to the maximum DAC update rate of 250

kHz for all four channels. Each individual DAC is written every 2 s, correspond-ing to it's required settling time. In most systems slower update rates will be

used. You can either synchronize DAC writes to the ADC interrupt, or use a DSP

timer interrupt if an update frequency different from the ADC sampling frequency

is required. Many systems will also use "on demand" DAC writes, i.e. write to the

DAC only if the output value needs to be changed.

The DSP programmer should use one of the following programming techniques:

only one DAC is used in the system: Direct writes to the DAC are possible,

either programmed, from an interrupt, or DMA triggered.

two DACs are used: After writing to the first DAC the serial transfer starts

immediately and the buffer is free again to accept the data for the 2nd DAC.

Poll the DAC_READY flag before writing to the 2nd DAC to make sure trans-

fer has started and the DAC buffer is free. The latency caused by polling the

DAC_READY flag is approximately 50 ns

ADDA16_DAC_WRITE (0, data); while (!(ADDA16-cfg & ADDA16_DAC_READY));

ADDA16_DAC_WRITE (1, data);

three or four DACs are used: always poll the DAC_READY flag before writing

to a DAC, or use interrupt transfers. Polling DAC_READY will block your pro-

gram for only 50 ns before the 2nd

DAC can be written, but for 500 ns each

before writing to the 3rd

and the 4th

DAC. If this time is not tolerable use inter-

rupts as shown in this program fragment:


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D.SignT 2004 Doc #1.0 16

void dac_int (void)

{

static int idx = 1;

ADDA16_DAC_WRITE (idx, data); /* write to next DAC */

if (++idx == 4) {

ADDA16->cfg &= ADDA16_INT1DAC; /* disable INT1 */

idx = 1;

}

}

void main (void) {

install_interrupt (SIG_INT1, dac_int);

...

for (;;) {

...

ADDA16_DAC_WRITE (0, data); /* write to DAC 0 */

ADDA16->cfg |= ADDA16_INT1DAC; /* enable DAC-Int */

} }

After the first DAC is written from the main program, DAC interrupts are en-

abled by setting the corresponding bit in the ADDA16 Configuration Register.

As soon as the DAC buffer is free, an interrupt will be generated, and interrupt

function dac_int() will be executed. In this function the 2nd

DAC is written, and

variable idx in incremented. As soon as the buffer is free again, dac_int() is

invoked again. Now the third DAC is written. After the buffer is free, dac_int()

will be executed for the last time. Now the fourth DAC is written. idx will in-

crement to 4, and further DAC interrupts are disabled by clearing the interrupt

enable bit, until enabled again.


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D.SignT 2004 Doc #1.0 17

4.1 DAC Updates (LDAC)

Writing to a DAC will only store the data in the DAC's internal buffer register, but

not update it's output. The LDAC signal is used to update the DAC output. The

D.Module.ADD16 supports three configurations to generate LDAC, which are

configured in the LDAC bitfield of the ADDA16 configuration register :

1. following any write to a DAC, LDAC is generated as soon as the transfer is

complete

2. LDAC is generated only after writing to the second, third, or fourth DAC.

3. LDAC is synchronous with the ADC sampling frequency

The first option, always generate LDAC following a write, is useful for on demand

DAC writes, if phase relation between DAC channels is not important, or if only

one DAC is used. Immediately after the write, the DAC will change it's output.

This option is selected by writing a 0 to the LDAC bitfield.

The second option will synchronously update the selected DACs after the last one

is written. To control a 3-phase motor for example, three DACs are required and

all should be updated synchronously to provide exact phase relationship. In this

case, set the LDAC bitfield to 2. Now write the output values to DAC0, DAC1, and

DAC2. After the last write (to DAC2), all three DACs synchronously update their

outputs. If DAC update and ADC conversion should by synchronized, start writing

the DACs in the ADC interrupt service.

The last option is used if ADC sampling and DAC update should be synchronous

and occur at exactly the same time. This configuration minimizes jitter on the

DAC outputs. Typically the program will write to the DACs in the ADC interrupt

service, to be synchronous. Exact phase relation between DAC channels is

maintained as long as all DACs are completely written before the next conversion

start (and hence LDAC) occurs. This can only be guaranteed for sampling fre-

quencies below approx. 133 kHz: Following conversion start, it takes 4.5 s until

the ADC interrupt is generated. If DAC writes are started now, it will take addi-

tional 2 s (4 x 500 ns) to write all four DACs. The total time from Conversion

start until the DAC writes are complete is 6.5 s. This is the minimum sampling

period to guarantee synchronous updates. Adding some extra time for interrupt

latencies results in 7.5s, or 133 kHz maximum sampling frequency. This option

is selected by writing a 4 to the LDAC bitfield.


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D.SignT 2004 Doc #1.0 18

4.2 Analog Outputs

The DACs are followed by an I-V converter, which translates the DAC output

current into a voltage, and a 2nd

order Butterworth smoothing filter. This filter

attenuates the high frequency switching spikes generated by DAC code transi-

tions. and smoothes the output waveform. The analog output is single-ended with

+/- 2.5V full-scale output.

The Butterworth filters are factory set to a corner frequency of 100 kHz. Custom

corner frequencies are available on demand.

Large capacitive loads on the outputs add a pole to the transfer function and will

increase ringing and overshot, and, in extreme cases, cause instability. Ca-

pacitive loads > 100 pF should be connected via a series resistor (approx. 100

ohms). To avoid gain loss the input of the driven circuit should be a high imped-

ance input. It is also possible to compensate the pole formed by the capacitive

load with a series RC combination from output to AGND.

Pin Signal Comment

G31 DAC0 OUT Channel 0 output

G32 AGND Analog Ground

H31 AGND Analog GroundH32 AGND Analog Ground

I31 DAC1 OUT Channel 1 output

I32 AGND Analog Ground



K31 DAC2 OUT Channel 2 output

K32 AGND Analog Ground



M31 DAC3 OUT Channel 3 output

M32 AGND Analog Ground

Table 4-1 Analog Output Signals


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D.Module.ADDA16 User's Guide Power Supply

D.SignT 2004 Doc #1.0 19

5 Power Supply

The ADDA16 module requires a bipolar analog power supply, and a single digital

3.3V power supply.

The analog power supply is +/- 5V. For best performance a power supply build

around a mains transformer and linear regulators should be used. The power-

supply rejection ratio of the op-amps and converters used on the ADDA16 will

attenuate power-supply noise up to 60dB. However, attenuation decreases with

increasing frequency. High frequency noise, as produced by switch mode power

supplies, cannot be sufficiently attenuated by the components and will degrade

performance: high frequency noise may modulate the input and output signals,

and is aliased into the baseband during conversion. A switch mode supply with

linear post regulation doesn't cure the problem, because linear regulators suffer

from bandwidth limitations too. If a switch mode supply must be used, add pas-

sive LC filters in the supply rails, tuned to the specific noise spectrum of the

switcher. An excellent choice for a low-noise switch mode supply is the Linear

Technology LTC1533 switching regulator.

The digital power supply can be taken directly from the DSP supply. It powers the

bus interface circuits, the serial interfaces to the data converters, and the sam-pling clock divider. This may add some jitter to the sampling clock, but this jitter

is attenuated later by resynchronization in an analog-powered D-type flip-flop.

Digital and Analog ground return paths should ideally be interconnected close to

the converters. Only one interconnection should exist in the entire system. A

jumper (JPGND) on the D.Module.ADD16 provides this connection. If your sys-

tem already has interconnected AGND and GND, open jumper JPGND on the

ADDA16 board. If multiple boards are cascaded, only one should have JPGND

closed. Some experiments may be required to determine the best location forAGND-GND connection, depending on your system layout.


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D.Module.ADDA16 User's Guide Pinout

D.SignT 2004 Doc #1.0 20

6 Pinout

Pin A B C T U V

1 VCC GND

2 nRD

3 nINT0

4 nINT1

5 nWR

6 BUSCLK

7 nRESOUT

8 nIOSEL9 A0

10 A1

11 A2

12 A3 A16

13 A4 A17

14 A5 A18

15 -AVCC D0

16 AGND D1

17 +AVCC D2

18 D3

19 D4

20 D5

21 D6

22 EXT_CLKIN D7

23 EXT_CLKOUT D8

24 D9

25 D10

26 D11

27 D1228 D13

29 D15

30 D15

31

32 GND VCC GND GND

Table 6-1 D.Module.Connector, blank fields are not connected


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D.Module.ADDA16 User's Guide Pinout

D.SignT 2004 Doc #1.0 21

Pin 1 2

F +AVCC (use as output only!) -AVCC (use as output only )

G ADC channel 0 IN+ ADC channel 0 IN -H AGND AGND

I ADC channel 1 IN+ ADC channel 1 IN -

J AGND AGND

K ADC channel 2 IN+ ADC channel 2 IN -

L AGND AGND

M ADC channel 3 IN+ ADC channel 3 IN -

N VCC (use as output only) GND (use as output only)

O rsvd rsvd

P rsvd rsvd

Table 6-2 Analog Input Connector Pinout

Pin 31 32

F +AVCC (use as output only!) -AVCC (use as output only )

G DAC channel 0 OUT AGNDH AGND AGND

I DAC channel 1 OUT AGND

J AGND AGND

K DAC channel 2 OUT AGND

L AGND AGND

M DAC channel 3 OUT AGND

N VCC (use as output only) GND (use as output only)

O rsvd rsvd

P rsvd rsvd

Table 6-3 Analog Output Connector Pinout


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D.Module.ADDA16 User's Guide Mechanics

D.SignT 2004 Doc #1.0 22

7 Mechanics

32

2,54 mm

78,74 mm

B

C

A

T

UV

53,3

4mm

2,54 mm

7,6

2mm

35,5

6mm

58,4

2mm

83,82 mm

1,27 mm

2,54 mm

2,54 mm

76,20 mm1

12,7

0mm

3,21mm

1,59 mm

4,76 mm

4,85 mmmax component height on top : 4,50 mm

max component height on bottom: 2,50 mm

7,96 mm

Figure 5-1 D.Module.ADDA16 Mechanics


24/24

D.Module.ADDA16 User's Guide Electrical Characteristics

8 Electrical Characteristics

Power Supply analog: +/- 5V 150mA

digital: +3.3V 400mA

Operating Temperature 0 .. +70C

Analog Inputs 4, differential (single-ended by grounding IN-)

Input Voltage +/-2.5V

Input Resistance 200 kOhm differential, 100 kOhm single-ended

Input Bandwidth 800 kHz

Analog Outputs 4, single ended

Output Voltage +/- 2.5V

Output Load > 2 kOhm

A/D Converter 4, successive approximation

Resolution 16 bit

Acquisition Time 2.75 s

Conversion Time 1.25 s

Sampling Frequency 16 .. 250 kHz internal, 0..250 kHz external

D/A Converter 4, R2R ladder

Resolution 16 bit

Settling Time 2 s to 1 LSB for a full-scale step

Smoothing Filter 2nd

order Butterworth, cutoff frequency 100 kHz

Digital Inputs TTL, 5V tolerant, 10 pF input capacitance

Digital Outputs TTL, 5V TTL compatible, max. +/-4mA

DSP Interface Timing

Read: Access Time (Addr, nRD, nIOSEL to data valid) > 30 ns

Write: Data Setup to rising edge of nWR or nIOSEL: > 20 ns

Data Hold from rising edge of nWR or nIOSEL: > 0ns

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