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UWB Amplifier UWB Amplifier
Sarah Kief and Saif AnwarSarah Kief and Saif Anwar
Advisor: Dr. Prasad ShastryAdvisor: Dr. Prasad Shastry
2008 Senior Project2008 Senior Project
Bradley University Electrical Bradley University Electrical EngineeringEngineering
OutlineOutline
Where we left offWhere we left off Distributed Amplifier DesignDistributed Amplifier Design Microstrip Line DesignMicrostrip Line Design Coplanar Wave Guide DesignCoplanar Wave Guide Design M-derive Design M-derive Design Near future activitiesNear future activities
Where we left offWhere we left off
Picked transistor - NE4210S01Picked transistor - NE4210S01 Cutoff max at 20 GHzCutoff max at 20 GHz
Designed lumped element Designed lumped element componentscomponents Design EquationsDesign Equations
Design EquationsDesign Equations
Where we left offWhere we left off
Picked transistor - NE4210S01Picked transistor - NE4210S01 Cutoff max at 20 GHzCutoff max at 20 GHz
Designed lumped element Designed lumped element componentscomponents
Chose biasing parameters from the Chose biasing parameters from the DC-IV curvesDC-IV curves Vds=1[V], Vgs=-.45[V]Vds=1[V], Vgs=-.45[V]
Bias Point SelectionBias Point Selection
0.5 1.0 1.5 2.0 2.5 3.0 3.50.0 4.0
10
20
30
40
50
60
0
70
VDS
I_P
robe
1.i,
mA
Readout
m1
3.9800.061
m2
4.0000.055
m3
2.0100.010
m4
m1VDS=I_Probe1.i=0.032VGS=-0.520000
3.980m2VDS=I_Probe1.i=0.029VGS=-0.560000
3.980m3VDS=I_Probe1.i=0.026VGS=-0.600000
4.000m4VDS=I_Probe1.i=0.010VGS=-0.680000
2.010Vds of 2 volts and Ids of 10mA for noise figure.
Where we left offWhere we left off
Picked transistor - NE4210S01Picked transistor - NE4210S01 Cutoff max at 20 GHzCutoff max at 20 GHz
Designed lumped element Designed lumped element componentscomponents
Chose biasing parameters from the Chose biasing parameters from the DC-IV curvesDC-IV curves Vds=1[V], Vgs=-.45[V]Vds=1[V], Vgs=-.45[V]
Built / simulated lumped element Built / simulated lumped element model with 1 transistormodel with 1 transistor 7 dB7 dB
Distributed Amplifier Distributed Amplifier DesignDesign
Lumped element model built in ADSLumped element model built in ADS 2 and 3 transistor designs2 and 3 transistor designs Simulations Simulations
Gain flatnessGain flatness Phase linearity Phase linearity StabilityStability
3 Transistor M-derived 3 Transistor M-derived Lumped Element NetworkLumped Element Network
LGLG/2-
LG/2 LG
LDLDLD/2
LD/2
LL9
R=L=.424 nH
CC5C=.0954 pF
LL8
R=L=.238 nHTerm
Term1
Z=50 OhmNum=1
CC6C=2400 pF
LL19
R=L=.395 nH
LL11
R=L=.238 nH
LL3
R=L=.79 nH
LL17
R=L=.79 nH
LL2
R=L=.395 nH
LL14
R=L=2200 nH
CC9C=2400 pF
CC11C=2400 pF
V_DCSRC2Vdc=-.45 V
RR2R=50 Ohm
CC8C=.0954 pF
LL13
R=L=.424 nH
LL25
R=L=56.31 pH
LL24
R=L=56.31 pH
LL23
R=L=56.31 pH
CC3C=2400 pF
LL7
R=L=2200 nH
CC4C=2400 pF
RR3R=50 Ohm
CC2C=.0954 pF
LL6
R=L=.424 nH
LL5
R=L=.238 nH
V_DCSRC1Vdc=1 V
S_ParamSP1
Step=Stop=10.6 GHzStart=3.1 GHz
S-PARAMETERS
TechInclude_NEC_ACTIVELIBRARYNEC_ACTIVELIBRARY_LibFile=Nominal
LL1
R=L=.395 nH
LL18
R=L=.395 nH
LL4
R=L=.79 nH
LL15
R=L=.79 nH
LL20
R=L=56.31 pH
LL21
R=L=56.31 pH
LL22
R=L=56.31 pH
NEC_FETQ2partName=NE4210S01_v116
NEC_FETQ3partName=NE4210S01_v116
NEC_FETQ1partName=NE4210S01_v116
LL12
R=L=.424 nH
CC7C=.0954 pF
LL10
R=L=.238 nH
TermTerm2
Z=50 OhmNum=2
CC12C=2400 pF
SimulationsSimulations
3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.53.0 11.0
-10
-5
0
5
10
-15
15
freq, GHz
dB(S
(2,1
))
Readout
m1
m1freq=dB(S(2,1))=14.857Max
7.649GHz
4 5 6 7 8 9 103 11
-100
0
100
-200
200
freq, GHz
phas
e(S
(2,1
))
SimulationsSimulations
Eqnk = stab_fact(S)Eqnk1=stab_meas(S)m2freq=k=0.543Min
9.623GHz
4 5 6 7 8 9 103 11
50
100
150
0
200
freq, GHz
k
Readout
m2
m2freq=k=0.543Min
9.623GHz
4 5 6 7 8 9 103 11
0.8
1.0
0.6
1.2
freq, GHz
k1
Microstrip Line DesignMicrostrip Line Design
Translated lumped element Translated lumped element components into respective lengths components into respective lengths and widths in the MSTRIP programand widths in the MSTRIP program Capacitors Zo=30 ohmsCapacitors Zo=30 ohms Inductor Zo=90 ohmsInductor Zo=90 ohms
Built layout in ADS and simulatedBuilt layout in ADS and simulated Compared microstrip simulation Compared microstrip simulation
results to lumped element results to lumped element simulationssimulations
Component Values Component Values
Capacitors (pF) Capacitors (pF) width(mm)width(mm) length (mm)length (mm) Inductors (nH) Inductors (nH) width(mm)width(mm)
length length (mm(mm
))
9.54E-149.54E-14 2.670222.67022 0.53350.5335 6.34E-106.34E-10 0.7035560.703556 1.38201.3820
1.50E-131.50E-13 2.670222.67022 0.83610.8361 7.90E-107.90E-10 0.7035560.703556 1.72341.7234
2.40E-092.40E-09 2.670222.67022 13422.240013422.2400 4.24E-104.24E-10 0.7035560.703556 0.92490.9249
2.20E-062.20E-06 0.7035560.7035564799.2264799.226
77
5.63E-115.63E-11 0.7035560.703556 0.12280.1228
Lambda EFF (mm)Lambda EFF (mm) Lambda EFF (mm)Lambda EFF (mm)
15.53515.535 16.36116.361
1.9418751.941875 2.0451252.045125
FrequencyFrequency
1.20E+101.20E+10
Zo (ohms)Zo (ohms) Zo (ohms)Zo (ohms)
3030 9090
Cap = f * lambda eff * cap Cap = f * lambda eff * cap * zo* zo
L = f * lambda eff * L = f * lambda eff * in/zoin/zo
Microstrip LayoutMicrostrip Layout
MSUBMSub1
Rough=0 milTanD=0.0012T=35 umHu=3.9e+034 milCond=5.8E7Mur=1Er=2.94H=20.0 mil
MSub
TechInclude_NEC_ACTIVELIBRARYNEC_ACTIVELIBRARY_LibFile=Nominal
S_ParamSP1
Step=Stop=10.6 GHzStart=3.1 GHz
S-PARAMETERS
MTEE_ADSTee3
W3=.703556 mmW2=25.0 milW1=.703556 mmSubst="MSub1"
MLINL12
L=.9249 mmW=.703556 mmSubst="MSub1"
MSTEPStep5
W2=.703556 mmW1=2.67022 mmSubst="MSub1"
MLINC7
L=.5335 mmW=2.67022 mmSubst="MSub1"
TermTerm1
Z=50 OhmNum=2
CC14C=2400 pF
MLINL17+L11
L=1.3820 mmW=.703556 mmSubst="MSub1"
VIAGNDV14
W=25.0 milRho=1.0T=0.15 milD=15.0 milSubst="MSub1"
VIAGNDV11
W=25.0 milRho=1.0T=0.15 milD=15.0 milSubst="MSub1"
MLINL15+L10
L=1.3820 mmW=.703556 mmSubst="MSub1"MTEE_ADS
Tee9
W3=.703556 mmW2=.703556 mmW1=.703556 mmSubst="MSub1"
MLINTL5
L=.1228 mmW=.703556 mmSubst="MSub1"
NEC_FETQ3partName=NE4210S01_v116
MLINTL6
L=.1228 mmW=.703556 mmSubst="MSub1"
MTEE_ADSTee10
W3=.703556 mmW2=.703556 mmW1=.703556 mmSubst="MSub1"
MLINTL4
L=.1228 mmW=.703556 mmSubst="MSub1"
MLINL20
L=1.7234 mmW=.703556 mmSubst="MSub1"
VIAGNDV3
W=25.0 milRho=1.0T=0.15 milD=15.0 milSubst="MSub1"
VIAGNDV13
W=25.0 milRho=1.0T=0.15 milD=15.0 milSubst="MSub1"
NEC_FETQ2partName=NE4210S01_v116
MLINTL1
L=.1228 mmW=.703556 mmSubst="MSub1"
MTEE_ADSTee5
W3=.703556 mmW2=.703556 mmW1=.703556 mmSubst="MSub1"
MLINL4
L=1.7234 mmW=.703556 mmSubst="MSub1"MTEE_ADS
Tee6
W3=.703556 mmW2=.703556 mmW1=.703556 mmSubst="MSub1"
MLINTL2
L=.1228 mmW=.703556 mmSubst="MSub1" VIAGND
V12
W=25.0 milRho=1.0T=0.15 milD=15.0 milSubst="MSub1"
VIAGNDV2
W=25.0 milRho=1.0T=0.15 milD=15.0 milSubst="MSub1"
MTEE_ADSTee8
W3=.703556 mmW2=.703556 mmW1=.703556 mmSubst="MSub1"
MLINL8+L2
L=1.3820 mmW=.703556 mmSubst="MSub1"
NEC_FETQ1partName=NE4210S01_v116
MLINTL3
L=.1228 mmW=.703556 mmSubst="MSub1"
MTEE_ADSTee7
W3=.703556 mmW2=.703556 mmW1=.703556 mmSubst="MSub1"
MLINL21
L=1.7234 mmW=.703556 mmSubst="MSub1"
VIAGNDV6
W=25.0 milRho=1.0T=0.15 milD=15.0 milSubst="MSub1"
VIAGNDV5
W=25.0 milRho=1.0T=0.15 milD=15.0 milSubst="MSub1"
MTEE_ADSTee4
W3=.703556 mmW2=25.0 milW1=.703556 mmSubst="MSub1"
MLINC8
L=.5335 mmW=2.67022 mmSubst="MSub1"
MSTEPStep6
W2=.703556 mmW1=2.67022 mmSubst="MSub1"
MLINL13
L=.9249 mmW=.703556 mmSubst="MSub1"
V_DCSRC2Vdc=-.45 V
CC16C=2400 pF
LL19
R=L=2200 nH
RR2R=50 Ohm
CC15C=2400 pF
MLINL3
L=1.7234 mmW=.703556 mmSubst="MSub1"
VIAGNDV10
W=25.0 milRho=1.0T=0.15 milD=15.0 milSubst="MSub1"
CC10C=2400 pF
LL18
R=L=2200 nH
V_DCSRC1Vdc=1.0 V
MLINL5+L1
L=1.3820 mmW=.703556 mmSubst="MSub1"
MLINC2
L=.5335 mmW=2.67022 mmSubst="MSub1"
MSTEPStep1
W2=.703556 mmW1=2.67022 mmSubst="MSub1"
MLINL6
L=.9249 mmW=.703556 mmSubst="MSub1"
MTEE_ADSTee2
W3=.703556 mmW2=.703556 mmW1=25.0 milSubst="MSub1"
CC11C=2400 pF
RR1R=50 Ohm
VIAGNDV8
W=25.0 milRho=1.0T=0.15 milD=15.0 milSubst="MSub1"
MTEE_ADSTee1
W3=.703556 mmW2=.703556 mmW1=25.0 milSubst="MSub1"
MLINC5
L=.5335 mmW=2.67022 mmSubst="MSub1"
MSTEPStep7
W2=.703556 mmW1=2.67022 mmSubst="MSub1"
MLINL9
L=.9249 mmW=.703556 mmSubst="MSub1"
TermTerm2
Z=50 OhmNum=1
CC9C=2400 pF
SimulationsSimulations
3.54.04.55.05.56.06.57.07.58.08.59.09.510.010.53.0 11.0123456789
1011
0
12
freq, GHzdB
(S(2
,1))
Readout
m1m1freq=dB(S(2,1))=11.717Max7.085GHz4 5 6 7 8 9 103 11
-100
0
100
-200
200
freq, GHz
ph
ase
(S(2
,1))
SimulationsSimulations
Eqn k = stab_fact(S) m2freq=k=1.477Min
10.60GHz
4 5 6 7 8 9 103 11
2
3
4
5
1
6
freq, GHz
k
Readout
m2
m2freq=k=1.477Min
10.60GHzEqn k1=stab_meas(S)
m3freq=k1=0.868Min
10.60GHz
4 5 6 7 8 9 103 11
0.88
0.90
0.92
0.94
0.86
0.96
freq, GHz
k1
Readout
m3
m3freq=k1=0.868Min
10.60GHz
Coplanar Wave Guide Coplanar Wave Guide DesignDesign
Chose RT/Duriod 6002 boardChose RT/Duriod 6002 board Thickness : 20 mils, .508 mmThickness : 20 mils, .508 mm Dielectric Constant : 2.94 Dielectric Constant : 2.94 1 oz copper plating1 oz copper plating High mechanical strength High mechanical strength
Coplanar Wave Guide Coplanar Wave Guide DesignDesign
Design wave guide to test transistorsDesign wave guide to test transistors LayoutLayout
Designed width and length of the Designed width and length of the layout using Line calclayout using Line calc DimensionsDimensions
Width = 1.017 mmWidth = 1.017 mm Air Gap = .808 mmAir Gap = .808 mm Length = 10 mmLength = 10 mm
Constructed layout in ADS Constructed layout in ADS Tested and simulated in ADSTested and simulated in ADS
NE4210S01 Transistor Pad NE4210S01 Transistor Pad LayoutLayout
Full Coplanar Wave Full Coplanar Wave GuideGuide
Half Coplanar Wave Guide Half Coplanar Wave Guide LayoutLayout
ADS Schematic of Coplanar ADS Schematic of Coplanar WaveguideWaveguide
Layout SimulationLayout Simulation
Lm
Cm
Constant-k LPF M-Derived LPF
Need for M-Derived Filter Design• To avoid padding capacitor.
• Useful in the layout design.
• Easier for optimization purpose.
M-Derive Design LayoutM-Derive Design Layout
• Lm = L*(k-m2)/4*m
• k = m*Cg or Cd / Cm
where Cm = Cin or Cout
• Cin=.33 pF, Cout=.1686 pF
• Lmd = 1.42 nH (for drain side)
• Lmg = 0.004nH (for gate side)
M-Derive EquationsM-Derive Equations
M-Derived Microstrip M-Derived Microstrip LayoutLayout
MSUBMSub1
Rough=0 milTanD=0.0012T=35 umHu=3.9e+034 milCond=5.8E7Mur=1Er=2.94H=20.0 mil
MSub
TechInclude_NEC_ACTIVELIBRARYNEC_ACTIVELIBRARY_LibFile=Nominal
S_ParamSP1
Step=Stop=10.6 GHzStart=3.1 GHz
S-PARAMETERS
MTEE_ADSTee3
W3=.703556 mmW2=25.0 milW1=.703556 mmSubst="MSub1"
MLINL12
L=.9249 mmW=.703556 mmSubst="MSub1"
MSTEPStep5
W2=.703556 mmW1=2.67022 mmSubst="MSub1"
MLINC7
L=.5335 mmW=2.67022 mmSubst="MSub1"
TermTerm1
Z=50 OhmNum=2
CC14C=2400 pF
MLINL17+L11
L=1.3820 mmW=.703556 mmSubst="MSub1"
VIAGNDV14
W=25.0 milRho=1.0T=0.15 milD=15.0 milSubst="MSub1"
VIAGNDV11
W=25.0 milRho=1.0T=0.15 milD=15.0 milSubst="MSub1"
MLINL15+L10
L=1.3820 mmW=.703556 mmSubst="MSub1"MTEE_ADS
Tee9
W3=.703556 mmW2=.703556 mmW1=.703556 mmSubst="MSub1"
MLINTL5
L=.1228 mmW=.703556 mmSubst="MSub1"
NEC_FETQ3partName=NE4210S01_v116
MLINTL6
L=.1228 mmW=.703556 mmSubst="MSub1"
MTEE_ADSTee10
W3=.703556 mmW2=.703556 mmW1=.703556 mmSubst="MSub1"
MLINTL4
L=.1228 mmW=.703556 mmSubst="MSub1"
MLINL20
L=1.7234 mmW=.703556 mmSubst="MSub1"
VIAGNDV3
W=25.0 milRho=1.0T=0.15 milD=15.0 milSubst="MSub1"
VIAGNDV13
W=25.0 milRho=1.0T=0.15 milD=15.0 milSubst="MSub1"
NEC_FETQ2partName=NE4210S01_v116
MLINTL1
L=.1228 mmW=.703556 mmSubst="MSub1"
MTEE_ADSTee5
W3=.703556 mmW2=.703556 mmW1=.703556 mmSubst="MSub1"
MLINL4
L=1.7234 mmW=.703556 mmSubst="MSub1"MTEE_ADS
Tee6
W3=.703556 mmW2=.703556 mmW1=.703556 mmSubst="MSub1"
MLINTL2
L=.1228 mmW=.703556 mmSubst="MSub1" VIAGND
V12
W=25.0 milRho=1.0T=0.15 milD=15.0 milSubst="MSub1"
VIAGNDV2
W=25.0 milRho=1.0T=0.15 milD=15.0 milSubst="MSub1"
MTEE_ADSTee8
W3=.703556 mmW2=.703556 mmW1=.703556 mmSubst="MSub1"
MLINL8+L2
L=1.3820 mmW=.703556 mmSubst="MSub1"
NEC_FETQ1partName=NE4210S01_v116
MLINTL3
L=.1228 mmW=.703556 mmSubst="MSub1"
MTEE_ADSTee7
W3=.703556 mmW2=.703556 mmW1=.703556 mmSubst="MSub1"
MLINL21
L=1.7234 mmW=.703556 mmSubst="MSub1"
VIAGNDV6
W=25.0 milRho=1.0T=0.15 milD=15.0 milSubst="MSub1"
VIAGNDV5
W=25.0 milRho=1.0T=0.15 milD=15.0 milSubst="MSub1"
MTEE_ADSTee4
W3=.703556 mmW2=25.0 milW1=.703556 mmSubst="MSub1"
MLINC8
L=.5335 mmW=2.67022 mmSubst="MSub1"
MSTEPStep6
W2=.703556 mmW1=2.67022 mmSubst="MSub1"
MLINL13
L=.9249 mmW=.703556 mmSubst="MSub1"
V_DCSRC2Vdc=-.45 V
CC16C=2400 pF
LL19
R=L=2200 nH
RR2R=50 Ohm
CC15C=2400 pF
MLINL3
L=1.7234 mmW=.703556 mmSubst="MSub1"
VIAGNDV10
W=25.0 milRho=1.0T=0.15 milD=15.0 milSubst="MSub1"
CC10C=2400 pF
LL18
R=L=2200 nH
V_DCSRC1Vdc=1.0 V
MLINL5+L1
L=1.3820 mmW=.703556 mmSubst="MSub1"
MLINC2
L=.5335 mmW=2.67022 mmSubst="MSub1"
MSTEPStep1
W2=.703556 mmW1=2.67022 mmSubst="MSub1"
MLINL6
L=.9249 mmW=.703556 mmSubst="MSub1"
MTEE_ADSTee2
W3=.703556 mmW2=.703556 mmW1=25.0 milSubst="MSub1"
CC11C=2400 pF
RR1R=50 Ohm
VIAGNDV8
W=25.0 milRho=1.0T=0.15 milD=15.0 milSubst="MSub1"
MTEE_ADSTee1
W3=.703556 mmW2=.703556 mmW1=25.0 milSubst="MSub1"
MLINC5
L=.5335 mmW=2.67022 mmSubst="MSub1"
MSTEPStep7
W2=.703556 mmW1=2.67022 mmSubst="MSub1"
MLINL9
L=.9249 mmW=.703556 mmSubst="MSub1"
TermTerm2
Z=50 OhmNum=1
CC9C=2400 pF
Updated ScheduleUpdated ScheduleWeek of Tasks to complete
January 25th Designing the microstrip version of lumped element model.
February 7th Board , microstrip simulations and designing
February 14th M-derived simulations, coplanar wave guide design
February 21st Coplanar wave guide design simulation
February 28th Coplanar wave guide optimization and finalizing
March 6th Transistor optimization, coplanar wave guide finalizing
March 13th Transistor optimization, coplanar wave guide fabrication
March 20th Spring break, coplanar wave guide fabrication
March 27th Testing of transistor using coplanar wave guide
April 3rd Testing of transistor using coplanar wave guide, de-embedding
April 10th Amplifier fabrication
April 17th Amplifier fabrication
April 24th Testing amplifier
May 1st Testing amplifier
May 8th presentations
Near future Activities Near future Activities
Do De-embedding to find S-Parameters Do De-embedding to find S-Parameters on Coplanar Waveguideon Coplanar Waveguide
Determine the optimal number of Determine the optimal number of transistorstransistors
Order RT/Duriod BoardOrder RT/Duriod Board Test the S-Parameters of the Test the S-Parameters of the
TransistorsTransistors Optimize the final layoutOptimize the final layout Fabricate and test the circuitFabricate and test the circuit