COMPANY CONFIDENTIAL 1

Validation Test for IC Digital Design

Alex Lollio, Global Rotation Engineer

Automotive Products Business UnitProvence Design Centre, France

Sept, 2013 - Oct, 2013

Project Leader : Denis ParmentierProject Manager : Andre MourrierProgram Mentor : Massimo Grasso

COMPANY CONFIDENTIAL

Digital Design Flow: Validation Test is missing

Digital Pattern Testing Signal

SIMULATED DUT Expected Output

1. CADENCE DIGITAL SIMULATION TEST

3. FAILURE ANALISYS

REAL DUT

CADENCE “.stil” file generation

VALIDATION TEST ON DIGITAL DESIGN IS MISSING

Digital Pattern Testing Signal

Real DUT Output

2. VALIDATION TEST

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Digital Design Flow: Proposed Validation Test

Digital Pattern Testing Signal

SIMULATED DUT Expected Output

Digital Pattern Testing Signal

Test Passed if Real DUT Output = Expected Output

Real DUT Output

REAL DUT

PXI System located in Provence

1. CADENCE DIGITAL SIMULATION TEST

2. PROPOSED VALIDATION TEST

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Project Goal: Testing Application

Digital Pattern Testing Signal

DUTExpected Output

CADENCE “.stil” file generation

TSSI Converter“.stil” to “.xml”2k$

CADENCE SIMULATION

PROPOSED VALIDATION TEST

LabVIEW application for Generating and Acquiring the digital data and make the comparison test

7k$

DUT

Project Goal: Write LabVIEW application for making the

test

?0$

0$

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PXI System Overview

PXI CHASSIS

PXI CONTROLLER

HSDIO (NI PXI-6552)• -2 to 5.5V DIO Channels• Clock 100MHz• Internal Memory 8MB

BANANA TERMINALS

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Real Test Bench located at IR Provence

PROBER

CONNECTOR

PXI SYSTEM

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LabVIEW Interface: Signal Gen&Acq

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Conclusions

• LabVIEW Application for .STIL Digital Testing has been presented

• The LabVIEW Application Source Code has been uploaded to Provence Server and can be easily modified by everyone

• LabVIEW Classes of 5 working days has been done in Provence Design Center

• PXI system can be easily upgraded with an analog card in order to synchronize digital generation with analog acquisition

• Next step is to add to the system the IDDQ testing capability