VALLIAMMAI ENGINEERING COLLEGE
SRM Nagar, Kattankulathur – 603 203
DEPARTMENT OF
COMPUTER SCIENCE AND ENGINEERING
QUESTION BANK
III SEMESTER
CS8351-Digital Principles and system Design
Regulation – 2017
Academic Year 2018- 19
Prepared by
Dr.L.Karthikeyan AP/CSE
Ms.A.Vidhya Ap/CSE
Ms.Shanthi S AP/CSE
STUDENTSFOCUS.COM
VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur – 603 203.
DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING
QUESTION BANK
Year & Semester : II & III
Section : CSE 1 & 2 & 3
Subject Code : CS8351
Subject Name :
DIGITAL PRINCIPLES AND SYSTEMS DESIGN
Degree & Branch : B.E (CSE)
Staff in charge
: Dr.L.Karthikeyan AP/CSE
Ms.A.Vidhya Ap/CSE
Ms.Shanthi S AP/CSE
UNIT I
BOOLEAN ALGEBRA AND LOGIC GATES :Number Systems - Arithmetic Operations - Binary Codes- Boolean Algebra and Logic Gates - Theorems and Properties of Boolean Algebra - Boolean Functions - Canonical and Standard Forms - Simplification of Boolean Functions using Karnaugh Map - Logic Gates – NAND and NOR Implementations.
PART – A
Q.No Questions BT
Level
Competence
1. Define Multilevel Gates. BTL-1 Remember
2. Describe weighted binary code and Non –weighted
code. BTL-1 Remember
3. Explain Canonical and Standard Forms. BTL-5 Evaluate
4. Define and prove the consensus theorem. BTL-1 Remember
5. State and Apply DeMorgan’s theorem.
[(x+y)’+(x+y)’]’=x+y BTL-3 Apply
6. Explain the principle of duality. BTL-5 Evaluate
7. Describe the Commutative law and convert (126)10 to
octal. BTL-2 Understand
8. What is meant by self-Complementing Code and
convert (0.6875)10 to Binary BTL -1 Remember
9. Differentiate SOP and POS and convert
(101101.1101)2 to Hexadecimal. BTL-4 Analyze
10. Develop XOR gate using only 4 NAND gates. BTL-6 Create
11. Give the octal equivalent of hexadecimal numbers of
DC.BA and AB.CD BTL-2 Understand
12. Explain any four Boolean theorems with example. BTL-4 Analyze
13. Develop AND gate using NAND. BTL-6 Create
14. Define distributive law and associative law BTL-1 Remember
15. Describe Excess-3 code BTL-1 Remember
16. Summarize about the limitations of Karnaugh map. BTL-2 Remember
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17. Infer AND gate using only NOR gate. BTL-4 Analyze
18. Apply 10’s compliment to subtract 52532 - 3250 BTL-3 Apply
19. Give the Truth Table of XOR gate. BTL-2 Understand
20. Solve the following:
(i)(1001010.1101001)2 to base 16
(ii)(231.07)8 to base 10 BTL-3 Apply
PART – B
1 i) Define K-map and simplify
F(A,B,C,D)=∑(0,1,2,5,8,9,10) in sum of products
and product of sum using K-map. (10)
ii) Describe negative and positive logic. (3)
BTL-1 Remember
2 Discuss the following switching functions using K-map
F(A,B,C,D)= ∑(0,3,5,7,8,9,10,12,15) (8)
(ii)Realize the above expression using logic gates. (5)
BTL-2 Understand
3 Describe the MSP form of the switching function
F(a,b,c,d)=_(0,2,4,6,8)+_d(10,11,12,13,14,15) (8)
ii) Check if NOR Operator is associative. (5) BTL-1 Remember
4 i)Apply the switching function
f(x,y,z)= ∑m(0,1,3,4,12,14,15) using NAND gate. (8)
(ii)Check if NAND operator is associative. (5)
BTL-3 Apply
5
5
Explain the following Boolean expression in
Product-of –sum and Sum-of –product using Karnaugh
map for AC’ + B’D + A’CD + ABCD. (13)
BTL-4 Analyze
6
Assess the following function in sum of min-terms and
product of max terms F(x,y,z)=x+yz. (13)
BTL-5 Evaluate
7
7
i)Discuss and minimize the following expression using
Karnaugh map.
Y=A’BC’D’+A’BC’D+ABC’D’+AB’C’D+A’B’CD’ (10)
ii)State and prove DeMorgan’s theorem. (3)
BTL-2 Understand
8
Point out the rules for Binary Addition and Subtraction
using 2’s complement arithmetic. Give examples. (13) BTL-4 Analyze
9
i) Develop the Boolean function in Sum of
Products(SOP)
F(w,x,y,z)=∑m(0,1,2,5,8,9,10). (5)
(ii) Design the Boolean function in karnaugh map and
simplify it F(w,x,y,z)=∑m(0,1,2,4,5,6,8,9,12,13,14) (8)
BTL-6 Create
10 Examine the following expression and implement
them with two level NAND gates circuits:
(i)AB’+ABD+ABD’+A’C’D’+A’BC’ (7)
(ii)BD+BCD’+AB’C’D’ (6)
BTL-1 Remember
11
Analyze the following expression in SOP and POS
i) X’Z’+Y’Z’+YZ’+XY (7)
ii) (A’+B’+D’)(A+B’+C’)(A’+B+D’)(B+C’+D’) (6)
BTL-4 Analyze
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12
Express the following function in a simplified manner
using K map technique.
(i) G=πM(0,1,3,7,9,11) (5)
(ii) f(W,X,Y,Z)=∑m(0,7,8,9,10,12) + ∑d(2,5,13) (8)
BTL-2 Understand
13
(i)Describe about Common postulates used to
formulate various algebraic structures with example. (6)
(ii)Convert the following logic system into NAND
gates only. (7)
BTL-1 Remember
14
Solve the following using Boolean theorems and
Demorgans law
(i)F=(((A’.B’)’).(B’+C’)) (4)
(ii)F2=((A’+C).((AB)’)) (3)
(iii)AB+A’C+BC=AB+A’C (3)
(iv)A’BD’+BCD+ABC’+AB’D (3)
BTL-3 Apply
PART-C
1 Analyze the expression using Quine
McCluskey(Tabulation ) method.
F(x1,x2,x3,x4,x5)=∑m(0,2,4,5,6,7,8,10,14,17,18,21,31)
+ ∑d(11,20,22) (15)
BTL-4 Analyze
2 (i) Summarize in detail about prime implicant and
essential prime implicants. (5)
(ii) Describe the procedure obtaining logic diagram
with NAND gates from a Boolean function. (10)
BTL-5 Evaluate
3 Formulate the Boolean theorems and prove the
following. (15)
i) A+BA=A (3)
ii) A+A’B=A+B (3)
iii) AB+BC+B’C=AB+C (3)
iii) (A+B)(A+C)=A+BC (3)
iv) ABC+AB’C+A’BC+AB’C’+ABC’+A’BC’ (3)
BTL-6 Create
4 Deduce the following Boolean expressions to a
minimum number of literals: (15)
(i) AC + ABC + AC. (5)
(ii) XYZ + XY + XY Z . (5)
(iii) A B + ABD + AB D + ACD + ABC. (5)
BTL-5 Evaluate
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UNIT II
COMBINATIONAL LOGIC: Combinational Circuits – Analysis and Design Procedures - Binary Adder- Subtractor - Decimal Adder - Binary Multiplier - Magnitude Comparator - Decoders – Encoders – Multiplexers - Introduction to HDL – HDL Models of Combinational circuits.
PART – A
Q.
No Questions BT Level Competence
1 Define Combinational Circuits. BTL-1 Remember
2 Tabulate the TT for the Half adder and write the expression
for the sum and carry. BTL-1 Remember
3 Deduce the Truth table for full subtractor. BTL-5 Evaluate
4 What is full adder? Draw the logic diagram of Full adder
basic gates. BTL-1 Remember
5 Apply NAND gate for designing Half subtractor. BTL-3 Apply
6 Explain Binary Decoder. Draw the block diagram and truth
table for 2X4 decoder. BTL-5 Evaluate
7 Illustrate the TT for the half subtractor. BTL-3 Apply
8 Define Magnitude Comparator. BTL -1 Remember
9 Differentiate parallel and serial adder. BTL-4 Analyze
10 Design the combinational circuits with 3 inputs and 1 output.
The output is 1 when the binary value of the inputs is less
than 3.The output is 0 otherwise. BTL-6 Create
11 Given the input frequency of a 7497 binary rate multipliers is
64 kHz. Measure its output be if the multiplier word is 1011? BTL-2 Understand
12 Analyze the function G=∑m (0, 3) using 2 X4 decoder.
Differentiate Decoder and Demultiplexer. BTL-4 Analyze
13 Develop a full adder with 4 X1 MUX. BTL-6 Create 14 Define Priority encoder. BTL-1 Remember 15 Define Mux. Draw the circuit for a 2-to -1 line Multiplexer. BTL-1 Remember 16 Discuss about HDL and Test Bench. BTL-2 Remember 17 Explain the HDL description for the following circuit and
give the advantage of HDL.
BTL-4 Analyze
18 Discuss the application of Mux and implement the following
Boolean function using 8:1 Mux F(A,B,C) =∑m(1,3,5,6). BTL-2 Understand
19 Express the Data flow description of a 4 bit comparator. BTL-2 Understand
A
B g1
C y
x
e
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20 Show the circuits for 2 to 1 multiplexer. BTL-3 Apply
PART – B
1
i) Examine a full adder with inputs X,Y,Z and two outputs S
and C .The circuits performs X+Y+Z,.Z is the input carry ,C
is the output carry and S is the sum. (8)
(ii)Draw the full adder using NAND Gate. (5)
BTL-1 Remember
2
i) Express a logic circuit that accepts a 4 bit gray code and
converts it into 4 bit binary code. (8)
ii) Design a binary multiplier. (5)
BTL-2 Understand
3
Describe and design a combinational circuit to convert binary
to gray. (13)
BTL-1 Remember
4 Solve a combinational circuit to convert 8421 BCD code to
Excess 3 code. (13) BTL-3 Apply
5
i) Explain the Analysis procedure. Analyze the following
logic diagram. (6)
ii) With a neat diagram explain the 4 bit adder with carry
look ahead. (7)
BTL-4 Analyze
6
i)Explain BCD adder. (6)
ii) Design a full 4 bit adder using three full adders and 1 half
adder. (7) BTL-5 Evaluate
7
i) Discuss Full subtractor. (6)
ii) Design a code convertor that converts 8421
to BCD code. (7) BTL-2 Understand
8
i) Compare and Contrast between the encoder and the
multiplexer. (6)
ii) Analyse HDL models for combinational circuits. (7)
BTL-4 Analyze
9
i)Develop the following Boolean function using 8 to 1
multiplexer.
F(A,B,C,D)=A’BD’ + ACD + B’CD + A’C’D. (6)
ii) Implement the function using 16 to 1 multiplexer. (7)
BTL-6 Create
10
i)Examine the following Boolean Functions with the Mux
F(w,x,y,z)= ∑(2,3,5,6,11,14,15). (6)
ii) Construct a 5 to 32 line decoder using 3 to 8 line decoder
and 2 to 4 line decoder. (7)
BTL-1 Remember
11
i)Explain about Data Flow modelling. (5)
ii)Implement the following switching function with the
8 input Mux:
F(w,x,y,z)= ∑m(0,1,3,4,12,14,15). (8)
BTL-4 Analyze
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12
Discuss the Analysis procedure. Analyze the following logic
diagram. (13)
BTL-2 Understand
13
(i)Describe a 2 bit magnitude Comparator. (8)
(ii) Write a Verilog HDL code for 2 bit magnitude
Comparator. (5)
BTL-1 Remember
14
i) Demonstrate the VHDL code for the BCD to 7 segment
code convertors using a selected signal assignment. (8)
ii) Write test bench for half adder circuit. (5) BTL-3 Apply
PART-C
1
i)Design and analyse a 8421 to gray code converter and
convert it using only NAND gate. (8)
ii)Design an magnitude comparator. (7) BTL-4 Analyze
2
i)Summarize the procedure to build a 4-to-16 decoder, using
only 2-to-4 decoders. (8)
ii) Design half adder and Half subtractor. (7)
BTL-5 Evaluate
3 Design a Full adder, Full subtractor, Multiplexer and write a
HDL program module for the same. (15) BTL-6 Create
4
i) Explain the steps involved in designing BCD to 7- Segment
code converter. (8)
ii) Design an encoder and implement using gates. (7) BTL-5 Evaluate
UNIT III
SYNCHRONOUS SEQUENTIAL LOGIC: Sequential Circuits - Storage Elements: Latches , Flip-Flops - Analysis of Clocked Sequential Circuits - State Reduction and Assignment - Design Procedure - Registers and Counters - HDL Models of Sequential Circuits.
A
B
C
D
F
G
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PART – A
Q.
N
o
Questions BT Level Competence
1 Tabulate the excitation table of JK flip flop. BTL-1 Remember 2 What is the operation of JK Flip flop and write down its
characteristic equation. BTL-1 Remember
3 Deduce many logic devices are required for a MOD-64 parallel
counter. BTL-5 Evaluate
4 Define Race around Condition. BTL-1 Remember 5 Show how many FF are required to construct a binary counter
that counts from 0 to 1023? BTL-3 Apply
6 Explain Shift register. BTL-5 Evaluate 7 Examine a Ring counter. BTL-3 Apply 8 List the application of Shift register. BTL -1 Remember 9 Point out the working of T-flip flop with the diagram. BTL-4 Analyze
10 Design the number of states in a 3bit ring counter. BTL-6 Create 11 Develop the block diagram of Master slave D Flip flop. BTL-6 Create 12 Design a 4 bit binary synchronous counter with D flip flops. BTL-4 Analyze 13 Distinguish between FF and latch. BTL-2 Understand
14 Define Ring counter. BTL-1 Remember 15 List the difference between D latch and SR latch. BTL-1 Remember 16 Explain Ripple counter. BTL-2 Remember 17 Differentiate Moore and Mealy circuit. BTL-4 Analyze 18 Describe how T-FF is converted into D-FF. BTL-2 Understand
19 Discuss edge triggered Flip-flop. BTL-2 Understand 20 Show how the synchronous counter differs from asynchronous
counter. BTL-3 Apply
PART-B
1 Design and describe a binary counter using T-flip-flop which
counts in the sequence.
i)000,001,010,011,100,101,111,000 (7)
ii)000,100,111,010,011,000 (6)
BTL-1 Remember
2 Design a three bit synchronous counter with T flip flop and
draw the diagram. (13) BTL-2 Understand
3 Consider the design of 4-bit BCD counter that counts in the
following way:
0000, 0001, 0010... 1001 and back to 0000.Draw the logic
diagram of this circuit and describe it. (13)
BTL-1 Remember
4 i) Illustrate a shift register using JK flipflop. (5)
ii)Design and demonstrate T flip flop using D flipflop and Jk
flipflop using D flipflop. (8)
BTL-3 Apply
5 i) Draw the logical diagram of priority encoder and
explain. (7)
ii) Explain mealy and moore models. (6)
BTL-4 Analyze
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6 i) Compare state table, characteristic table and an excitation
table. (7)
ii) Summarize on programmable logical device with examples.
(6)
BTL-5 Evaluate
7 Discuss about modulo 5 synchronous counter using JK Flip Flop
and implement it. Construct its timing diagram. (13)
BTL-2 Understand
8 i) Write and Analyze the HDL description of T-flipflop and JK
flipflop from D flipflop and gates. (7)
ii) Pointout the behavioural modelling in HDL for sequential
logical circuit. (6)
BTL-4 Analyze
9 Design a synchronous counter which counts in the sequence
000,001,010,011,100,101,110,111,000 using D-FF. (13) BTL-6 Create
10 Describe a sequence detector that detects a sequence of three or
more consecutive 1’s in a string of bits coming through an input
line and produce s an output whenever this sequence is
detected. (13)
BTL-1 Remember
11 i)Design a modulo 5 synchronous counter using JK flip flop and
Analyze it. Construct its timing diagram. (7)
ii) Analyze Mod-7 counter using JK flip-flop. (6)
BTL-4 Analyze
12 i)Discuss JK flip flop using Dflip flop. (7)
ii) How the race condition can be avoided in a flip flop. (6) BTL-2 Understand
13 i) Describe the operation of JK FF, SR-FF,T-FF and D-FF with
a neat diagram. (7)
ii) Describe their characteristics and excitation table. (6)
BTL-1 Remember
14 Analyze the following clocked sequential circuit and obtain the
state equations and state diagram. (13)
BTL-3 Apply
PART-C
1 Analyze and Design a synchronous counter which counts in the
sequence. 000,001,010,011,100,101,110,111,000 using D
flipflop. (15) BTL-4 Analyze
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2 Assess and Design a synchronous counter using JK flipflop to
count the following sequence 7,4,3,1,5,0,7...... (15) BTL-5 Evaluate
3 A sequential circuit with two D flip-flops A and B, one input X,
and one output Z is specified by the following next-state and
output equations:
A(t+1)=A'+B, B(t+1)=B'x, Z=A=B'
(1)Design the logical diagram of the circuit. (5)
(2)Derive the state table. (5)
(3)Draw the sate diagram of the circuit. (5)
BTL-6 Create
4 Design and explain the sequential circuit for the state diagram
shown below. Use JK flip-flop. (15)
BTL-5 Evaluate
UNIT IV
ASYNCHRONOUS SEQUENTIAL LOGIC: Analysis and Design of Asynchronous Sequential Circuits – Reduction of State and Flow Tables – Race-free State Assignment – Hazards.
PART – A
Q.No Questions BT Level Competence
1 Define critical race condition. Give example. BTL-1 Remember
2 Name the two types of asynchronous sequential circuits. BTL-1 Remember
3 Compare critical rate and non critical rate. BTL-5 Evaluate
4 Define hazard. BTL-1 Remember
5 Show the need of state reduction in sequential circuit
design. BTL-3 Apply
6 Explain Flow table. BTL-5 Evaluate
7 Illustrate the fundamental mode of operation. BTL-3 Apply
8 List the types of hazards. BTL -1 Remember
9 Pointout the procedure for designing asynchronous
sequential circuit. BTL-4 Analyze
10 Design the wave forms showing static 1 hazard. BTL-6 Create
11 Distinguish between the stable state and the unstable
state. BTL-2 Understand
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12 Differentiate conventional flow chart and an ASM
chart. BTL-4 Analyze
13 Generalize about fundamental mode circuits and pulse-
mode circuits. BTL-6 Create
14 Define Shared Row method. BTL-1 Remember
15 What happens when a hazard happens in a logical
circuit? BTL-1 Remember
16 Summarize about State Assignment. BTL-2 Remember
17 Explain Multiple row method. BTL-4 Analyze
18 Distinguish static ‘1’ and static ‘0’ hazards. BTL-2 Understand
19 Give reason why the pulse mode operation of
asynchronous is sequential circuits not very popular? BTL-2 Understand
20 Show the block diagram of an asynchronous sequential
circuit. BTL-3 Apply
PART – B
1 i) List the steps to analyse the asynchronous sequential
circuit. (5)
ii) Describe the fundamental mode sequential circuit. (8)
BTL-1 Remember
2 (i)Discuss in detail the procedure for reducing the flow
table with an example. (7)
ii) Discuss the steps for designing of asynchronous
sequential circuits. (6)
BTL-2 Understand
3 For a given Boolean function obtain the hazard free
circuit and examine it.
F(A,B,C,D)= Σm(1,3,6,7,13,15) (13) BTL-1 Remember
4 Design and demonstrate an asynchronous sequential circuit with inputs x1 and x2 and one output z. Initially and at any time if both the inputs are 0, output is equal to
BTL-3 Apply
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0. When x1 or x2 becomes 1, z becomes 1. When second input also becomes 1, z=0; the output stays at 0 until circuit goes back to initial state. (Nov/Dec 2013) (13)
5 i) Explain how ASM charts are used to design an
asynchronous sequential circuit with example. (7)
ii) Draw the ACM chart for a mod-5 counter. (6)
BTL-4 Analyze
6 Assess and Design an asynchronous sequential circuit
with 2 inputs X and Y and with one output Z Wherever
Y is 1, input X is transferred to Z. When Y is 0; the
output does not change for any change in X. Use D-
flipflop . (13)
BTL-5 Evaluate
7 Discuss about the following that occur in an asychronous
sequential circuit with example:
(i)Race condition.(5)
(ii)Hazards.(5)
(iii) Cycle.(3)
BTL-2 Understand
8 (i)Explain in detail about the static hazard. (7)
(ii)Explain in detail about the dynamic hazard. (6) BTL-4 Analyze
9 i) Design an asynchronous sequential circuit with 2
inputs X and Y and with one output Z Wherever Y is 1,
input X is transferred to Z. When Y is 0; the output does
not change for any change in X. Use SR latch for
implementation of the circuit. (7)
ii) Compose the types of races and explain it. (6)
BTL-6 Create
10 i)What is the objective of state assignment in
asynchronous circuit? Explain race-free state
assignment with an example. (7)
ii) Describe about static, dynamic and essential hazards
in asynchronous sequential circuits. (6)
BTL-1 Remember
11 i) Design and Analyze asynchronous serial parity
generator with proper state assignment procedure. (7)
ii) Write a note on pulsed mode and fundamental
asynchronous sequential circuit. (6)
BTL-4 Analyze
12 Discuss the types of hazards in combinational circuits
and sequential circuits and also demonstrate a hazard and
its removal with example. (13)
BTL-2 Understand
13 (i)Describe What is the objective of state assignment in
asynchronous circuit? (7)
ii) Explain race-free state assignment with an
example. (6)
BTL-1 Remember
14 Implement and illustrate the switching function
F=Σm(1,3,5,7,8,9,14,15) by a static hazard free 2 level
AND-OR gate network. (13) BTL-3 Apply
PART-C
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1 Analyze and Design asynchronous circuit that has 2 input X2 and X1 and output Z. When X1 =0, Z=0. The first change is X2 that occurs while X1 is 1 will cause output Z to be 1. The output Z will remain 1 until X1 returns to 0. (15)
BTL-4 Analyze
2 An asynchronous sequential circuit is described by the
following excitation and output function.
Y=X1X2+(X1+X2)Y
Z=Y
(i) Draw the logic diagram of the circuit. (5)
(ii) Deduce the transition table and output map. (5)
(iii)Describe the behaviour of the circuit. (5)
BTL-5 Evaluate
3 i)Generalize about Race-free state assignment
procedure. (7)
(ii) Reduce the number of states in the following state
diagram. Tabulate the reduced state table and draw the
reduced state diagram. (8)
Presen
t State
Next State Output
x=0 x=1 x=0 x=1
a a b 0 0
b c d 0 0
c a d 0 0
d e f 0 1
e a f 0 1
f g f 0 1
g a f 0 1
BTL-6 Create
4
Implement the switching function
F=∑m(1,3,5,7,8,9,14,15) by a static hazard free two
level AND OR gate network and explain it. (15) BTL-5 Evaluate
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UNIT V
MEMORY AND PROGRAMMABLE LOGIC:RAM – Memory Decoding – Error
Detection and Correction - ROM - Programmable Logic Array – Programmable Array
Logic – Sequential Programmable Devices.
PART – A
Q.N
o
Questions BT
Level
Competence
1 Define RAM and its types. BTL-1 Remember
2 List the Read and write operation for RAM. BTL-1 Remember
3 Explain ROM and draw its block diagram. BTL-5 Evaluate
4 Define PROM, EPROM and EEPROM. BTL-1 Remember
5 Demonstrate why memory decoding is needed. BTL-3 Apply
6 Explain hamming code. BTL-5 Evaluate
7 Illustrate the various types of ROM. BTL-3 Apply
8 List the three types of PLD. BTL -1 Remember
9 Point out the programmable array logic (PAL). BTL-4 Analyze
10 Formulate the programmable logic array (PLA). BTL-6 Create
11 Express what a sequential programmable device is. BTL-2 Understand
12 Point out in detail about various types of sequential
programmable device. BTL-4 Analyze
13 Design the block diagram of CPLD. BTL-6 Create
14 Describe FPGA. BTL-1 Remember
15 Define SPLD. BTL-1 Remember
16 Differentiate PLA and PAL. BTL-2 Remember
17 Explain Error Detecting code. BTL-4 Analyze
18 Distinguish between SRAM and DRAM. BTL-2 Understand
19
Give the maximum range of memory that can be accessed
using 10 address Lines.
BTL-2
Understand
20 Demonstrate Error correction code. BTL-3 Apply
PART – B
1 i)Describe in detail about the classification
of memory. (7)
ii) Examine in detail about error correction. (6)
BTL-1 Remember
2 i)Summarize the memory decoding with diagram. (7)
ii) Discuss in detail about ROM. (6) BTL-2 Understand
3 i) Describe the hamming code with example. (5)
ii) List the steps to encode the binary 1011 using 7 bit
Hamming code. (8) BTL-1 Remember
4 i)Apply the 12-bit hamming code received is
101110000110.Check for errors. What is the correct
information transmitted. (7)
ii) Discuss sequential programmable device. (6) BTL-3 Apply
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5 i) Explain PLA. (3)
ii)A combinational circuit is defined by the functions.
F1=Σm(3,5,7)
F2=Σm(4,5,7)
ii)Analyse the circuit with a PLA having 3 inputs, 3
product terms and 2 outputs. (10)
BTL-4 Analyze
6 Deduce the PLA for the following: (13)
F1(a,b,c)=Σm(0,1,3,4)
F2(a,b,c)= Σm(1,2,3,4,5)
BTL-5 Evaluate
7 i) Discuss the BCD to Excess-3 code converter and
implement using suitable PLA. (8)
ii) Discuss in detail about RAM. (5)
BTL-2 Understand
8 Analyze the following multi-boolean function using
3 *4*2 PLA. (13)
F1(a2,a1,a0)=Σm(0,1,3,5)
F2(a2,a1,a0)= Σm(3,5,7)
BTL-4 Analyze
9 Formulate the switching function
Z1 = abde+abcde+bc+de
Z2=ace
Z3=bc+de+cde+bd
Z4=ace+ce
Using a 5 X 8 X 4 programmable logic array. (13)
BTL-6 Create
10 i) Examine the PAL with suitable example. (7)
ii) Describe the various types of PLD. (6) BTL-1 Remember
11 i)Explain with an example the error detection
technique. (3)
ii)Analyse PAL for the following: (10)
A(x,y,z)= ∑m(1,2,4,6)
B(x,y,z)= ∑m(0,1,6,7)
C(x,y,z)= ∑m(2,6)
D (x,y,z)= ∑m(1,2,3,5,7)
BTL-4 Analyze
12 Discuss the following messages have been coded in the
even parity hamming code and transmitted through a
noisy channel. Decode the messages, assuming that a
most a single error has occurred in each
code word. (13)
i) 1001001
ii) 0111001
iii) 1110110
iv) 0011011
BTL-2 Understand
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13 Describe the minimum sum of products expression for
each of two function F and G, minimizing them
individually.
F=WY’ + XY’Z
G=WX’Y’+X’Y+W’Y’Z
i) Implement them with a ROM. (7)
ii) Implement them in the PLA. (6)
BTL-1 Remember
14 Illuatrate with an example about the working and
application of semi-conductor memories. (13) BTL-3 Apply
PART-C
1 Draw and analyse a neat sketch showing implementation
of Z1=ab’d’e+a’b’c’e+bc+de, (15)
Z2=a’c’e
Z3=bc+de+c’d’e
Z4=a’c’e+ce using 5*8*4 PLA.
BTL-4 Analyse
2 Design using PLA. (15)
A(x,y,z)=∑m(1,2,4,6)
B(x,y,z)=∑m(0,1,6,7)
C(x,y,z)=∑m(2,6)
BTL-6 Create
3 Explain a combinational circuit using ROM that accepts
a three bit binary number and outputs a binary number
equal to the square of the input number. (15) BTL-5 Evaluate
4 Implement the following Boolean function using
PAL. (15)
W(A,B,C,D)= ∑m(0,2,6,7,8,9,12,13)
x(A,B,C.D)= ∑m(0,2,6,7,8,9,12,13,14)
y(A,B,C.D)= ∑m(2,3,8,9,10,12,13)
z(A,B,C.D)= ∑m(1,3,4,6,9,12,14)
BTL-5 Evaluate
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