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Variation immunity in sub-threshold operationPatricia GonzalezDivya AkellaVLSI Class ProjectMotivation : Sub-threshold Operation Sub-threshold processor which runs on 180mV [1]Sub-threshold FPGAs A sub-VT ring oscillator at 80mV [2].A 65nm chip : 256kb memory in sub-threshold region to below 400mV [3]New wireless applications : Wearable body sensor node (19uW) running on harvested energy small devices, long lifetimes!

Ultimate aim ? Reduce Power consumption! Variation In sub-threshold

Taken from [1] B. CalhounIssue : Meet Throughput100 operations every 5 seconds -> Frequency requirementExtract ECG : Some chips will met the requirement some chips wont 3Motivation : Yield a critical obstacle : sensitivity of sub-threshold circuits to variations in process, voltage, and temperature (PVT)Affects delay : limits product yield ! A system that adjusts the chip operation to account for PVT ?Motivation : Razor System should be able to run at multiple frequencies and voltages. Design to ensure correct operation at all PVT variations. Variations ? Environmental, local, global, voltage droops, even data dependent!

Razor approach : DVS based on dynamic detection of errors

Motivation : PDVSVoltage reduced to minimum voltage possible. Headers allow to dither between voltages. Different energies for different modes of operation/workload!

The Problem

First high input is caught by the flop : seen at output QSecond high input is missed ? Test circuit

To experiment with this problem : chose a 3 bit adderOutput is shown to be flopped Solution

Shadow latch Error comparator Waveform

System

Overhead ? Power consumption of razor circuit :

Worst case (FF) corner power at 0.4 V = 1.4 nW Further optimization is definitely possible!

Use of razor circuit only for critical paths

Design Typically corner analysis to select a supply voltage ? Extra margin for worst case scenario! What if variability is rare , what if it never occurs ?In lower processes and sub threshold , variability might be so much voltage margins go up!

Optimization during circuit design can now be done for a typical caseWe attempt to show use of razor in sub-threshold voltages.

Savings example (T = 20C)V (3 freq of operation)% savings0.431.81%0.42521.99%0.4514.21%0.4750.538.21%0.5525.49%0.618.32%0.650.742.49%0.829.24%0.915.08%1A Perspective of Yield Variable voltage and frequency to adjust to variation It will improve the efficiency, thereby increasing yield and lowering costs.Achievable performance for a given energy budgetImprove yield at a given frequency by allowing slower chips to speed up by going to higher VDD

Yield against process variation !!40 MHz200 kHz100 kHz[1] Wang, A.; Chandrakasan, A.; , "A 180mV FFT processor using subthreshold circuit techniques," Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International , vol., no., pp. 292- 529 Vol.1, 15-19 Feb. 2004

2] B. H. Calhoun and A. Chandrakasan, Characterizing andModeling Minimum Energy Operation for Subthreshold Circuits, in ISLPED, 2004, pp. 9095.

[3] B. Zhai, et al., Theoretical and Practical Limits of DynamicVoltage Scaling, in DAC, 2004, pp. 868873.

[4] Dan Ernst, Tao Phan. Razor : A low power pipeline based on Circuit Level timming speculation.

[5] Mathias Eireiner,. In situ Delay Characterization and Local Supply voltage adjustment for compensation of local parameter variations.

ReferencesGate leakage based timer :

Intended to use it as a clock sourceDid not integrate into the systemOriginally, used as a timer in the sub Hz rangeGate leakage based system variation with temperature is reducedFound that with varying capacitance charging time, leakage transistors and Schmitt trigger design higher frequency ranges can be obtained.

VoltageTime periodFrequency0.4 3.71E-07 2.70E+060.5 5.65E-08 1.77E+070.6 1.40E-08 7.16E+070.7 5.16E-09 1.94E+080.8 2.54E-09 3.94E+080.9 1.54E-09 6.48E+08Can be used as an unstable source of clock on chip, with possible caliberation with a stable clock source.