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VCO Design Project ECE 712

05/06/11

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Table of Contents

Executive Summary ................................................................................................................................. 3

Design Overview...................................................................................................................................... 3

Varactors ............................................................................................................................................. 4

Band tuning capacitors and switches ................................................................................................... 4

VCO buffer........................................................................................................................................... 4

Table 1 Target vs. Actual Specifications.................................................................................................... 5

Table 2 Noise Summary ........................................................................................................................... 5

Discussion ............................................................................................................................................... 6

Key Noise Contributors ........................................................................................................................ 6

Worst-case Performance ..................................................................................................................... 6

Supply Pushing .................................................................................................................................... 6

Temperature Effects ............................................................................................................................ 6

Conclusion ............................................................................................................................................... 7

Figures .................................................................................................................................................... 7

References ............................................................................................................................................ 27

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Executive Summary We designed a voltage controlled oscillator (VCO) in 180nm technology. The VCO is a cross-coupled

oscillator with both PMOS and NMOS active elements. This configuration was selected due to ease of

oscillation and a relatively straightforward design approach. Tuning range was achieved with a 16-band

digitally switched capacitor bank having low VCO gain. Inversion mode PMOS capacitors were used for

fine tuning. The frequency dependence on supply voltage was reduced as much as possible by

employing a self-biased current source. The VCO has an 18% tuning range of 5 to 6GHz with a worst-case

phase noise of -114.9 dBc at 1MHz offset, 1.5 V worst-case peak to peak differential swing, less than 38

MHz/V supply pushing response, and 8.6 mW power consumption at 1.8 V.

Design Overview The VCO design process involved the following stages:

1. Design of the VCO tank

a. Design of the inductor including parasitics

b. Design of the varactor

c. Design of band capacitors and switches

2. Design of the cross-coupled amplifier pair and the tail current source.

3. Design of the VCO buffer

4. Design of the bias network

5. Additional noise optimization (low-pass filters, etc.)

As a starting point, it made sense to design the VCO core to oscillate slightly above 6 GHz; tuning

capacitors would then be added later in the design to vary the frequency to as low as 5 GHz. Rather than

simulate inductor Q with an ideal inductor and series resistor, an actual model was obtained from ASITIC

at the outset. This approach accounted for the effects of parasitic RC components on output frequency

and phase noise. The inductor design is symmetrical (differential).

An inductor value was assumed and then the corresponding capacitance was calculated for 6.1 GHz

from ω0 = 1/ √ (LC). In a second iteration, the inductor value was halved to accommodate additional

capacitance from a new output buffer design. The original output buffer was a tuned-LC cascode

amplifier with minimal capacitive loading, high input-output isolation, and wide swing. This buffer was

traded for a design without an inductor.

The core transistors were initially sized minimally to reduce the addition of their capacitance to the fixed

capacitance calculated above. Once oscillation was established, transistors were then sized optimally

while adjusting the fixed capacitor accordingly. The active-element NMOS transistors contributed

significant thermal noise. This noise was minimized by reducing width and number of fingers, effectively

reducing gm in the thermal noise equation: ind2 = 4kT·(2/3)·gm·Δf.

The tail transistor was sized to provide sufficient current for output swing and phase-noise reduction. It

also appeared that operating the tail transistor in triode reduced supply pushing, possibly from reduced

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effect of Vgs on current through the transistor. The tail current and other bias transistors generated high

amounts of phase noise. Flicker noise was reduced in all major contributors by proportionally increasing

both width and length of each device. This result is reflected in the inverse relationship of WL to flicker

noise: vn2 = [KF/(WLCox)]·(1/f)·Δf. An RC low-pass filter (Fig 4) was added between the current-source bias

network and the VCO to reduce noise from the bias network. Finally, an LC pair was added at the drain

of the current-source transistor (Fig 4) to further block noise from the VCO core.

Varactors The variable capacitance necessary for fine tuning was realized using two PMOS inversion mode

varactors. The PMOS varactor was chosen instead of the NMOS because it is less sensitive to substrate

induced noise [1]. Ordinarily, a MOS varactor yields a non-monotonic response when the tuning voltage

is varied. In order to achieve a monotonic response, the body of the PMOS varactor is tied to the supply

voltage. This step keeps Vbg > Vt for a wide range of tuning voltage. The variation of capacitance with

tuning voltage is shown in Fig 17. The Q-factor of the varactors is shown in Fig 18. The very high Q-factor

probably comes from an inaccurate model. In order to isolate the DC operating point of the varactor

from the rest of the VCO circuit, two fixed capacitors were connected in series with the varactors as

shown in Fig 9. The DC operating-point of the varactor gate terminals were set to zero by connecting

them to the ground with two 3K Ohm resistors. The resistors provide RF isolation between ground and

the varactor gates.

The value of the varactors were determined by the ratio of variable to fixed capacitance, which in turn is

determined by the tuning range, the required overlap between the tuning bands, the desired VCO gain,

and the fixed parasitic capacitance added by the transistors.

Band tuning capacitors and switches In order to obtain a low VCO gain and still cover the full tuning range, digitally switched capacitors were

implemented in the VCO tank. Four sets of capacitors, approximately binary weighted, were employed,

resulting in 16-band tuning. Implementing a higher number of bands provides better overlap between

the bands; on the downside it adds some fixed capacitance from the pass transistor switches. The

capacitors used were of Metal Insulator Metal (MIM) type. Initially, the capacitor values were selected

as binary weighted, but then were adjusted for improved overlap.

The band switches were designed using NMOS pass gates. The NMOS pass-gate sizes were also binary

weighted initially, but were adjusted along with the capacitors. The source and drain of the NMOS pass-

gates were biased at DC ground, to keep them on when the output of the oscillator swings to extreme

values and also to avoid high currents between source-bulk and drain-bulk junctions. Similar to what

was done with the varactors, the source and drain terminals were connected to ground using two 3K-

ohm resistors, which provide RF isolation.

VCO buffer A White follower or push-pull amplifier configuration was employed as the output stage, driving a 300 fF

load-capacitor at each output node. The White follower usually gives better swing range than the source

follower configuration. The bias points of the two NMOS pairs in the White follower was determined by

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the required output swing (single-ended) at the buffer output and also by the output swing of the core

VCO. The bias voltage for the lower NMOS transistor was generated using the same bias network that

supplies the VCO tail transistor (Fig 4). The bias voltage for the upper NMOS was found to be near 1.2V;

hence, the provided bandgap voltage-source was used.

The two NMOS transistors of each White follower are driven by the VCO output in a complimentary

fashion. The lower NMOS is connected to the positive VCO output and the upper NMOS is connected to

the negative VCO output for one buffer, and vice versa for the other buffer.

A 10pF MIM capacitor was used for RF input into the buffers to block DC. The buffer bias network was

isolated from the RF signal using a 3K Ohm resistor (Fig 6).

Table 1 Target vs. Actual Specifications Specifications Target Values Actual Values

Tuning Range 18% (5-6 GHz) 18% (5.005 – 6.004 GHz)

Phase Noise < -110 dBc/Hz at 1 MHz offset -114.9 worst case

Power Consumption < 10 mW 8.6 mW

VCO Gain < 1.5 GHz/V < 364 MHz/V

Band overlap > 40% > 40%

Supply pushing Lowest possible < 38 MHz/V

Output swing 1.5 V ppd 1.5 V ppd worst case

Load capacitance 300 fF 300 fF

Table 2 Noise Summary Device Noise Type Noise Contribution (V2/Hz) % of Total

Fig 9, R6 rs 2.316e-13 17.16

Fig 9, R7 rs 2.269e-13 16.81

Fig 15, MN0 fn 1.115e-13 8.26

Fig 4, MN1.m0 id 7.391e-14 5.47

Fig 4, MN0.m0 id 7.238e-14 5.36

Fig10, R0 rn 6.800e-14 5.04

Fig 4, MP1.m0 id 5.648e-14 4.18

Fig 4, MP0.m0 id 5.556e-14 4.12

Fig 4, MN0.m0 fn 4.677e-14 3.46

Fig 4, MN1.m0 fn 4.502e-14 3.33

Fig 15, MP0.m0 fn 3.032e-14 2.25

Fig 15, MP1.m0 fn 2.770e-14 2.05

Fig 6, R0 rs 2.066e-14 1.53

Fig 6, R0 rs 1.967e-14 1.46

Fig 10, R1 rn 1.963e-14 1.45

Total All 1.35e-12 82

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Discussion

Key Noise Contributors The main noise contributors in the current design appear in Table 2. Before optimization, the main noise

contributors were the NMOS transistors in the VCO core (thermal noise), the tail transistor (flicker

noise), and the bias-network NMOS transistors. Phase noise was minimized using the techniques

described above.

Worst-case Performance Without the varactor, phase noise increases with frequency. Phase-noise relation to frequency is

somewhat less simple once tuning is implemented. Highest phase noise is no longer at the highest

frequency, but where the VCO has the most gain (~ 5.9 GHz). Figs 25-27 show phase noise vs. offset

frequency.

Output swing is lowest at 5 GHz, owing mostly to additional capacitive loading of the output (Fig 30).

In Fig 22, a small ripple is seen in the VCO gain for one band. The cause of the ripple is unknown, but

may be due to numerical resolution of the simulation.

Supply Pushing Supply-pushing response was reduced by more than 50% when a more stable current-source bias

network was added. A current-source design with better supply independence can help to minimize

supply-noise response. Operating the current-source transistor in the triode region also resulted in

significantly less sensitivity to supply noise, possibly owing to diminished modulation of current by Vgs of

the tail transistor. Various nodes connected to the supply were individually tested for sensitivity. The

active-element PMOS transistors at the VCO core have significant impact on output frequency when

noise is introduced at the supply. The voltage at this node may be stabilized with a voltage regulator.

Temperature Effects

At 0° Celsius, the tuning curves shift upward by about 400MHz. The lowest frequency is about

5.4GHz but the highest frequency remains same. At 85° C, the tuning curves shift by about

100MHz down.

The variation is caused by the change of MIM capacitors, MOS capacitors and the inductor with

temperature. Since the inductor is modeled with ideal components, the variations in inductance

may not be accurate. Of MIM capacitors and MOS capacitors, the MIM capacitors would be

more sensitive to temperature variations. Also, the parasitic capacitance added by the

transistors would contribute a small amount in the temperature variation of frequency.

Phase noise changes minimally. At 27° C, worst phase noise is -114.9 dBc/Hz at 1 MHz offset. At

0° C, the value is -115.1 dBc/Hz. The worst-case phase noise at 85° C is -114.1 dBc/Hz. These

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relatively small changes may be attributed to thermal noise which increases linearly with

temperature, as shown in the equation for MOSFET thermal noise: ind2 = 4kT·(2/3)·gm·Δf.

Conclusion The VCO design experience provided a better understanding of key concepts and tradeoffs

involved. The choice of inductor value and Q factor was a major factor as it affected other

design choices like the tuning frequency, the available capacitance and hence the tuning range,

the oscillation amplitude, and the phase noise. The ratio of fixed and variable capacitors affects

the tuning range greatly. The choice of bias points plays a major role in determining the

oscillation amplitude and the phase noise. The power distribution between VCO core stage and

the buffer stage is also an important choice and depends on the load to be driven.

The supply pushing of the VCO is relatively large and is a point for improvement. A better bias

circuit could be designed by using the given bandgap voltage source or by implementing a

voltage regulator in order to achieve a stable supply voltage.

Figures

Fig 1 Top Level

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Fig 2 Top level – DC operating points

Fig 3 VCO

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Fig 4 VCO – DC operating points

Fig 5 Output buffers

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Fig 6 Output buffers – DC operating points

Fig 7 VCO Tank

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Fig 8 “cap bank”

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Fig 9 “Cap bank” – DC operating points

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Fig 10 VCO Inductor

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Fig 11 VCO Inductor – DC operating points

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Fig 12 Source Inductor

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Fig 13 Source Inductor – DC operating points

Fig 14 Current Source Bias

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Fig 15 Current Source Bias – DC operating points

Fig 16 Current-source bias kick-start inverter

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Fig 17 Varactor capacitance vs. tuning voltage

Fig 18 Varactor Q vs. tuning voltage (model not realistic)

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Fig 19 Band-switch capacitance vs. on/off state from (0,0,0,0) to (1.8,1.8,1.8,1.8) in order

Fig 20 Band-switch Q vs. on/off state from (0,0,0,0) to (1.8,1.8,1.8,1.8) in order

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Fig 21 Frequency vs. tuning voltage for 16 bands in order from (0,0,0,0) to (1.8,1.8,1.8,1.8)

Fig 22 VCO gain vs. tuning voltage for 16 bands in order from (0,0,0,0) to (1.8,1.8,1.8,1.8)

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Fig 23 Tuning curves for the 16 bands at 0° C

Fig 24 Tuning curves for the 16 bands at 85° C

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Fig 25 Phase Noise: 5.9 GHz, 27°, highest VCO gain – worst case

Fig 26 Phase Noise: 5GHz, 27°, highest VCO gain – best case

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Fig 27 Phase Noise: 6 GHz, 27°, highest VCO gain – typical

Fig 28 Phase Noise: 5.9 GHz, 0°, highest VCO gain – worst case

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Fig 29 Phase Noise: 5.9 GHz, 85°, highest VCO gain – worst case

Fig 30 Output swing: 5 GHz – worst case

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Fig 31: Output swing: 5.9 GHz – best case

Fig 32 Output swing: 5.51 GHz – typical

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Fig 33 Supply-Pushing: Frequency vs. Vdd

Fig 34 Supply pushing at Vdd (MHz/V)

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References

Andreani, P. et al. 2000. On the Use of MOS Varactors in RF VCO’s. IEEE Journal of Solid-State Circuits

35(6): 905-910.