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VEDIC MULTIPLIER FOR "FPGA"

Date post: 21-May-2015
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Vedic multiplier for FPGA based on arthimatic ckt
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Page 1: VEDIC MULTIPLIER FOR "FPGA"
Page 2: VEDIC MULTIPLIER FOR "FPGA"

The proposed Vedic multiplier is based on the

Vedic Sutras "Urdhva Tiryagbhyam Sutra” and “Nikhilam Sutra" multiplication techniques.

These Sutras have been traditionally used for the multiplication of two numbers in the decimal number system

Page 3: VEDIC MULTIPLIER FOR "FPGA"

• It multiples two numbers & adds It with accumulator register.

• The output of the register given to one input of adder.

• Computes the product much quicker than conventional shifting & adding.

Page 4: VEDIC MULTIPLIER FOR "FPGA"

Vedic Multiplier Architecture

Page 5: VEDIC MULTIPLIER FOR "FPGA"
Page 6: VEDIC MULTIPLIER FOR "FPGA"
Page 7: VEDIC MULTIPLIER FOR "FPGA"
Page 8: VEDIC MULTIPLIER FOR "FPGA"

It is faster than the booth & array multiplier…

The area needed for this very small as compared to other multiplier.

It is used in modern ‘‘Digital Signal Processing’’

Page 9: VEDIC MULTIPLIER FOR "FPGA"

For complex multiplications, even system becomes complex…

Page 10: VEDIC MULTIPLIER FOR "FPGA"

The proposed Vedic multiplier based MAC unit proves to be highly efficient in terms of speed & area.

Page 11: VEDIC MULTIPLIER FOR "FPGA"
Page 12: VEDIC MULTIPLIER FOR "FPGA"

Submitted by RAJENDAR

SAIKRISHNA SANDEEP


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