Versal ACAP Soſt DDR4 SDRAM Memory Controller v1.0 LogiCORE IP Product Guide Vivado Design Suite PG353 (v1.0) November 3, 2021 Xilinx is creating an environment where employees, customers, and partners feel welcome and included. To that end, we’re removing non- inclusive language from our products and related collateral. We’ve launched an internal initiative to remove language that could exclude people or reinforce historical biases, including terms embedded in our software and IPs. You may still find examples of non-inclusive language in our older products as we work to make these changes and align with evolving industry standards. Follow this link for more information.
Transcript
Versal ACAP Soft DDR4SDRAM Memory Controllerv1.0
LogiCORE IP Product GuideVivado Design Suite
PG353 (v1.0) November 3, 2021
Xilinx is creating an environment where employees, customers, andpartners feel welcome and included. To that end, we’re removing non-inclusive language from our products and related collateral. We’velaunched an internal initiative to remove language that could excludepeople or reinforce historical biases, including terms embedded in oursoftware and IPs. You may still find examples of non-inclusivelanguage in our older products as we work to make these changes andalign with evolving industry standards. Follow this link for moreinformation.
Chapter 2: Overview......................................................................................................7Introduction to Versal ACAP.......................................................................................................7Navigating Content by Design Process.................................................................................... 8Core Overview..............................................................................................................................9Licensing and Ordering............................................................................................................ 10
Chapter 5: Designing with the Core................................................................... 48Clocking...................................................................................................................................... 48Resets..........................................................................................................................................50PCB Guidelines...........................................................................................................................51Pin and Bank Rules....................................................................................................................51Pin Mapping for x4 RDIMMs/LRDIMMs..................................................................................55Protocol Description................................................................................................................. 56Performance............................................................................................................................ 116DIMM Configurations............................................................................................................. 126Setting Timing Options...........................................................................................................130
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M and D Support for Reference Input Clock Speed............................................................135
Chapter 6: Design Flow Steps...............................................................................137Customizing and Generating the Core.................................................................................137I/O Planning.............................................................................................................................148Constraining the Core.............................................................................................................148Simulation................................................................................................................................ 149Synthesis and Implementation............................................................................................. 150
Chapter 7: Example Design................................................................................... 151Simulating the Example Design (Designs with Standard User Interface)....................... 152Project-Based Simulation....................................................................................................... 153Using Xilinx IP with Third-Party Synthesis Tools................................................................. 159
Simulation3 For supported simulators, see the Xilinx Design Tools: Release Notes Guide.
Synthesis Vivado Synthesis
Support
All Vivado IP Change Logs Master Vivado IP Change Logs: 72775
Xilinx Support web page
Notes:1. For a complete list of supported devices, see the Vivado IP catalog.2. For the supported versions of third-party tools, see the Xilinx Design Tools: Release Notes Guide.3. Behavioral simulations are supported with Mixed Simulator Language. Netlist (post-synthesis and post-
implementation) simulations are supported with Verilog Simulator Language and are not supported by VivadoSimulator.
Chapter 1: Introduction
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Introduction to Versal ACAPVersal® adaptive compute acceleration platforms (ACAPs) combine Scalar Engines, AdaptableEngines, and Intelligent Engines with leading-edge memory and interfacing technologies todeliver powerful heterogeneous acceleration for any application. Most importantly, Versal ACAPhardware and software are targeted for programming and optimization by data scientists andsoftware and hardware developers. Versal ACAPs are enabled by a host of tools, software,libraries, IP, middleware, and frameworks to enable all industry-standard design flows.
Built on the TSMC 7 nm FinFET process technology, the Versal portfolio is the first platform tocombine software programmability and domain-specific hardware acceleration with theadaptability necessary to meet today's rapid pace of innovation. The portfolio includes six seriesof devices uniquely architected to deliver scalability and AI inference capabilities for a host ofapplications across different markets—from cloud—to networking—to wireless communications—to edge computing and endpoints.
The Versal architecture combines different engine types with a wealth of connectivity andcommunication capability and a network on chip (NoC) to enable seamless memory-mappedaccess to the full height and width of the device. Intelligent Engines are SIMD VLIW AI Enginesfor adaptive inference and advanced signal processing compute, and DSP Engines for fixed point,floating point, and complex MAC operations. Adaptable Engines are a combination ofprogrammable logic blocks and memory, architected for high-compute density. Scalar Engines,including Arm® Cortex®-A72 and Cortex-R5F processors, allow for intensive compute tasks.
The Versal AI Edge series focuses on AI performance per watt for real-time systems in automateddrive, predictive factory and healthcare systems, multi-mission payloads in aerospace & defense,and a breadth of other applications. More than just AI, the Versal AI Edge series accelerates thewhole application from sensor to AI to real-time control, all with the highest levels of safety andsecurity to meet critical standards such as ISO26262 and IEC 61508.
Chapter 2: Overview
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The Versal AI Core series delivers breakthrough AI inference acceleration with AI Engines thatdeliver over 100x greater compute performance than current server-class of CPUs. This series isdesigned for a breadth of applications, including cloud for dynamic workloads and network formassive bandwidth, all while delivering advanced safety and security features. AI and datascientists, as well as software and hardware developers, can all take advantage of the high-compute density to accelerate the performance of any application.
The Versal Prime series is the foundation and the mid-range of the Versal platform, serving thebroadest range of uses across multiple markets. These applications include 100G to 200Gnetworking equipment, network and storage acceleration in the Data Center, communicationstest equipment, broadcast, and aerospace & defense. The series integrates mainstream 58Gtransceivers and optimized I/O and DDR connectivity, achieving low-latency acceleration andperformance across diverse workloads.
The Versal Premium series provides breakthrough heterogeneous integration, very high-performance compute, connectivity, and security in an adaptable platform with a minimizedpower and area footprint. The series is designed to exceed the demands of high-bandwidth,compute-intensive applications in wired communications, data center, test & measurement, andother applications. Versal Premium series ACAPs include 112G PAM4 transceivers and integratedblocks for 600G Ethernet, 600G Interlaken, PCI Express® Gen5, and high-speed cryptography.
The Versal architecture documentation suite is available at: https://www.xilinx.com/versal.
Navigating Content by Design ProcessXilinx® documentation is organized around a set of standard design processes to help you findrelevant content for your current development task. All Versal® ACAP design process DesignHubs and the Design Flow Assistant materials can be found on the Xilinx.com website. Thisdocument covers the following design processes:
• Hardware, IP, and Platform Development: Creating the PL IP blocks for the hardwareplatform, creating PL kernels, functional simulation, and evaluating the Vivado® timing,resource use, and power closure. Also involves developing the hardware platform for systemintegration. Topics in this document that apply to this design process include:
• Port Descriptions
• Chapter 4: Core Architecture
• Chapter 5: Designing with the Core
• Chapter 6: Design Flow Steps
• Chapter 7: Example Design
Chapter 2: Overview
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Core OverviewThe DDR4 SDRAM core provides solutions for interfacing with the SDRAM memory type. Both acomplete Memory Controller and a physical (PHY) layer only solution are supported. The VersalACAP for the DDR4 SDRAM core are organized in the following high-level blocks:
• Controller: The controller accepts burst transactions from the user interface and generatestransactions to and from the SDRAM. The controller takes care of the SDRAM timingparameters and refresh. It coalesces write and read transactions to reduce the number of deadcycles involved in turning the bus around. The controller also reorders commands to improvethe utilization of the data bus to the SDRAM.
• Physical Layer: The physical layer provides a high-speed interface to the SDRAM. This layerincludes the hard blocks inside the Versal ACAP and the soft blocks calibration logic necessaryto ensure optimal timing of the hard blocks interfacing to the SDRAM.The application logic isresponsible for all SDRAM transactions, timing, and refresh. These hard blocks include:
• Data serialization and transmission
• Data capture and deserialization
• High-speed clock generation and synchronization
• Coarse and fine delay elements per pin with voltage and temperature tracking
The soft blocks include:
• Memory Initialization: The calibration modules provide a JEDEC®-compliant initializationroutine for the particular memory type. The delays in the initialization process can bebypassed to speed up simulation time, if desired.
• Calibration: The calibration modules provide a complete method to set all delays in thehard blocks and soft IP to work with the memory interface. Each bit is individually trainedand then combined to ensure optimal interface performance. Results of the calibrationprocess are available through the Xilinx® debug tools. After completion of calibration, thePHY layer presents raw interface to the SDRAM.
• Application Interface: The user interface layer provides a simple FIFO-like interface to theapplication. Data is buffered and read data is presented in request order. The above userinterface is layered on top of the native interface to the controller. The native interface is notaccessible by the user application and has no buffering and presents return data to the userinterface as it is received from the SDRAM which is not necessarily in the original requestorder. The user interface then buffers the read and write data and reorders the data asneeded.
Chapter 2: Overview
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Licensing and OrderingThis Xilinx® LogiCORE™ IP module is provided at no additional cost with the Xilinx Vivado®
Design Suite under the terms of the Xilinx End User License.
Note: To verify that you need a license, check the License column of the IP Catalog. Included means that alicense is included with the Vivado® Design Suite; Purchase means that you have to purchase a license touse the core.
Information about other Xilinx® LogiCORE™ IP modules is available at the Xilinx IntellectualProperty page. For information about pricing and availability of other Xilinx LogiCORE IP modulesand tools, contact your local Xilinx sales representative.
Chapter 2: Overview
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StandardsThis core adheres to the following standard(s):
• JESD79-4, DDR4 SDRAM Standard, JEDEC® Solid State Technology Association
• DDR4 3DS Addendum
PerformanceMaximum Frequencies
For more information on the maximum frequencies, see the following documentation:
• Versal Prime Series Data Sheet: DC and AC Switching Characteristics (DS956)
• Versal AI Core Series Data Sheet: DC and AC Switching Characteristics (DS957)
Port DescriptionsThere are three port categories at the top-level of the memory interface core called the “userdesign.”
• The first category is the memory interface signals that directly interfaces with the SDRAM.These are defined by the JEDEC specification.
• The second category is the application interface signals. These are described in the ProtocolDescription section.
• The third category includes other signals necessary for proper operation of the core. Theseinclude the clocks, reset, and status signals from the core. The clocking and reset signals aredescribed in their respective sections.
Chapter 3: Product Specification
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The active-High init_calib_complete signal indicates that the initialization andcalibration are complete and that the interface is now ready to accept commands for theinterface.
For a PHY layer only solution, the top-level application interface signals are replaced with thePHY interface. These signals are described in the PHY Only Interface section.
The signals that interface directly with the SDRAM and the clocking and reset signals are thesame as for the Memory Controller solution.
Related Information
PHY Only InterfaceProtocol Description
Chapter 3: Product Specification
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Core ArchitectureThis section describes the Xilinx® Versal® adaptive compute acceleration platform (ACAP)Memory Interface Solutions core with an overview of the modules and interfaces. The core isshown below.
Memory ControllerThe Memory Controller (MC) is designed to take Read, Write, and Read-Modify-Writetransactions from the user interface (UI) block and issues them to memory efficiently with lowlatency, meeting all DRAM protocol and timing requirements, while using minimal Versal ACAPresources. The MC operates with a DRAM to system clock ratio of 4:1 and can issue oneActivate, one CAS, and one Precharge command on each system clock cycle.
The MC supports an open page policy and can achieve very high efficiencies with workloads witha high degree of spatial locality. The MC also supports a closed page policy and the ability toreorder transactions to efficiently schedule workloads with address patterns that are morerandom. The MC also allows a degree of control over low-level functions with a UI control signalfor AutoPrecharge on a per transaction basis as well as signals that can be used to determinewhen DRAM refresh commands are issued.
The key blocks of the MC command path include:
1. The Group FSMs that queue up transactions, check DRAM timing, and decide when torequest Precharge, Activate, and CAS DRAM commands.
2. The "Safe" logic and arbitration units that reorder transactions between Group FSMs basedon additional DRAM timing checks while also ensuring forward progress for all DRAMcommand requests.
3. The Final Arbiter that makes the final decision about which commands are issued to the PHYand feeds the result back to the previous stages.
The maintenance blocks of the MC command path include:
1. Blocks that generate refresh and ZQCS commands
2. Commands needed for VT tracking
3. Optional block that implements a SECDED ECC for 72-bit, 40-bit, and 24-bit wide data buses
The following figure shows the MC block diagram.
Chapter 4: Core Architecture
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Native InterfaceThe UI block is connected to the MC by the native interface, and provides the MC with addressdecode and read/write data buffering. On writes, data is requested by the MC one cycle before itis needed by presenting the data buffer address on the native interface. This data is expected tobe supplied by the UI block on the next cycle. Hence there is no buffering of any kind for data(except due to the barrel shifting to place the data on a particular DDR clock).
On reads, the data is offered by the MC on the cycle it is available. Read data, along with a bufferaddress is presented on the native interface as soon as it is ready. The data has to be accepted bythe UI block.
Read and write transactions are mapped to an mcGroup instance based on bank group and bankaddress bits of the decoded address from the UI block. The name group represents either a realgroup in DDR4 x4 and x8 devices (which serves four banks of that group).
In the case of DDR4 x16 interface, the mcGroup represents 1-bit of group (there are only onegroup bit in x16) and 1-bit of bank, whereby the mcGroup serves two banks.
The total number of outstanding requests depends on the number of mcGroup instances, as wellas the round trip delay from the MC to memory and back. When the MC issues an SDRAM CAScommand to memory, an mcGroup instance becomes available to take a new request, while theprevious CAS commands, read return data, or write data might still be in flight.
Control and DatapathsThe control path starts at the mcGroup instances. The mapping of SDRAM group and bankaddresses to mcGroup instance ensures that transactions to the same full address map to thesame mcGroup instance. Because each mcGroup instance processes the transactions it receivesin order, read-after-write and write-after-write address hazards are prevented.
Read and write data pass through the MC. If ECC is enabled, a SECDEC code word is generatedon writes and checked on reads. For more details on ECC, see the related information. The MCgenerates the requisite control signals to the mcRead and mcWrite modules telling them thetiming of read and write data. The two modules acquire or provide the data as required at theright time.
Related Information
ECC
Chapter 4: Core Architecture
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Read and Write CoalescingThe MC prioritizes reads over writes when reordering is enabled. If both read and write CAScommands are safe to issue on the SDRAM command bus, the MC selects only read CAScommands for arbitration. When a read CAS issues, write CAS commands are blocked for severalSDRAM clocks specified by parameter tRTW. This extra time required for a write CAS to becomesafe after issuing a read CAS allows groups of reads to issue on the command bus without beinginterrupted by pending writes.
ReorderingRequests that map to the same mcGroup are never reordered. Reordering between the mcGroupinstances is controlled with the ORDERING parameter. When set to "NORM," reordering isenabled and the arbiter implements a round-robin priority plan, selecting in priority order amongthe mcGroups with a command that is safe to issue to the SDRAM.
The timing of when it is safe to issue a command to the SDRAM can vary on the target bank orbank group and its page status. This often contributes to reordering.
When the ORDERING parameter is set to "STRICT," all requests have their CAS commandsissued in the order in which the requests were accepted at the native interface. STRICT orderingoverrides all other controller mechanisms, such as the tendency to coalesce read requests, andcan therefore degrade data bandwidth usage in some workloads.
Group MachinesIn the Memory Controller, there are four group state machines. These state machines areallocated depending on technology (DDR4) and width (x4, x8, and x16). The followingsummarizes the allocation to each group machine. In this description, GM refers to the GroupMachine (0 to 3), BG refers to group address, and BA refers to bank address. Note that group inthe context of a group state machine denotes a notional group and does not necessarily refer toa real group (except in case of DDR4, part x4 and x8).
• DDR4, x4 and x8 parts – Total of 16 banks
• GM 0: Services BG 0; four banks per group
• GM 1: Services BG 1; four banks per group
• GM 2: Services BG 2; four banks per group
• GM 3: Services BG 3; four banks per group
• DDR4, x16 parts – Total of eight banks
• GM 0: Services BG 0, BA[0] == 0; 2 banks per group
• GM 1: Services BG 0, BA[0] == 1; 2 banks per group
Chapter 4: Core Architecture
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• GM 2: Services BG 1, BA[0] == 0; 2 banks per group
• GM 3: Services BG 1, BA[0] == 1; 2 banks per group
The following figure shows the Group FSM block diagram for one instance. There are two mainsections to the Group FSM block, stage 1 and stage 2, each containing a FIFO and an FSM. Stage1 interfaces to the UI, issues Precharge and Activate commands, and tracks the DRAM pagestatus.
Stage 2 issues CAS commands and manages the RMW flow. There is also a set of DRAM timersfor each rank and bank used by the FSMs to schedule DRAM commands at the earliest safe time.The Group FSM block is designed so that each instance queues up multiple transactions from theUI, interleaves DRAM commands from multiple transactions onto the DDR bus for efficiency, andexecutes CAS commands strictly in order.
Figure 4: Group FSM Block Diagram
Stage 1TransactionGroup FSM
Stage 1 FIFO Stage 2 FIFO
Stage 2CAS
Group FSM
DRAM Address
DRAM Address for New UI Transaction
pop push
full
empty
fullPage Table
PageStatus
Activate Request
Precharge Request
empty
CAS Request
pop
Activate/Precharge Address
CAS Address
push
DRAMCommands
DRAMCommands
tRCDtRP
tRASTimers
Winning Command Feedback
X23067-080119
When a new transaction is accepted from the UI, it is pushed into the stage 1 transaction FIFO.The page status of the transaction at the head of the stage 1 FIFO is checked and provided tothe stage 1 transaction FSM. The FSM decides if a Precharge or Activate command needs to beissued, and when it is safe to issue them based on the DRAM timers.
Chapter 4: Core Architecture
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When the page is open and not already scheduled to be closed due to a pending RDA or WRA inthe stage 2 FIFO, the transaction is transferred from the stage 1 FIFO to the stage 2 FIFO. At thispoint, the stage 1 FIFO is popped and the stage 1 FSM begins processing the next transaction. Inparallel, the stage 2 FSM processes the CAS command phase of the transaction at the head ofthe stage 2 FIFO. The stage 2 FSM issues a CAS command request when it is safe based on thetRCD timers. The stage 2 FSM also issues both a read and write CAS request for RMWtransactions.
ECCThe MC supports an optional SECDED ECC scheme that detects and corrects read data errorswith 1-bit error per DQ bus burst and detects all 2-bit errors per burst. The 2-bit errors are notcorrected. Three or more bit errors per burst might or might not be detected, but are nevercorrected. Enabling ECC adds four DRAM clock cycles of latency to all reads, whether errors aredetected/corrected or not.
A Read-Modify-Write (RMW) scheme is also implemented to support Partial Writes when ECC isenabled. Partial Writes have one or more user interface write data mask bits set High. PartialWrites with ECC disabled are handled by sending the data mask bits to the DRAM Data Mask(DM) pins, so the RMW flow is used only when ECC is enabled. When ECC is enabled, PartialWrites require their own command, wr_bytes or 0x3, so the MC knows when to use the RMWflow.
Note: When ECC is enabled, initialize (or write to) the memory space prior to performing partial writes(RMW).
Read-Modify-Write FlowWhen a wr_bytes command is accepted at the user interface it is eventually assigned to agroup state machine like other write or read transactions. The group machine breaks the PartialWrite into a read phase and a write phase. The read phase performs the following:
1. First reads data from memory.
2. Checks for errors in the read data.
3. Corrects single bit errors.
4. Stores the result inside the Memory Controller.
Data from the read phase is not returned to the user interface. If errors are detected in the readdata, an ECC error signal is asserted at the native interface. After read data is stored in thecontroller, the write phase begins as follows:
1. Write data is merged with the stored read data based on the write data mask bits.
Chapter 4: Core Architecture
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2. New ECC check bits are generated for the merged data and check bits are written tomemory.
3. Any multiple bit errors in the read phase results in the error being made undetectable in thewrite phase as new check bits are generated for the merged data. This is why the ECC errorsignal is generated on the read phase even though data is not returned to the user interface.This allows the system to know if an uncorrectable error has been turned into anundetectable error.
When the write phase completes, the group machine becomes available to process a newtransaction. The RMW flow ties up a group machine for a longer time than a simple read or write,and therefore might impact performance.
ECC ModuleThe ECC module is instantiated inside the DDR4 Memory Controller. It is made up of fivesubmodules as shown below.
Chapter 4: Core Architecture
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Read data and check bits from the PHY are sent to the Decode block, and on the next systemclock cycle data and error indicators ecc_single/ecc_multiple are sent to the NI.ecc_single asserts when a correctable error is detected and the read data has been corrected.ecc_multiple asserts when an uncorrectable error is detected.
Read data is not modified by the ECC logic on an uncorrectable error. Error indicators are neverasserted for “periodic reads,” which are read transactions generated by the controller only for thepurposes of VT tracking and are not returned to the user interface or written back to memory inan RMW flow.
Write data is merged in the Encode block with read data stored in the ECC Buffer. The merge iscontrolled on a per byte basis by the write data mask signal. All writes use this flow, so full writesare required to have all data mask bits deasserted to prevent unintended merging. After theMerge stage, the Encode block generates check bits for the write data. The data and check bitsare output from the Encode block with a one system clock cycle delay.
The ECC Gen block implements an algorithm that generates an H-matrix for ECC check bitgeneration and error checking/correction. The generated code depends only on thePAYLOAD_WIDTH and DQ_WIDTH parameters, where DQ_WIDTH = PAYLOAD_WIDTH +ECC_WIDTH. DQ_WIDTHs of 72, 40, and 24 with ECC_WIDTH of 8 are supported.
Error AddressEach time a read CAS command is issued, the full DRAM address is stored in a FIFO in thedecode block. When read data is returned and checked for errors, the DRAM address is poppedfrom the FIFO and ecc_err_addr[51:0] is returned on the same cycle as signalsecc_single and ecc_multiple for the purposes of error logging or debug. The followingtable is a common definition of this address for DDR4.
LatencyWhen the parameter ECC is ON, the ECC modules are instantiated and read and write datalatency through the MC increases by one system clock cycle. When ECC is OFF, the data busesjust pass through the MC and all ECC logic should be optimized out.
ECC Port DescriptionsThe following table provides the ECC port descriptions at the User Interface.
Table 2: DDR4 ECC Operation Signal Direction Description
Signal I/O Descriptionddr4_ecc_single[7:0] O The ddr4_ecc_single signal is non-zero if the read data from the
external memory has a single bit error per beat of the read burst.
ddr4_ecc_multiple[7:0] O The ddr4_ecc_multiple signal is non-zero if the read data from theexternal memory has two bit errors per beat of the read burst. TheSECDED algorithm does not correct the corresponding read data andputs a non-zero value on this signal to notify the corrupted read dataat the User Interface.
ddr4_ecc_err_addr[51:0] O This bus contains the address of the current read command. Theddr4_ecc_err_addr signal is valid during the assertion of eitherddr4_ecc_single or ddr4_ecc_multiple.
Address ParityThe Memory Controller generates even command/address parity with a one DRAM clock delayafter the chip select asserts Low. This signal is only used in DDR4 RDIMM configurations whereparity is required by the DIMM RCD component.
Address parity is supported only for DDR4 RDIMM and LRDIMM configurations, which includes3DS RDIMMs and LRDIMMs. The Memory Controller does not monitor the Alert_n parityerror status output from the RDIMM/LRDIMM and it might return corrupted data to the UserInterface after a parity error.
The Alert_n signal is provided to the user through the user interface.
PHYThe PHY is considered the low-level physical interface to an external DDR4 SDRAM device aswell as all calibration logic for ensuring reliable operation of the physical interface itself. The PHYgenerates the signal timing and sequencing required to interface to the memory device.
Chapter 4: Core Architecture
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In addition, the PHY contains calibration logic to perform timing training of the read and writedatapaths to account for system static and dynamic delays.
The PHY is included in the complete Memory Interface Solution core, but can also beimplemented as a standalone PHY only block. A PHY only solution can be selected if you plan toimplement a custom Memory Controller. For details about interfacing to the PHY only block, seethe PHY Only Interface section.
IMPORTANT! The PHY interface is not DFI-compliant.
Related Information
PHY Only Interface
Overall PHY ArchitectureThe Versal ACAP PHY is composed of dedicated blocks and soft calibration logic. The dedicatedblocks are structured adjacent to one another with back-to-back interconnects to minimize theclock and datapath routing necessary to build high performance physical layers.
The MC and calibration logic communicate with this dedicated PHY in the slow frequency clockdomain, which is either divided by four or divided by two. This depends on the DDR4 memoryclock. A more detailed block diagram of the PHY design is shown in the following figure.
Chapter 4: Core Architecture
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The MC is designed to separate out the command processing from the low-level PHYrequirements to ensure a clean separation between the controller and physical layer. Thecommand processing can be replaced with custom logic if desired, while the logic for interactingwith the PHY stays the same and can still be used by the calibration logic.
Table 3: PHY Modules
Module Name Description<module>_...cal_top.sv Contains <module>_...cal_top.sv, <module>_...mc_pi.sv, and MUXes
between the calibration and the Memory Controller.
<module>_...cal_riu.sv Contains the MicroBlaze processing system and associated logic.
<module>_...mc_pi.sv Adjusts signal timing for the PHY for reads and writes.
Chapter 4: Core Architecture
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Module Name Description<module>_...cal_addr_decode.sv Versal ACAP logic interface for the MicroBlaze processor.
<module>_...config_rom.sv Configuration storage for calibration options.
microblaze_mcs_0.sv MicroBlaze MCS module
<module>_...iob.sv Instantiates all byte IOB modules.
<module>_...iob_byte.sv Generates the I/O buffers for all the signals in a given byte lane.
<module>_...debug_microblaze.sv Simulation-only file to parse debug statements from software running inMicroBlaze to indicate status and calibration results to the log.
<module>_...cal_cplx.sv RTL state machine for complex pattern calibration.
<module>_...cal_cplx_data.sv Data patterns used for complex pattern calibration.
<module>_...xphy.sv Top-level XPHY module.
<module>_...phy.sv Top-level of the PHY, contains pll and xphy.sv modules.
The PHY architecture encompasses all of the logic contained in <module>_...phy.sv. ThePHY contains wrappers around dedicated hard blocks to build up the memory interface fromsmaller components. A byte lane contains all of the clocks, resets, and datapaths for a givensubset of I/O. Multiple byte lanes are grouped together, along with dedicated clocking resources,to make up a single bank memory interface. Each nibble in the PHY contains a Register InterfaceUnit (RIU), a dedicated integrated block in the XPHY that provides an interface to the generalinterconnect logic for changing settings and delays for calibration. For more information on thehard silicon physical layer architecture, see the Versal ACAP SelectIO Resources ArchitectureManual (AM010).
The memory initialization is executed in Verilog RTL. The calibration and training areimplemented by an embedded MicroBlaze™ processor. The MicroBlaze Controller System (MCS)is configured with an I/O Module and a block RAM. The <module>_...cal_addr_decode.svmodule provides the interface for the processor to the rest of the system and implements helperlogic. The <module>_...config_rom.sv module stores settings that control the operation ofinitialization and calibration, providing run time options that can be adjusted without having torecompile the source code.
The address unit connects the MCS to the local register set and the PHY by performing addressdecode and control translation on the I/O module bus from spaces in the memory map andMUXing return data (<module>_...cal_addr_decode.sv). In addition, it provides addresstranslation (also known as “mapping”) from a logical conceptualization of the DRAM interface tothe appropriate pinout-dependent location of the delay control in the PHY address space.
Although the calibration architecture presents a simple and organized address map formanipulating the delay elements for individual data, control and command bits, there is flexibilityin how those I/O pins are placed. For a given I/O placement, the path to the Versal ACAP logic islocked to a given pin. To enable a single binary software file to work with any memory interfacepinout, a translation block converts the simplified RIU addressing into the pinout-specific RIUaddress for the target design (see the XPHY RIU Addressing and Description table).
Chapter 4: Core Architecture
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The specific address translation is written by DDR4 SDRAM after a pinout is selected and cannotbe modified. The code shows an example of the RTL structure that supports this.
In this example, DQ0 is pinned out on Bit[0] of nibble 0 (nibble 0 according to instantiation order).The RIU address for the ODELAY for Bit[0] is 0x0D. When DQ0 is addressed — indicated byaddress 0x000_4100), this snippet of code is active. It enables nibble 0 (decoded to one-hotdownstream) and forwards the address 0x0D to the RIU address bus.
The MicroBlaze I/O module interface is not always fast enough for implementing all of thefunctions required in calibration. A helper circuit implemented in<module>_...cal_addr_decode.sv is required to obtain commands from the registers andtranslate at least a portion into single-cycle accuracy for submission to the PHY. In addition, itsupports command repetition to enable back-to-back read transactions and read datacomparison.
Table 4: XPHY RIU Addressing and Description
RIU Address Name Description0x00 NIBBLE_CTRL0 Nibble Control 0: Controls nibble clocking from neighboring nibble,
inversion of clock path from IOB to RX Bitslice-0, serial mode for IOB pair,transmit clock gating, receive clock gating, preamble extension forDQS_BIAS, fixdly_rdy generation, clearing gate for BISC, and disabling RXbitslice dynamic mode.
0x01 NIBBLE_CTRL1 Nibble Control 1: Controls 90° phase shift of RX clock , TX clock per bitslice,tristate output, RefClk TX bitslice, and Reference data Xx bitslice.
0x02 CALIB_CTRL Calibration Control: Controls BISC calibration, IDELAY BISC VT tracking,ODELAY BISC VT tracking, BISC calibration per bitslice and Master clockbitslice when IDELAY or ODELAY set to TIME.Provides status of fixed delay calibration and PHY ready, state ofBS_RESET_CTRL.bsc_reset, controls PQTR and NQTR VT tracking, andindicates status of BISC state machine.
0x03 BS_RESET_CTRL Bitslice reset control: Controls clear gate, bitslice reset, bitslice-tri reset, andmonitor reset if not masked. Also, it controls software BISC reset and XPHYreset when set by DDRMC (must assert for a minimum of 8 RIU clockcycles).Provides gate status, indicates overflow and underflow of coarse delay.
0x05 IODLY_BCAST_MASK Broadcast IDELAY and ODELAY mask
0x06 IODLY_BCAST_CTRL IO delay broadcast control: Enable/Disable IDELAY and ODELAY broadcast,controls fine or coarse increment or decrement or self clear when notmasked.
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Table 4: XPHY RIU Addressing and Description (cont'd)
RIU Address Name Description0x07 PQTR Rising edge delay for DQS: Controls one tap increment/decrement, or
coarse increment/decrement.
0x08 NQTR Falling edge delay for DQS: Controls one tap increment/decrement orcoarse increment/decrement.
0x09 MON Monitor delay: Controls one tap or coarse increments/decrements.
0x0A TRISTATE_ODLY Bitslice-tri delay: Controls one tap or coarse increments/decrements.
0x0B ODLY0 Bitslice-0 odelay: Controls one tap increments/decrements or coarseincrements/decrements based on CntvalueIn. Wraps around to h'0 whenincremented at delay value h'3ff. Wraps around to h`3ff when decrementedat delay value h`0.
0x0C ODLY1 Bitslice-1 odelay: Controls one tap increments/decrements or coarseincrements/decrements based on CntvalueIn. Wraps around to h'0 whenincremented at delay value h'3ff. Wraps around to h`3ff when decrementedat delay value h`0.
0x0D ODLY2 Bitslice-2 odelay: Controls one tap increments/decrements or coarseincrements/decrements based on CntvalueIn. Wraps around to h'0 whenincremented at delay value h'3ff. Wraps around to h`3ff when decrementedat delay value h`0.
0x0E ODLY3 Bitslice-3 odelay: Controls one tap increments/decrements or coarseincrements/decrements based on CntvalueIn. Wraps around to h'0 whenincremented at delay value h'3ff. Wraps around to h`3ff when decrementedat delay value h`0.
0x0F ODLY4 Bitslice-4 odelay: Controls one tap increments/decrements or coarseincrements/decrements based on CntvalueIn. Wraps around to h'0 whenincremented at delay value h'3ff. Wraps around to h`3ff when decrementedat delay value h`0.
0x10 ODLY5 Bitslice-5 odelay: Controls one tap increments/decrements or coarseincrements/decrements based on CntvalueIn. Wraps around to h'0 whenincremented at delay value h'3ff. Wraps around to h`3ff when decrementedat delay value h`0.
0x11 BS_RST_MASK Bitslice reset mask: When set, the corresponding bitslice will not get resetwhen a 1 is written to BS_RESET_CTRL.bs_reset.Bitslice-tri reset mask: When set, the tristate bitslice will not get reset whena 1 is written to BS_RESET_CTRL.bs_reset_tri.Monitor reset mask: When set, monitor logic will not get reset when a 1 iswritten to BS_RESET_CTRL.mon_reset.
0x12 IDLY0 Bitslice-0 idelay: Controls one tap increments/decrements or coarseincrements/decrements based on CntvalueIn. Wraps around to h'0 whenincremented at delay value h'3ff. Wraps around to h`3ff when decrementedat delay value h`0.
0x13 IDLY1 Bitslice-1 idelay: Controls one tap increments/decrements or coarseincrements/decrements based on CntvalueIn. Wraps around to h'0 whenincremented at delay value h'3ff. Wraps around to h`3ff when decrementedat delay value h`0.
0x14 IDLY2 Bitslice-2 idelay: Controls one tap increments/decrements or coarseincrements/decrements based on CntvalueIn. Wraps around to h'0 whenincremented at delay value h'3ff. Wraps around to h`3ff when decrementedat delay value h`0.
0x15 IDLY3 Bitslice-3 idelay: Controls one tap increments/decrements or coarseincrements/decrements based on CntvalueIn. Wraps around to h'0 whenincremented at delay value h'3ff. Wraps around to h`3ff when decrementedat delay value h`0.
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Table 4: XPHY RIU Addressing and Description (cont'd)
RIU Address Name Description0x16 IDLY4 Bitslice-4 idelay: Controls one tap increments/decrements or coarse
increments/decrements based on CntvalueIn. Wraps around to h'0 whenincremented at delay value h'3ff. Wraps around to h`3ff when decrementedat delay value h`0.
0x17 IDLY5 Bitslice-5 idelay: Controls one tap increments/decrements or coarseincrements/decrements based on CntvalueIn. Wraps around to h'0 whenincremented at delay value h'3ff. Wraps around to h`3ff when decrementedat delay value h`0.
0x18 CRSE_DLY Coarse Delay (32 tap CRSE DELAY to provide 1.8 ns delay in front of PQTRand NQTR for slow interfaces): Controls one tap increments/decrements orloading coarse delay value.
0x19 PQTR_ALIGN PQTR align delay value
0x1A NQTR_ALIGN NQTR align delay value
0x1B MON_ALIGN Monitor align delay value
0x1C IDLY0_ALIGN IDELAY0 align delay value
0x1D IDLY1_ALIGN IDELAY1 align delay value
0x1E IDLY2_ALIGN IDELAY2 align delay value
0x1F IDLY3_ALIGN IDELAY3 align delay value
0x20 IDLY4_ALIGN IDELAY4 align delay value
0x21 IDLY5_ALIGN IDELAY5 align delay value
0x22 RLDLYUPDATE RlDlyRank Update: Controls rank read level delay increments/decrementsby one tap or coarse steps. Increments/decrements by one tap or coarsesteps if corresponding rank mask bit not set.
0x2B WL_TRAIN Write level mode: When set, XPHY is put in write leveling mode otherwisenormal operation.Delay control enable VTC: When set, XPHY prepares the base line for the VTcompensation and upon completion it assert PHY_RDY.Enable transmit clockgen 1tck gap: When set, transmit clockgen suppressthe last ddr_strb for the current burst and first strobe of the next burstwhen it detects the 1tck gap between two write bursts so that tristate isinactive between the bursts.BISC Pause: When set, BISC state machine pauses.
0x2C WLDLYRNK0 Rank-0 write level fine and coarse delay
0x2D WLDLYRNK1 Rank-1 write level fine and coarse delay
0x2E WLDLYRNK2 Rank-2 write level fine and coarse delay
0x2F WLDLYRNK3 Rank-3 write level fine and coarse delay
0x30 RLDLYRNK0 Rank-0 read level fine and coarse delay and updates read delay rankregisters.
0x31 RLDLYRNK1 Rank-1 read level fine and coarse delay and updates read delay rankregisters.
0x32 RLDLYRNK2 Rank-2 read level fine and coarse delay and updates read delay rankregisters.
0x33 RLDLYRNK3 Rank-3 read level fine and coarse delay and updates read delay rankregisters.
0x3B INCDEC_CRSE Increment/decrement coarse adjustment value
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Table 4: XPHY RIU Addressing and Description (cont'd)
RIU Address Name Description0x3E NIBBLE_CTRL2 Nibble Control 2: Per bitslice ODT control. When set, ODT is disabled
otherwise it is enabled.Controls start of DQS gate training, enables DQS gate VT tracking, controlsper rank versus single rank gate delay tracking, controls if BISC employscoarse delay for quarter delay push out for PDQS and NDQS if PQTR andNQTR saturate and controls preamble for DDR4.
0x41 VREF_CTRL 10-bit VREF SettingProvides selection of VREF control from Fabric versus IOB config register.
0x49 CRSE_ADJUST Coarse adjust value. Default value is programmed to CRSE_ADJUSTattribute.
Memory Initialization and Calibration SequenceAfter deassertion of the system reset, the PHY performs some required internal calibration stepsfirst.
1. The built-in self-check (BISC) of the PHY is run. BISC is used in the PHY to compute internalskews for use in voltage and temperature tracking after calibration is completed.
2. After BISC is completed, calibration logic performs the required power-on initializationsequence for the memory.
3. This is followed by several stages of timing calibration for the write and read datapaths.
4. After calibration is completed, the PHY calculates internal offsets to be used in voltage andtemperature tracking.
5. The PHY indicates calibration is finished and the controller begins issuing commands to thememory.
The following table shows the overall flow of memory initialization and the different stages ofcalibration.
Table 5: PHY Overall Initialization and Calibration Sequence
SerialNumber Calibration Stage Calibration
Stage Code DDR4 DDR4_LRDIMM Rank-wiseCalibration
1 PHY Related calibration 0x0 Yes Yes N/A
2 Memory Initialization (DDR4, RCD,DB as applicable)
0x1 Yes Yes N/A
3 LRDIMM Data Buffer MREPTraining
0x2 N/A Yes Sequential
4 LRDIMM Data Buffer MRD CycleTraining
0x3 N/A Yes Sequential
5 LRDIMM Data Buffer MRD CenterTraining
0x4 N/A Yes Sequential
6 LRDIMM Data Buffer DWL Training 0x5 N/A Yes Sequential
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Notes:1. Sequential (Rank-wise Calibration): This means that the calibration stage will be completed one rank at a time in
sequence.2. Parallel (Rank-wise Calibration): This means that the calibration stage will be performed for all ranks simultaneously.
For LRDIMM configuration, the Data Buffer (DB) acts as an endpoint and represents all the ranksof the LRDIMM card. Hence all calibration stages are performed between the Host and the Databuffer.
Not all configurations require the entire calibration sequence to be performed. There will bevariations to this sequence based on data rate. The hardware manager will list the actualcalibration sequence for the configuration being used.
When simulating a design out of DDR4 SDRAM, the calibration it set to be bypassed to enableyou to generate traffic to and from the DRAM as quickly as possible. When running in hardwareor simulating with calibration, signals are provided to indicate the calibration stage beingperformed and the error status per stage.
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DQS GateDuring this stage of calibration, the read DQS preamble is detected and the gate to enable datacapture within the Versal ACAP is calibrated. The coarse and fine DQS gate taps are adjustedduring this stage. Read commands are issued with gaps in between to continually search for theDQS preamble position. The DDR4 preamble training mode is enabled during this stage toincrease the low preamble period and aid in detection. During this stage of calibration, only theread DQS signals are monitored and not the read DQ signals. DQS Preamble Detection isperformed in parallel for all bytes.
During this stage of calibration, the coarse taps are first adjusted while searching for the lowpreamble position and the third DQS edge, in other words, a DQS pattern of 0-0-x-1-x-0-x-1.
Figure 7: DDR4 Preamble
DDR4
Preamble training mode
0 0 X 1 X 0 X 1 X 0
X23036-080519
If the preamble is not found, the read latency is increased by one. The coarse taps are reset andthen adjusted again while searching for the low preamble and first rising DQS edge. After thepreamble position is properly detected, the fine taps are then adjusted to fine tune and edgealign the position of the sample clock with the DQS.
Write LevelingDDR4 write leveling allows the controller to adjust each write DQS phase independently withrespect to the CK forwarded to the DDR4 SDRAM device. This compensates for the skewbetween DQS and CK and meets the tDQSS specification.
During write leveling, DQS is driven by the Versal ACAP memory interface and DQ is driven bythe DDR4 SDRAM device to provide feedback. DQS is delayed until the 0 to 1 edge transition onDQ is detected. The DQS delay is achieved using both ODELAY and coarse tap delays.
After the edge transition is detected, the write leveling algorithm centers on the noise regionaround the transition to maximize margin. This second step is completed with only the use ofODELAY taps. Any reference to “FINE” is the ODELAY search.
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Read DQ Per-Bit Deskew and Centering: SimpleRead Leveling is performed over multiple stages to maximize the data eye and center the internalread sampling clock in the read DQ window for robust sampling. To perform this, Read Levelingperforms the following sequential steps:
1. Maximizes the DQ eye by removing skew and OCV effects using per bit read DQ deskew.
2. Sweeps DQS across all DQ bits and finds the center of the data eye using both easy (Multi-Purpose register data pattern) and complex data patterns. Centering of the data eye iscompleted for both the DQS and DQS#.
3. Post calibration, continuously maintains the relative delay of DQS versus DQ across the VTrange.
During the per bit deskew step, the toggling 01010101 MPR pattern is continuously readback. Parallel increments of PQTR and NQTR are performed until the true and complement ofthe internal read clock registers valid data on every bit in its nibble. This is followed byparallel increments of IDELAY taps for each DQ bit until invalid data is registered for each bit.At the end of this step, the DQ bits are internally deskewed to the left edge of the incomingDQS.
During the DQS centering step, the toggling 01010101 MPR pattern is continuously readback. Parallel increments of PQTR and NQTR are performed until the true and complement ofthe internal read clock registers invalid to valid data on any bit in its nibble. This transition isrecorded as the left edge of the valid window. Parallel increments of PQTR and NQTRcontinue until the true and complement of the internal read clock registers valid to invaliddata on any bit in its nibble. This value is recorded as the right edge of the valid window. Thecenter value is computed and loaded sequentially to all nibble PQTRs and NQTRs.
After completion of read DQS centering, a sanity check is performed to ensure the DQS isindeed in the valid data window.
Write Per-Bit Deskew and Centering: SimpleThis stage of calibration is required to center align the write DQS in the write DQ window perbit. At the start of Write DQS Centering and Per-Bit Deskew, DQS is aligned to CK but noadjustments on the write window have been made. Write window adjustments are made in thefollowing two sequential steps:
• Write Per-Bit Deskew
• Write DQS Centering
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During write per-bit deskew step, a known pattern is written and read back. First, DQS delay tapsare incremented until valid data is read back on all the DQ bits associated with a DQS. Next,delay taps of DQ bits are incremented until invalid data is read back on every DQ bit therebyedge aligning all DQ bits to its associated DQS.
For DBI deskew, enable write DBI and increment DQS delay taps until valid data is read back onall DQ bits. Next, delay DBI until invalid data is read back on all DQ bits.
Write Centering
In the write DQS centering step, the left and right margins have to be determined. First,increment delay taps of DQ bits and DBI until invalid data is read back. This is recorded as theleft margin of the write valid window. To find the right margin, DQS taps are incremented untilvalid to invalid data transition is found. Finally, DQS is placed at the center of the write validwindow based on the left and right margins detected.
At the end of this stage of calibration, a sanity check is performed to ensure correct write andread functionality.
Read DBI Deskew and Centering: SimpleBefore performing read DBI calibration, it is assumed that read DQ and write DQ calibrationshave been completed.
The 0F0F0F0F pattern is written to the DRAM and read back with read DBI enabled. The DRAMsends the data back as FFFFFFFF but the DBI pin has the clock pattern 01010101, that is usedto measure the data valid window of the DBI input pin itself. The final DQS location isdetermined based on the aggregate window for the DQ and DBI pins.
Write Latency CalibrationWrite Latency Calibration is required to align DQS to the correct CK edge. During write leveling,DQS is aligned to the nearest rising edge of CK. However, this might not be the edge thatcaptures the write command.
Depending on the interface type (UDIMM, RDIMM, LRDIMM, or component), the DQS couldeither be one CK cycle earlier than, two CK cycles earlier than, or aligned to the CK edge thatcaptures the write command.
This is a pattern based calibration where coarse adjustments are made on a per byte basis untilthe expected on time write pattern is read back. The process is as follows:
1. Issue extended writes followed by a single read.
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2. Check the pattern readback against the expected patterns.
3. If necessary add coarse adjustments.
4. Repeat until the on time write pattern is read back, signifying DQS is aligned to the correctCK cycle, or an incorrect pattern is received resulting in a Write Latency failure.
The following data is written at address 0x000:
• Data pattern before (with extra DQS pulses): 0000000000000000
• Data pattern written to address 0x000: FF00AA5555AA9966
• Data pattern after (with extra DQS pulses): FFFFFFFFFFFFFFFFFF
Reads are then performed where the following patterns can be calibrated:
• On time write pattern read back: FF00AA5555AA9966 (no adjustments needed)
• One DQS early write pattern read back: AA5555AA9966FFFF
• Two DQS early write pattern read back: 55AA9966FFFFFFFF
• Three DQS early write pattern read back: 9966FFFFFFFFFFFF
• Write Latency Calibration can fail for the following cases and signify a board violationbetween DQS and CK trace matching:
○ Four DQS early pattern FFFFFFFFFFFFFFFF
○ One DQS late write pattern read back: 0000FF00AA5555AA
○ Two DQS late write pattern read back: 00000000FF00AA55
○ Three DQS late write pattern read back: 000000000000FF00
Read DQS Centering (Complex)The final stage of DQS read centering that is completed before normal operation is to repeatread DQS centering with a complex data pattern. The purpose of using a complex pattern is tostress the system for SI effects such as ISI and noise while calculating the read DQS centerposition. This ensures that the read center position can reliably capture data with margin in a truesystem.
The first step in this stage is to revert the PQTR and NQTR delays to 0. At tap 0 if invalid data isnot detected on all data bits, increment DQ and DBI IDELAYs until invalid data is detected. Next,the PQTR and NQTR delays are incremented to detect invalid to valid and then valid to invalidedges of the read window. In the final step, read DQS is centered in the valid window.
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Write DQS-to-DQ Centering (Complex)Note: The calibration step is only enabled for the first rank in a multi-rank system. Also, this is only enabledfor data rates above 1,600 Mb/s.
For the same reasons as described in the Read DQS Centering (Complex), a complex data patternis used on the write path to adjust the Write DQS-to-DQ alignment. The same steps as detailedin the Write DQS-to-DQ Centering are repeated just with a complex data pattern.
Related Information
Read DQS Centering (Complex)Write Centering
Read Leveling Multi-Rank AdjustmentFor multi-rank systems the read DQS centering algorithm is ran on each rank, but the final delaysetting must be common for all ranks. The results of training each rank separately are stored inXSDB, but the final delay setting is a computed average of the training results across all ranks.The final PQTR/NQTR delay is indicated by RDLVL_PQTR_CENTER_FINAL_NIBBLE/RDLVL_NQTR_CENTER_FINAL_NIBBLE, while the DQ IDELAY isRDLVL_IDELAY_FINAL_BYTE_BIT.
Multi-Rank Adjustments and Checks
DQS Gate Multi-Rank Adjustment
During DQS gate calibration for multi-rank systems, each rank is allowed to calibrateindependently given the algorithm as described in DQS Gate. After all ranks have beencalibrated, an adjustment is required before normal operation to ensure fast rank-to-rankswitching. The general interconnect signal clb2phy_rd_en (indicated byDQS_GATE_READ_LATENCY_RANK_BYTE in XSDB) that controls the gate timing on a DRAM-clock-cycle resolution is adjusted here to be the same for a given byte across all ranks.
The coarse taps are adjusted so the timing of the gate opening stays the same for any given rank,where four coarse taps are equal to a single read latency adjustment in the general interconnect.During this step, the algorithm tries to find a common clb2phy_rd_en setting where across allranks for a given byte the coarse setting would not overflow or underflow, starting with thelowest read latency setting found for the byte during calibration. If the lowest setting does notwork for all ranks, the clb2phy_rd_en increments by one and the check is repeated. The finetap setting is < 90°, so it is not included in the adjustment.
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If the check reaches the maximum clb2phy_rd_en setting initially found during calibrationwithout finding a value that works between all ranks for a byte, an error is asserted. If after theadjustment is made and the coarse taps are larger than 360° (four coarse tap settings), a differenterror is asserted. For the error codes, see Error Signal Descriptions.
For multi-rank systems, the coarse taps must be seven or less so additional delay is added usingthe general interconnect read latency to compensate for the coarse tap requirement.
Related Information
DQS GateMemory Initialization and Calibration Sequence
Write Latency Multi-Rank Check
The write latency is allowed to fall wherever it can in multi-rank systems, each rank is allowed tocalibrate independently given the algorithms in Write Leveling and Write Latency Calibration.After all ranks have been calibrated and before it finishes, a check is made to ensure certainXPHY requirements are met on the write path. The difference in write latency between the ranksis allowed to be 180° (or two XPHY coarse taps).
Enable VT TrackingAfter the DQS gate multi-rank adjustment (if required), a signal is sent to the XPHY to recalibrateinternal delays to start voltage and temperature tracking. The XPHY asserts a signal whencomplete, phy2clb_phy_rdy_upp for upper nibbles and phy2clb_phy_rdy_low for lowernibbles.
For multi-rank systems, when all nibbles are ready for normal operation there is a requirement ofthe XPHY where two write-read bursts are required to be sent to the DRAM before startingnormal traffic. A data pattern of F00FF00F is used for the first and 0FF00FF0 for the second.The data itself is not checked and is expected to fail.
Write Read Sanity Check (Multi-Rank Only)For multi-rank systems, a check of the data for each rank is made to ensure the previous stagesof calibration did not inadvertently leave the write or read path in a bad spot. A single write burstfollowed by a single read command to the same location is sent to each DRAM rank. The data ischecked against the expected data across all bytes before continuing.
After all stages are completed across all ranks without any error, calDone gets asserted toindicate user traffic can begin. In XSDB, DBG_END contains 0x1 if calibration completes and0x2 if there is a failure.
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Read and Write VREF CalibrationThis section describes the VREF calibration algorithm. The algorithm is the same for Read DQVREF and Write DQ VREF calibration.
VREF calibration starts at a default VREF and the horizontal window at the default VREF is recordedas Vref_max_h. Next, VREF is incremented by a pre-defined step size. After each step sizeincrements, the horizontal window size will be calculated and compared with the previousdetected windows. If the current horizontal window is bigger than all the other windows, thecurrent VREF is recorded as Vref_max_h, and its horizontal window is recorded as W_max_r.
VREF increments by step size continues until the horizontal window at a VREF goes down to N ×W_max_r; 0 < N < 1. The VREF value where the horizontal window is less than N × W_max_r isrecorded as Vref_min_h.
In some cases, two Vref_min_h points can be found before (Vref_lb) and after (Vref_ub)finding the Vref_max_h. The final VREF point will be set to (Vref_ub – Vref_lb) / 2.
In other cases, Vref_lb cannot be detected while increasing the VREF. In such cases, VREF willbe reverted back to the default value and decremented by the step size until it finds theVref_lb point. While decrementing, there can be cases where the horizontal window startsincreasing and a new Vref_max_h point can be found with a bigger horizontal window thanW_max_r. In this case, the final VREF is set to the center of the new Vref_min_h points.
Calibration Sequence Status and Error ReportingThis section describes status and error reporting for the calibration sequence. This information isavailable through the hardware debugger in Vivado. MicroBlaze™ updates this status ascalibration proceeds.
Calibration Pointer (CAL_POINTER)
CAL_POINTER reports the status of the current calibration stage. On completion of a calibrationstage, this location reports status of the next calibration stage in the sequence specified byCAL_SEQ. The lower order Bits[5:0] indicate the calibration stage and the higher order Bits[8:6]indicate its status.
Calibration Stage Status (CAL_STATUS)
CAL_STATUS provides the status of calibration stage specified in CAL_POINTER. MicroBlazeupdates the progress and status.
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CAL_STATUS Description0 Calibration is enabled and yet to start this stage.
1 Calibration stage to be skipped due to any of the following:• Calibration stage is invalid.• Calibration stage is valid, but it can be skipped due to low frequency of operation.• Calibration stage is valid, but it can be skipped in functional simulations to cut down
simulation times.
2 Calibration values to be loaded. Calibration stage is valid and values need to be loaded. Thisis to cut down on functional simulation time.
3 Calibration stage in progress.
4 Calibration stage skipped.
5 Calibration values loaded.
6 Calibration stage passed.
7 Calibration stage failed.
Calibration Sub-Stage (CAL_SUB_STAGE)
Each calibration stage has its own set of sub-stages. CAL_SUB_STAGE provides the informationof the sub stage being run during a calibration stage. This location is valid only when the currentcalibration stage status is in-progress.
Table 7: Calibration Sub-Stage Status
Calibration Stage Sub-Stage Description
DQS Gate Calibration
0 Initializing internal variables
1 Finding third edge stage. Rank-wise.
2 Stable 0 confirmation before the third rise edge. Rank-wise.
3 Find left edge of the noise of the third edge using fine tapsof step size bigger than 1. Ranks wise.
4 Find noise width of the third edge using fine taps of stepsize 1. Rank wise.
5 Align to the center of noise using fine taps. Rank-wise.
6 Add extra read latency of 1 to allow gate logic to capture fullburst of the dqs. Rank-wise.
7 Multi-rank read latency and coarse adjustments.
8 DQS gate calibration exiting
Write Leveling
0 Finding the 0x1 edge detection. Rank-wise sequential.
1 Stage 0 confirmation. Rank-wise sequential.
2 Align to the center of noise using fine taps. Rank-wisesequential.
Write Latency
0 Finding required latency and adjustment. Rank-wise.
1 Multi rank write latency and coarse adjustment
2 Sanity Check. Rank-wise.
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1 Move PDQS and NDQS to valid region of their associateddata bits
2 Move all the DQ lines to valid region sampling of theirassociated PDQS
3 Move all the DQ lines to get start of the noise regionsampling of their associated PDQS
4 Move all the DQS lines together to get the noise regionsampling of their associated NDQS
5 Move PDQS and NDQS using fine taps of step size of 1 to getnoise to valid region crossing
6 Move PDQS and NDQS using fine taps of step size of morethan 1 to get valid to noise region crossing
7 Move PDQS and NDQS backward by one step size to go backto last valid sampling region
8 Move PDQS and NDQS using fine taps of step size of 1 to getvalid to noise region crossing
9 Move PDQS and NDQS to center of the detected validwindow
10 Check sanity of the read data calibration
11 Read calibration exiting
Calibration Rank (CAL_RANK)
Some of the sub-stages of calibration are repeated sequentially for every rank. CAL_RANK holdsthe value of the current rank being calibrated. This location is only valid for a rank-wisesequential calibration sub-stage.
Calibration Error Code (CAL_ERROR)
Each calibration stage has its own set of error scenarios. Each of the error scenario is encoded inCAL_ERROR with different values. This location is only valid when the current calibration stagehas failed.
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4 Reached read latency limit in the preset sub-stage
5 Unable to find common read latency across all ranksbecause of unexpected read latency difference
Write Latency Calibration1 No pattern match
2 Sanity check failed
Write Leveling
1 Could not find the 0x1 edge
2 Ran out of offset value, while finding the stable 0 value
3 Ran out of offset value, while finding the noise
Write DQ Per-bit Deskew and Centering
1 DQS delay crossing 90° offset
2 DQ delay crossing 180° offset during valid to noise
3 DQ delay crossing 180° offset during left edge of noise
4 Sanity check failure
Read DQ Per-bit Deskew and Centering1 Ran out of fine taps in the present sub-stage
2 Sanity check failed
Calibration Data Nibble (CAL_DATA_NIBBLE)
CAL_DATA_NIBBLE lists logical nibbles which have failed in the current calibration stage. Eachbit corresponds to a logical nibble. Total number of valid bits depends on the number of datanibbles in the interface. Bit 0 corresponds to logical nibble 0, Bit 1 corresponds to logical nibble1, etc. This location is only valid when the current calibration stage has failed. Maximum possiblelogical nibbles is 18 (72-bit in an x4 based configuration).
Calibration Physical Nibble (CAL_PHY_NIBBLE)
This location lists the physical nibbles which have failed in the current calibration stage. Each bitcorresponds to a physical nibble. Total number of valid bits is based on the number of physicalnibbles in the interface. Bit 0 corresponds to physical nibble 0, Bit 1 corresponds to physicalnibble 1, etc. This location is only valid when the current calibration stage has failed. Maximumpossible physical nibbles are 27 (three banks with nine nibbles per bank).
Calibration Data Bit (CAL_BIT)
CAL_BIT lists the bits which have failed in the current calibration stage. There are eight suchlocations to indicate 72 bits (9 bits per location) and each bit corresponds to each of the address/data pins. Total number of valid bits is based on the maximum number of data/address pins.Based on the error code, it specifies either the data or the address pins. This is valid only whenthe calibration stage has failed.
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This location reports the calibration warning in a given calibration stage. The type of the warning,rank number, nibble/byte, and/or data/address pin information is also reported. Every warninghas its own encoding based on the warning code.
Calibration Sequence (CAL_SEQ)
CAL_SEQ specifies the sequence of calibration. For every calibration stage in the sequence, thereis a calibration stage code and status.
DDR4 LRDIMM Calibration SequenceThe following data buffer calibration stages are added to meet the timing between the databuffer and DRAMs and these are repeated for each and every rank of the LRDIMM card/slot.
• MREP Training
• MRD Cycle Training
• MRD Center Training
• DWL Training
• MWD Cycle Training
• MWD Center Training
Whereas the host side calibration stages would exercise the timing between host and data bufferand they are performed once per every LRDIMM card/slot.
All the calibration stages between data buffer and DRAMs are exercised first and then the hostside calibration stages are exercised.
During the calibration stages between Data buffer and DRAM, the status value is placed on theDQ pins. At the time of these calibration stages, XPHY RX Gating is disabled and the Referenceclock is used to sample the DQ values.
At the end of each of the data buffer calibration stages, Per Buffer Addressing (PBA) mode isenabled to program the calibrated latency and the delay values into the data buffer registers.
The following sections describe the data buffer calibration stages.
Related Information
Memory Initialization and Calibration Sequence
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This training is to align the Read MDQS phase with the data buffer clock. In this training mode,host drives the read commands, DRAM sends out the MDQS, data buffer samples the strobewith the clock, and feeds the result on DQ. Host continues the training until a 1 to 0 transition isdetected on Read MDQS sampled with the data buffer clock.
MRD Cycle Training
This training is to find out the correct cycle to maintain the set Read Latency value at the databuffer. In this training mode, host pre-programs the DB MPR registers with the expected patternand issues the read commands. Data buffer compares the read data with the expected data andfeeds the result on to the DQ bus. Calibration picks up the correct cycle based on the result ofthe comparison.
MRD Center Training
This training is to perform center alignment of the Read MDQS in the Read MDQ window at thedata buffer. In this training mode, host pre-programs the DB MPR registers with the expectedpattern and issues the read commands. Data buffer compares the read data with the expecteddata and feeds the result on to the DQ bus. Calibration finds the left and right edges of the validwindow and centers it.
DWL Training
This training is to align the Write MDQS phase with the DRAM clock. In this training mode, DBdrives the MDQS pulses, DRAM samples the clock with MDQS, and feeds the result on to MDQ.Data buffer forwards this result from MDQ to DQ. Calibration continues to perform this trainingto find 0 to 1 transition on the clock sampled with the Write Read at the DRAM.
MWD Cycle Training
This training is to find out the right cycle to maintain the set Write Latency value in the DRAM. Inthis training mode, host pre-programs the DB MPR registers with the expected pattern, issuesthe write commands to load the data into memory and issues the reads to the memory. Databuffer compares the read data with the expected data and feeds the result on to the DQ bus.Calibration picks up the correct cycle based on the result of the comparison.
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This training is to center align the Write MDQS in the Write MDQ window at the DRAM. In thistraining mode, host pre-programs the DB MPR registers with the expected pattern, issues thewrite commands to load the data into memory, and issues the reads to the memory. Data bufferwould compare the read data with the expected data and feeds the result on to the DQ bus.Calibration finds the left and right edges of the valid window and centers it.
CAL_STATUS
There are two types of LRDIMM devices available: dual-rank cards and quad-rank cards. Becausethe data buffer calibration stages are repeated for every rank of the card, the calibrationsequence numbering is going to be different for dual-rank cards versus quad-rank cards.
ERROR STATUS
The Error signal descriptions of host calibration stages in the Error Signal Descriptions table istrue for LRDIMM host calibration stages, except that the stage numbering is as per LRDIMMdual-rank or quad-rank configuration.
The following table lists the error signals of the dual-rank LRDIMM data buffer calibration stagesand their description.
Table 9: Error Signal Description of Dual-Rank LRDIMM Data Buffer Calibration Stages
STAGE_NAME Stage Code DDR_CAL_ERROR_1 DDR_CAL_ERROR_0 ErrorData Buffer Rank 0 MREP 1 1 Nibble – Edge 1 to 0 transition is
not found for Rank 0
Data Buffer Rank 0 MRDCycle
2 1 Nibble – Pattern did not matchfor any of the Readlatencies of Rank 0
Data Buffer Rank 0 MRDCenter
3 1 Nibble – Found very short readvalid window for Rank 0
Data Buffer Rank 0 DWL 4 1 Nibble – Edge 0 to 1 transition isnot found for Rank 0
Data Buffer Rank 0 MWDCycle
5 1 Nibble – Pattern did not matchfor any of the Writelatencies of Rank 0
Data Buffer Rank 0 MWDCenter
6 1 Nibble – Found very short writevalid window for Rank 0
Data Buffer Rank 1 MREP 7 1 Nibble – Edge 1 to 0 transition isnot found for Rank 1
Data Buffer Rank 1 MRDCycle
8 1 Nibble – Pattern did not matchfor any of the Readlatencies of Rank 1
Data Buffer Rank 1 MRDCenter
9 1 Nibble – Found very short readvalid window for Rank 1
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15 1 Nibble – Found very short readvalid window for Rank 2
Data Buffer Rank 2 DWL 16 1 Nibble – Edge 0 to 1 transition isnot found for Rank 2
Data Buffer Rank 2 MWDCycle
17 1 Nibble – Pattern did not matchfor any of the Writelatencies of Rank 2
Data Buffer Rank 2 MWDCenter
18 1 Nibble – Found very short writevalid window for Rank 2
Data Buffer Rank 3 MREP 19 1 Nibble – Edge 1 to 0 transition isnot found for Rank 3
Data Buffer Rank 3 MRDCycle
20 1 Nibble – Pattern did not matchfor any of the Readlatencies of Rank 3
Data Buffer Rank 3 MRDCenter
21 1 Nibble – Found very short readvalid window for Rank 3
Data Buffer Rank 3 DWL 22 1 Nibble – Edge 0 to 1 transition isnot found for Rank 3
Data Buffer Rank 3 MWDCycle
23 1 Nibble – Pattern did not matchfor any of the Writelatencies of Rank 3
Data Buffer Rank 3 MWDCenter
24 1 Nibble – Found very short writevalid window for Rank 3
Related Information
Memory Initialization and Calibration Sequence
Reset SequenceThe sys_rst signal resets the entire memory interface design which includes generalinterconnect (fabric) logic, RIU interface logic, MicroBlaze™, and calibration logic. The sys_rstinput signal is synchronized internally to create the ui_clk_sync_rst signal. Theui_clk_sync_rst reset signal is synchronously asserted and synchronously deasserted.
The following figure shows the ui_clk_sync_rst signal (fabric reset) is synchronouslyasserted with a few clock delays after the sys_rst signal is asserted. When theui_clk_sync_rst signal is asserted, there are a few clocks before the clocks are shut off.
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Designing with the CoreThis section includes guidelines and additional information to facilitate designing with the core.
ClockingThe memory interface requires one XPLL per I/O bank used by the memory interface andBUFGs. These clocking components are used to create the proper clock frequencies and phaseshifts necessary for the proper operation of the memory interface.
There are two XPLLs per bank. If a bank is shared by two memory interfaces, both XPLLs in thatbank are used.
Note: DDR4 SDRAM generates the appropriate clocking structure and no modifications to the RTL aresupported.
The DDR4 SDRAM IP generates the appropriate clocking structure for the desired interface. Thisstructure must not be modified. The allowed clock configuration is as follows:
• Differential reference clock source connected to GCIO
• GCIO to XPLL (located in center bank of memory interface)
• XPLL to BUFG (located at center bank of memory interface) driving the Xilinx® Versal®adaptive compute acceleration platform (ACAP) logic and all XPLLs
• XPLL to BUFG (located at center bank of memory interface) divide by two mode driving 1/2rate Versal ACAP logic
Requirements
GCIO
• Must use a differential I/O standard
• Must be placed anywhere within the two or three banks of the interface
• The I/O standard and termination scheme are system dependent. For more information,consult the Versal ACAP SelectIO Resources Architecture Manual (AM010).
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• The input clock should always be clean and stable. The IP functionality is not guaranteed ifthis input system clock has a glitch, discontinuous, etc.
BUFGs and Clock Roots
BUFGs and clock roots must be located in one of the banks of the memory interface.
XPLL
• XPLL is used to generate the Versal ACAP logic system clock (1/4 of the memory clock)
• Must be located in the center bank of memory interface
• CLKOUTPHY from XPLL drives XPHY within its bank
• Must use internal feedback
Note: XPLLs do not have fractional clock generation.
The following figure shows an example of the clocking structure for a three bank memoryinterface. The GCIO drives the XPLL located at the center bank of the memory interface. TheXPLL in the center bank drives the inputs of the XPLLs in each of the adjacent banks.
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Figure 9: Clocking Structure for Three Bank Memory Interface
XPI/O Bank 1
XPI/O Bank 2
XPI/O Bank 3XPLL
XPLL
XPLL
Clock to RIU
Clock to Versal ACAP Logic
Mem
ory Interface
Differential GCIO Input
BUFG
BUFG
X23074-111820
XPLL UsageThere are two XPLLs per bank. One XPLL per bank is needed for the soft memory interface andthe total number of XPLLs depends on number of banks required for the interface. The followingshows the XPLL allocation/sharing rules:
• Any of the two XPLLs on a bank can be used for soft memory interface if that bank is not usedby the integrated DDR MC.
• If the same bank is shared by the integrated DDR MC and the soft memory interface, XPLL-0must be used for the integrated DDR MC and XPLL-1 must be used for the soft memoryinterface.
• When the same bank is shared by the soft memory interface and any IP other than theintegrated DDR MC, any of the two XPLLs can be used for soft memory interface.
ResetsAn asynchronous reset (sys_rst) input is provided. This is an active-High reset and thesys_rst must assert for a minimum pulse width of 5 ns. The sys_rst can be an internal orexternal pin.
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For more information on reset, see the Reset Sequence and Core Architecture sections.
Related Information
Reset SequenceCore ArchitectureUser Interface
PCB GuidelinesStrict adherence to all documented DDR4 PCB guidelines is required for successful operation.For more information on PCB guidelines, see the Versal ACAP PCB Design User Guide (UG863).
Pin and Bank RulesThe rules are for single and multi-rank memory interfaces.
IMPORTANT! The Versal ACAP soft memory IP can only use XPIO pins that are fully fabric accessible.Refer to the package file to determine XPIO pins that are fully fabric accessible. The XPIO pins/Banks in aVersal device that are not fabric accessible are called shadow pins/Banks.
• Address/control means cs_n, ras_n (a16), cas_n (a15), we_n (a14), ba, bg, ck, cke, a, odt,act_n, parity, and alert_n (valid for RDIMMs and LRDIMMs only). Multi-rank systemshave one cs_n, cke, odt, and one ck pair per rank.
• Each Bank has nine nibbles numbered 0 to 8. Two consecutive nibbles in a bank are paired toform a nibble pair. For example, 0-1, 2-3, 4-5, and 6-7 are the four nibble pairs in a bank.
• Pins in a nibble are numbered 0 to 5. For example in the package pin nameIO_L0N_XCC_N0P1_M0P1_700, N0P1 indicates pin 1 of nibble 0 in bank 700.
• An interface can span a maximum of three contiguous banks.
• Maximum component limit for a component interface is nine. This restriction is not applicablefor DIMMs.
• Skipping banks is not allowed. However, skipping nibbles is allowed.
• Maximum data width supported is 72.
○ Supported data widths for (x4): 8, 16, 24, and 32 with maximum of eight components.
○ Supported data widths for (x8): 8, 16, 24, 32, 40, 48, 56, 64, and 72 with maximum of ninecomponents.
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○ Supported data widths for (x16): 8, 16, 24, 32, 40, 48, 56, 64, and 72 with maximum of fivecomponents.
Note: There are two XPLLs per bank and the controller uses one XPLL in every bank that is being used bythe interface.
1. dqs, dq, and dm/dbi location.
a. DQS_t/c must be located on the dedicated DQS pair in a nibble with DQS_t on pin-0 andDQS_c on pin-1.
b. DQ pins must be placed only on 2, 3, 4, and 5 pins.
c. DQ’s associated with a DQS must be placed within the same nibble pair.
d. DM/DBI associated with a DQS must be placed only on the available pin-0 of a nibblepair. When DM/DBI is not used, pin-0 cannot be used for any other memory interface pinexcept RESET_n and ALERT_n.
e. x8 components and DIMMs:
• All DQ pins and DM pin associated with a DQS must be placed within a nibble pair(0-1, 2-3, 4-5, or 6-7).
• Swap of any byte with any other byte is allowed.
f. x4 components and DIMMs:
• All DQs associated with a DQS must be placed within a nibble.
g. All nibbles except nibble 8 in a bank can be used for Data group pins.
Consider x16 part with data width of 32 and all data bytes are allocated in a single bank.In such cases, DQS needs to be mapped as given in the DQS Mapping for x16Component table.
In the DQS Mapping for x16 Component table, the Bank-Byte and Selected Memory DataBytes indicate byte allocation in the I/O pin planner. The following example is given forone of the generated configuration in the I/O pin planner. Based on pin allocation, DQbyte allocation might vary.
DQS Allocated (in IP on the Versal ACAP) indicates DQS that is allocated on the VersalACAP end. Memory device mapping indicates how DQS needs to be mapped on thememory end.
Table 11: DQS Mapping for x16 Component
Bank-Byte Selected MemoryData Bytes
DQS Allocated (in IPon Versal ACAP) Memory Device Mapping
BankX_BYTE3 DQ[0-7] DQS0 Memory Device 0 – LDQS
BankX_BYTE2 DQ[8-15] DQS1 Memory Device 0 – UDQS
BankX_BYTE1 DQ[16-23] DQS2 Memory Device 1 – LDQS
BankX_BYTE0 DQ[24-31] DQS3 Memory Device 1 – UDQS
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2. Nibble pairs can be configured as either data or address/control. No data signals (DQS, DQ,DM/DBI) can be in a nibble pair that is configured for address/control. Only pin-1 (in x8components/DIMMs) can be used for the address/control in data nibbles.
3. Address/control signals can be placed on any of the pins in a nibble and all nibbles in a bankcan be used for Address/Control. All pins of Address/control group must be contained withinthe same bank.
4. A CK pair must be placed on a PN pin pair within the Address/Control bank. For multi-rankdevices, all CK pairs can be placed within a single nibble or spread across multiple nibbles.Here is the list of allowed nibble pins for CK.
• DDR4 component, UDIMM, SODIMM: CK_t/_c on pin pairs 0/1, 2/3 or 4/5.
• DDR4 RDIMM/LRDIMM: CK_t/_c on pin pairs 2/3 or 4/5 (not on 0/1).
5. The IO_VP pin is an additional bank pin that is used as a reference to calibrate internal on-dietermination (DCI). This pin must be externally connected to a 240Ω resistor on the PCB andpulled up to the bank VCCO voltage. DCI is required for this interface. All rules for the DCI inthe Versal ACAP SelectIO Resources Architecture Manual (AM010) must be followed.
RECOMMENDED: Xilinx strongly recommends that the DCIUpdateMode option is kept with thedefault value of ASREQUIRED so that the DCI circuitry is allowed to operate normally.
6. RESET_n and ALERT_n must be placed in XP banks and must be placed on same side ofbanks where interface is placed, Lets say, all memory interface pins are placed on bottom sidebanks of device, then RESET_n and ALERT_n must be placed on bottom side of device andmust not be placed on top banks of device.
7. Banks can be shared between two controllers.
a. Each nibble is dedicated to a specific controller (except for RESET_n). A nibble cannot beshared across two controllers
b. No nibble interleaving is allowed. For example, with controllers A and B, “AABB” isallowed but not “ABAB”.
8. All I/O banks used by the memory interface must be on a single side of the device, either topor bottom.
9. Input clock for the XPLL in the interface must come from any GCIO pair in the three I/Obanks used for the memory interface. Information on the clock input specifications can befound in the AC and DC Switching Characteristics data sheets (LVDS input requirements andXPLL requirements should be considered). For more information, see the Clocking section.
10. The par input for command and address parity and the TEN input for Connectivity TestMode are not supported by this interface. Consult the memory vendor for information on theproper connection for these pins when not used. For more information on parity errors, seethe Address Parity section.
11. For all other DRAM/DIMM pins that are not mentioned in this section, for example, SAx,SCL, SDA, contact the memory vendor for proper connectivity.
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IMPORTANT! Component interfaces should be created with the same component for all components inthe interface. x16 components have a different number of bank groups than the x8 components. Forexample, a 72-bit wide component interface should be created by using nine x8 components or five x16components where half of one component is not used. Four x16 components and one x8 component is notpermissible.
Related Information
DIMM ConfigurationsClockingAddress ParityPin Mapping for x4 RDIMMs/LRDIMMs
Nibble Pair View of Bank on Versal ACAP Die for x8and x16 SupportTable 12: Nibble Pair View of Bank on Versal ACAP Die for x8 and x16 Support
Triplet#Pin# Nibble#Pin# (_NxPy) Signal NameMxP0 IO_L0P_XCC_N0P0 DQS0_t
MxP1 IO_L0N_XCC_N0P1 DQS0_c
MxP2 IO_L1P_N0P2 DQ[7:0]
MxP3 IO_L1N_N0P3 DQ[7:0]
MxP4 IO_L2P_N0P4 DQ[7:0]
MxP5 IO_L2N_N0P5 DQ[7:0]
MxP6 IO_L3P_XCC_N1P0 DM/DBI
MxP7 IO_L3N_XCC_N1P1 Any Address/Command/Control except RESET_N andALERT_N
MxP8 IO_L4P_N1P2 DQ[7:0]
MxP9 IO_L4N_N1P3 DQ[7:0]
MxP10 IO_L5P_N1P4 DQ[7:0]
MxP11 IO_L5N_N1P5 DQ[7:0]
Nibble Pair View of Bank on Versal ACAP Die for x4,x8, and x16 SupportTable 13: Nibble Pair View of Bank on Versal ACAP Die for x4, x8, and x16 Support
Triplet#Pin# Nibble#Pin# (_NxPy) Signal NameMxP0 IO_L0P_XCC_N0P0 DQS0_t
MxP1 IO_L0N_XCC_N0P1 DQS0_c
MxP2 IO_L1P_N0P2 DQ[3:0]
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Table 13: Nibble Pair View of Bank on Versal ACAP Die for x4, x8, and x16 Support(cont'd)
Triplet#Pin# Nibble#Pin# (_NxPy) Signal NameMxP3 IO_L1N_N0P3 DQ[3:0]
MxP4 IO_L2P_N0P4 DQ[3:0]
MxP5 IO_L2N_N0P5 DQ[3:0]
MxP6 IO_L3P_XCC_N1P0 DM0/DBI0/DQS9_t
MxP7 IO_L3N_XCC_N1P1 DQS9_c
MxP8 IO_L4P_N1P2 DQ[7:4]
MxP9 IO_L4N_N1P3 DQ[7:4]
MxP10 IO_L5P_N1P4 DQ[7:4]
MxP11 IO_L5N_N1P5 DQ[7:4]
Pin Swapping• For x8 components and DIMMs, swap of any byte with any other byte is allowed.
• For x4 DIMMs, swap of any byte with any other byte is allowed and swap of nibbles withinbytes are allowed. This swapping rule should not be applied to x4/x8 compatible pinouts.
• For x4 components, swap of any nibble with any other nibble is allowed. This swapping ruleshould not be applied to x4/x8 compatible pinouts.
• Address/control pins can be freely swapped within and between nibbles contained in thesame bank.
• No other pin swapping is permitted.
Related Information
Pin and Bank Rules
Pin Mapping for x4 RDIMMs/LRDIMMsThe following table is an example showing the pin mapping for x4 DDR4 registered DIMMsbetween the memory data sheet and the XDC.
Table 14: Pin Mapping for x4 DDR4 DIMMs
Memory Data Sheet DDR4 SDRAM XDCDQ[63:0] DQ[63:0]
CB3 to CB0 DQ[67:64]
CB7 to CB4 DQ[71:68]
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Protocol DescriptionThe core has the following interfaces:
• User Interface
• AXI4 Slave Interface
• PHY Only Interface
User InterfaceThe user interface signals are connected to a Versal ACAP user design to allow access to anexternal memory device. The user interface is layered on top of the native interface which isdescribed earlier in the controller description.
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Signal I/O Descriptionapp_addr[APP_ADDR_WIDTH - 1:0]
I This input indicates the address for the current request.
app_cmd[2:0] I This input selects the command for the current request.
app_autoprecharge1 I This input instructs the controller to set the A10 autoprecharge bit onthe DRAM CAS command for the current request.
app_en I This is the active-High strobe for the app_addr[], app_cmd[2:0], andapp_hi_pri inputs.
app_rdy O This output indicates that the user interface is ready to acceptcommands. If the signal is deasserted when app_en is enabled, thecurrent app_cmd, app_autoprecharge, and app_addr must be retrieduntil app_rdy is asserted.
app_hi_pri I This input is reserved and should be tied to 0.
app_rd_data[APP_DATA_WIDTH - 1:0]
O This provides the output data from read commands.
app_rd_data_end O This active-High output indicates that the current clock cycle is the lastcycle of output data on app_rd_data[].
app_rd_data_valid O This active-High output indicates that app_rd_data[] is valid.
app_wdf_data[APP_DATA_WIDTH - 1:0]
I This provides the data for write commands.
app_wdf_end I This active-High input indicates that the current clock cycle is the lastcycle of input data on app_wdf_data[].
app_wdf_mask[APP_MASK_WIDTH - 1:0]
I This provides the mask for app_wdf_data[].This input port appears in the "Data Mask and DBI" Vivado IDE optionvalues of DM_NO_DBI and DM_DBI_RD.
app_wdf_rdy O This output indicates that the write data FIFO is ready to receive data.Write data is accepted when app_wdf_rdy = 1’b1 and app_wdf_wren =1’b1.
app_wdf_wren I This is the active-High strobe for app_wdf_data[].
app_ref_req2 I User refresh request.
app_ref_ack2 O User refresh request completed.
app_zq_req2 I User ZQCS command request.
app_zq_ack2 O User ZQCS command request completed.
ui_clk O This user interface clock must be one quarter of the DRAM clock.
init_calib_complete O PHY asserts init_calib_complete when calibration is finished.
ui_clk_sync_rst O This is the active-High user interface reset.
dbg_clk O Debug Clock. Do not connect any signals to dbg_clk and keep the portopen during instantiation.
sl_iport0 I[36:0]
Serial input port for debug interface.
sl_oport0 O[16:0]
Serial output port for debug interface.
ddr4_app_correct_en_i I When using the native interface with the input asserted, this enablesECC detection and correction.
LMB_UE O MCS Local Memory Uncorrectable Error (ECC only)
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Signal I/O DescriptionLMB_CE O MCS Local Memory Correctable Error (ECC only)
Notes:1. This port appears when "Enable Precharge Input" option is enabled in the Vivado IDE.2. These ports appear upon enabling "Enable User Refresh and ZQCS Input" option in the Vivado IDE.
app_addr[APP_ADDR_WIDTH - 1:0]
This input indicates the address for the request currently being submitted to the user interface.The user interface aggregates all the address fields of the external SDRAM and presents a flataddress space.
The MEM_ADDR_ORDER parameter determines how app_addr is mapped to the SDRAMaddress bus and chip select pins. This mapping can have a significant impact on memorybandwidth utilization. “ROW_COLUMN_BANK” is the recommended MEM_ADDR_ORDERsetting. The following tables show the “ROW_COLUMN_BANK” mapping for DDR4 withexamples. Note that the three LSBs of app_addr map to the column address LSBs whichcorrespond to SDRAM burst ordering.
The controller does not support burst ordering so these low order bits are ignored, making theeffective minimum app_addr step size hex 8.
The “ROW_COLUMN_BANK” setting maps app_addr[4:3] to the DDR4 bank group bits usedby the controller to interleave between its group FSMs. The lower order address bits equal toapp_addr[5] and above map to the remaining SDRAM bank and column address bits. Thehighest order address bits map to the SDRAM row. This mapping is ideal for workloads that haveaddress streams that increment linearly by a constant step size of hex 8 for long periods. Withthis configuration and workload, transactions sent to the user interface are evenly interleavedacross the controller group FSMs, making the best use of the controller resources.
In addition, this arrangement tends to generate hits to open pages in the SDRAM. Thecombination of group FSM interleaving and SDRAM page hits results in very high SDRAM databus usage.
Address streams other than the simple increment pattern tend to have lower SDRAM bus usage.You can recover this performance loss by tuning the mapping of your design flat address space tothe app_addr input port of the user interface. If you have knowledge of your address sequence,you can add logic to map your address bits with the highest toggle rate to the lowest app_addrbits, starting with app_addr[3] and working up from there.
For example, if you know that your workload address Bits[4:3] toggle much less than Bits[10:9],which toggle at the highest rate, you could add logic to swap these bits so that your addressBits[10:9] map to app_addr[4:3]. The result is an improvement in how the address streaminterleaves across the controller group FSMs, resulting in better controller throughput and higherSDRAM data bus usage.
DDR4 ROW_COLUMN_LRANK_BANK
The following table shows the “ROW_COLUMN_LRANK_BANK” mappings for DDR4 with 3DSexamples.
SDRAM Bus Row[14:0] Column[9:0] Bank[1:0] Bank Group[1:0]app_addr Bits 28 through 14 13 through 8, 5, and 2, 1, 0 7, 6 4, 3
app_cmd[2:0]
This input specifies the command for the request currently being submitted to the user interface.The available commands are shown here. With ECC enabled, the wr_bytes operation isrequired for writes with any non-zero app_wdf_mask bits. The wr_bytes triggers a read-modify-write flow in the controller, which is needed only for writes with masked data in ECCmode.
Table 26: Commands for app_cmd[2:0]
Operation app_cmd[2:0] CodeWrite 000
Read 001
wr_bytes 011
app_autoprecharge
This input specifies the state of the A10 autoprecharge bit for the DRAM CAS command forthe request currently being submitted to the user interface. When this input is Low, the MemoryController issues a DRAM RD or WR CAS command. When this input is High, the controllerissues a DRAM RDA or WRA CAS command. This input provides per request control, but canalso be tied off to configure the controller statically for open or closed page mode operation. TheMemory Controller also has an option to automatically determine when to issue anAutoPrecharge. This option disables the app_autoprecharge input. For more information onthe automatic mode, see the Performance section.
Related Information
Performance
app_en
This input strobes in a request. Apply the desired values to app_addr[], app_cmd[2:0], andapp_hi_pri, and then assert app_en to submit the request to the user interface. This initiatesa handshake that the user interface acknowledges by asserting app_rdy.
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This bus provides the data currently being written to the external memory. APP_DATA_WIDTH is2 × nCK_PER_CLK × DQ_WIDTH when ECC is disabled (ECC parameter value is OFF) and 2 ×nCK_PER_CLK × (DQ_WIDTH – ECC_WIDTH) when ECC is enabled (ECC parameter is ON).
PAYLOAD_WIDTH indicates the effective DQ_WIDTH on which the user interface data hasbeen transferred.
PAYLOAD_WIDTH is DQ_WIDTH when ECC is disabled (ECC parameter value is OFF).
PAYLOAD_WIDTH is (DQ_WIDTH - ECC_WIDTH) when ECC is enabled (ECC parameter is ON).
app_wdf_end
This input indicates that the data on the app_wdf_data[] bus in the current cycle is the lastdata for the current request.
app_wdf_mask[APP_MASK_WIDTH - 1:0]
This bus indicates which bits of app_wdf_data[] are written to the external memory andwhich bits remain in their current state. APP_MASK_WIDTH is APP_DATA_WIDTH / 8.
app_wdf_wren
This input indicates that the data on the app_wdf_data[] bus is valid.
app_rdy
This output indicates whether the request currently being submitted to the user interface isaccepted. If the user interface does not assert this signal after app_en is asserted, the currentrequest must be retried. The app_rdy output is not asserted if:
• PHY/Memory initialization is not yet completed.
• All the controller Group FSMs are occupied (can be viewed as the command buffer being full).
○ A read is requested and the read buffer is full.
○ A write is requested and no write buffer pointers are available.
• A periodic read is being inserted.
app_rd_data[APP_DATA_WIDTH - 1:0]
This output contains the data read from the external memory.
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This output indicates that the data on the app_rd_data[] bus in the current cycle is the lastdata for the current request.
app_rd_data_valid
This output indicates that the data on the app_rd_data[] bus is valid.
app_wdf_rdy
This output indicates that the write data FIFO is ready to receive data. Write data is acceptedwhen both app_wdf_rdy and app_wdf_wren are asserted.
app_ref_req
When asserted, this active-High input requests that the Memory Controller send a refreshcommand to the DRAM. It must be pulsed for a single cycle to make the request and thendeasserted at least until the app_ref_ack signal is asserted to acknowledge the request andindicate that it has been sent.
app_ref_ack
When asserted, this active-High input acknowledges a refresh request and indicates that thecommand has been sent from the Memory Controller to the PHY.
app_zq_req
When asserted, this active-High input requests that the Memory Controller send a ZQ calibrationcommand to the DRAM. It must be pulsed for a single cycle to make the request and thendeasserted at least until the app_zq_ack signal is asserted to acknowledge the request andindicate that it has been sent.
app_zq_ack
When asserted, this active-High input acknowledges a ZQ calibration request and indicates thatthe command has been sent from the Memory Controller to the PHY.
ui_clk_sync_rst
This is the reset from the user interface which is in synchronous with ui_clk.
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This is the output clock from the user interface. It must be a quarter the frequency of the clockgoing out to the external SDRAM, which depends on 4:1 mode selected in Vivado IDE.
init_calib_complete
PHY asserts init_calib_complete when calibration is finished. The application has no needto wait for init_calib_complete before sending commands to the Memory Controller.
Command Path
When the user logic app_en signal is asserted and the app_rdy signal is asserted from the userinterface, a command is accepted and written to the FIFO by the user interface. The command isignored by the user interface whenever app_rdy is deasserted. The user logic needs to holdapp_en High along with the valid command, autoprecharge, and address values until app_rdy isasserted as shown for the "write with autoprecharge" transaction in the following figure.
Figure 10: User Interface Command Timing Diagram with app_rdy Asserted
clk
app_cmd WRITE
app_addr Addr 0
app_en
app_rdyCommand is accepted when app_rdy is High and app_en is High.
app_autoprecharge
X23078-080619
A non back-to-back write command can be issued as shown in the following figure. This figuredepicts three scenarios for the app_wdf_data, app_wdf_wren, and app_wdf_end signals asfollows:
1. Write data is presented along with the corresponding write command.
2. Write data is presented before the corresponding write command.
3. Write data is presented after the corresponding write command, but should not exceed thelimitation of two clock cycles.
For write data that is output after the write command has been registered, as shown in #3, themaximum delay is two clock cycles.
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Figure 11: 4:1 Mode User Interface Write Timing Diagram (Memory Burst Type = BL8)
app_wdf_data
clk
app_cmd WRITE
app_addr Addr 0
app_wdf_end
app_en
app_wdf_wren
app_rdy
app_wdf_mask
app_wdf_rdy
W0
W0app_wdf_data
app_wdf_end
app_wdf_wren
app_wdf_data
app_wdf_end
app_wdf_wren
W0
Maximum allowed data delay from addr/cmd is two clocks as shown in Event 3.
1
2
3
X23079-080619
Write Path
The write data is registered in the write FIFO when app_wdf_wren is asserted andapp_wdf_rdy is High. If app_wdf_rdy is deasserted, the user logic needs to holdapp_wdf_wren and app_wdf_end High along with the valid app_wdf_data value untilapp_wdf_rdy is asserted. The app_wdf_mask signal can be used to mask out the bytes towrite to external memory.
Figure 12: 4:1 Mode User Interface Back-to-Back Write Commands Timing Diagram(Memory Burst Type = BL8)
clk
app_rdy
app_wdf_mask
app_wdf_rdy
app_cmd WRITE
app_addr Addr a
app_en
app_wdf_wren
app_wdf_end
app_wdf_data W a0 W b0 W c0 W d0 W e0 W f0 W g0
WRITE WRITE WRITE WRITE
Addr b Addr c Addr d Addr e
WRITE
Addr f
WRITE
Addr g
X23080-080619
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The timing requirement for app_wdf_data, app_wdf_wren, and app_wdf_end relative totheir associated write command is the same for back-to-back writes as it is for single writes, asshown in the 4:1 Mode User Interface Write Timing Diagram (Memory Burst Type = BL8) figure.
The map of the application interface data to the DRAM output data can be explained with anexample.
For a 4:1 Memory Controller to DRAM clock ratio with an 8-bit memory, at the applicationinterface, if the 64-bit data driven is 0000_0806_0000_0805 (Hex), the data at the DRAMinterface is as shown in the following figure. This is for a BL8 (Burst Length 8) transaction.
Figure 13: Data at the DRAM Interface for 4:1 Mode
1000 0000 3FFF 1000 0000 3FFF 1000
0 7 0 7 0
05 08 00 06 08 00
ddr4_ck_p
ddr4_ck_n
ddr4_cs_n
ddr4_ras_n
ddr4_cas_n
ddr4_we_n
ddr4_addr
ddr4_ba
ddr4_odt
ddr4_dqs_p
ddr4_dqs_nddr4_dm
ddr4_dq
X23081-090919
The data values at different clock edges are as shown in the following table.
The following table shows a generalized representation of how DRAM DQ bus data isconcatenated to form application interface data signals. app_wdf_data is shown in thefollowing table, but the table applies equally to app_rd_data. Each byte of the DQ bus haseight bursts, Rise0 (burst 0) through Fall3 (burst 7) as shown previously in the Data Values atDifferent Clock Edges table, for a total of 64 data bits. When concatenated with Rise0 in the LSBposition and Fall3 in the MSB position, a 64-bit chunk of the app_wdf_data signal is formed.
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For example, the eight bursts of ddr4_dq[7:0] corresponds to DQ bus byte 0, and whenconcatenated as described here, they map to app_wdf_data[63:0]. To be clear on theconcatenation order, ddr4_dq[0] from Rise0 (burst 0) maps to app_wdf_data[0], andddr4_dq[7] from Fall3 (burst 7) maps to app_wdf_data[63]. The table shows a secondexample, mapping DQ byte 1 to app_wdf_data[127:64], as well as the formula for DQ byteN.
Table 28: DRAM DQ Bus Data Map
DQ BusByte
App InterfaceSignal
DDR Bus Signal at Each BL8 Burst PositionFall3 ... Rise1 Fall0 Rise0
In a similar manner to the DQ bus mapping, the DM bus maps to app_wdf_mask byconcatenating the DM bits in the same burst order. Example for the first two bytes of the DRAMbus are shown in the following table, and the formula for mapping DM for byte N is also given.
The read data is returned by the user interface in the requested order and is valid whenapp_rd_data_valid is asserted. The app_rd_data_end signal indicates the end of eachread command burst and is not needed in user logic.
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Figure 14: 4:1 Mode User Interface Read Timing Diagram (Memory Burst Type = BL8)#1
app_rd_data
clk
app_cmd
R0
READ
app_addr Addr 0
app_en
app_rd_data_valid
app_rdy
app_autoprecharge
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In the following figure, the read data returned is always in the same order as the requests madeon the address/control bus.
Figure 15: 4:1 Mode User Interface Read Timing Diagram (Memory Burst Type = BL8)#2
app_rd_data
clk
app_cmd
R0
app_addr Addr 1
app_en
app_rd_data_valid
app_rdy
Addr 0
R1
READ
app_autoprecharge
X23083-080619
Maintenance Commands
The UI can be configured by the Vivado IDE to enable two DRAM Refresh modes. The defaultmode configures the UI and the Memory Controller to automatically generate DRAM Refreshand ZQCS commands, meeting all DRAM protocol and timing requirements. The controllerinterrupts normal system traffic on a regular basis to issue these maintenance commands on theDRAM bus.
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The User mode is enabled by checking the Enable User Refresh and ZQCS Input option in theVivado IDE. In this mode, you are responsible for issuing Refresh and ZQCS commands at therate required by the DRAM component specification after init_calib_complete assertsHigh. You use the app_ref_req and app_zq_req signals on the UI to request Refresh andZQCS commands, and monitor app_ref_ack and app_zq_ack to know when the commandshave completed. The controller manages all DRAM timing and protocol for these commands,other than the overall Refresh or ZQCS rate, just as it does for the default DRAM Refresh mode.These request/ack ports operate independently of the other UI command ports, like app_cmdand app_en.
The controller might not preserve the exact ordering of maintenance transactions presented tothe UI on relative to regular read and write transactions. When you request a Refresh or ZQCS,the controller interrupts system traffic, just as in the default mode, and inserts the maintenancecommands. To take the best advantage of this mode, you should request maintenance commandswhen the controller is idle or at least not very busy, keeping in mind that the DRAM Refresh rateand ZQCS rate requirements cannot be violated.
The following figure shows how the User mode ports are used and how they affect the DRAMcommand bus. This diagram shows the general idea about this mode of operation and is nottiming accurate. Assuming the DRAM is idle with all banks closed, a short time afterapp_ref_req or app_zq_req signals are asserted High for one system clock cycle, thecontroller issues the requested commands on the DRAM command bus. The app_ref_req andapp_zq_req signals can be asserted on the same cycle or different cycles, and they do not haveto be asserted at the same rate. After a request signal is asserted High for one system clock, youmust keep it deasserted until the acknowledge signal asserts.
Figure 16: User Mode Ports on DRAM Command Bus Timing Diagram
system clk
app_cmd
app_en
app_rdy
app_ref_req
app_zq_req
DRAM clk
DRAM cmd
CS_n
app_ref_ack
app_zq_ack
NOP Refresh ZQCS
tRFC tZQCSX23084-080619
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The following figure shows when the app_en is asserted and read transactions are presentedcontinuously to the UI when the app_ref_req and app_zq_req are asserted. The controllerinterrupts the DRAM traffic following DRAM protocol and timing requirements, issues theRefresh and ZQCS, and then continues issuing the read transactions. Note that the app_rdysignal deasserts during this sequence. It is likely to deassert during a sequence like this becausethe controller command queue can easily fill up during tRFC or tZQCS. After the maintenancecommands are issued and normal traffic resumes on the bus, the app_rdy signal asserts andnew transactions are accepted again into the controller.
Figure 17: Read Transaction on User Interface Timing Diagram
system clk
app_cmd
app_en
app_rdy
app_ref_req
app_zq_req
DRAM clk
DRAM cmd
CS_n
app_ref_ack
app_zq_ack
Read CAS Refresh ZQCS
tRFC tZQCS
PreCharge
tRPtRTP
Activate Read CAS
Read
X23085-080619
The previous figure also shows the operation for a single-rank. In a multi-rank system, a singlerefresh request generates a DRAM Refresh command to each rank, in series, staggered by tRFC /2. The Refresh commands are staggered because they are relatively high power consumptionoperations. A ZQCS command request generates a ZQCS command to all ranks in parallel.
AXI4 Slave InterfaceThe AXI4 slave interface block maps AXI4 transactions to the UI to provide an industry-standardbus protocol interface to the Memory Controller. The AXI4 slave interface is optional in designsprovided through the DDR4 SDRAM tool. The RTL is consistent between both tools. For detailson the AXI4 signaling protocol, see the AMBA AXI4-Stream Protocol Specification (ARM IHI0051A).
The overall design is composed of separate blocks to handle each AXI channel, which allows forindependent read and write transactions. Read and write commands to the UI rely on a simpleround-robin arbiter to handle simultaneous requests.
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The address read/address write modules are responsible for chopping the AXI4 incr/wraprequests into smaller memory size burst lengths of either four or eight, and also conveying thesmaller burst lengths to the read/write data modules so they can interact with the user interface.Fixed burst type is not supported.
If ECC is enabled, all write commands with any of the mask bits enabled are issued as read-modify-write operation. Also if ECC is enabled, all write commands with none of the mask bitsenabled are issued as write operation.
AXI4 Slave Interface Parameters
The following table lists the AXI4 slave interface parameters.
Table 30: AXI4 Slave Interface Parameters
Parameter Name Allowable Values DescriptionC_S_AXI_ADDR_WIDTH DDR4: 27–37 This is the width of address read and
address write signals. It depends onmemory density and the configurationselected. It is calculated as:For DDR4: log2(RANKS) + ROW_WIDTH +COL_WIDTH + BANK_WIDTH +BANK_GROUP_WIDTH +log2(PAYLOAD_WIDTH) - 3PAYLOAD_WIDTH: This is the data width ofthe external memory interface which islimited to 8, 16, 32, or 64 for AXI designs.
C_S_AXI_DATA_WIDTH 32, 64, 128, 256, 512 This is the width of data signals. Width ofAPP_DATA_WIDTH is recommended forbetter performance. Using a smaller widthinvokes an Upsizer, which would spendclocks in packing the data.
C_S_AXI_ID_WIDTH 1–16 This is the width of ID signals for everychannel.
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Parameter Name Allowable Values DescriptionC_S_AXI_SUPPORTS_NARROW_ BURST 0, 1 This parameter is only applicable when the
C_S_AXI_DATA_WIDTH is equal toAPP_DATA_WIDTH.When C_S_AXI_DATA_WIDTH is equal toAPP_DATA_WIDTH and this parameter isenabled, the AXI slave instantiates anupsizer. When Master sends AXI Narrowtransfers (a transfer that is narrower than itsdata bus), the upsizer packs consecutivetransfers to present a single request at theUser Interface. Hence if this AXI slave canreceive Narrow transfers, the parameterC_S_AXI_SUPPORTS_NARROW_BURST mustbe enabled. If not, it results in unexpectedbehavior when the Slave receives Narrowtransfers.When C_S_AXI_DATA_WIDTH is equal toAPP_DATA_WIDTH and it is known that theAXI slave never received Narrow transfers,you can disable this parameter to avoid theinstantiation of upsizer, thus savingimplementation area. In this case, ensurethat during actual simulation the AXI Slavenever receives Narrow transfers.When C_S_AXI_DATA_WIDTH is less thanAPP_DATA_WIDTH, upsizer is alwaysinstantiated and this parameter has noeffect.
This parameter indicates the Arbitrationalgorithm scheme. See the Arbitration in AXIShim section for more information.
C_ECC ON, OFF This parameter specifies if ECC is enabled forthe design or not. ECC is always enabled for72-bit designs and disabled for all other datawidths
Related Information
Arbitration in AXI Shim
AXI Addressing
The AXI address from the AXI master is a TRUE byte address. The AXI shim converts the addressfrom the AXI master to the memory based on AXI SIZE and memory data width. The LSBs of theAXI byte address are masked to 0, depending on the data width of the memory array. If thememory array is 64 bits (8 bytes) wide, AXI address[2:0] are ignored and treated as 0. If thememory array is 16 bits (2 bytes) wide, AXI address[0] is ignored and treated as 0. DDR4 DRAMis accessed in blocks of DRAM bursts and this memory controller always uses a fixed burst lengthof 8. The UI Data Width is always eight times the PAYLOAD_WIDTH.
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UI Data Width Memory InterfaceData Width AXI Byte Address
64 8 AxADDR = app_addr[ADDR_WIDTH-1:0]
128 16 AxADDR = app_addr[ADDR_WIDTH-1:0], 1'b0
256 32 AxADDR = app_addr[ADDR_WIDTH-1:0], 2'b00
512 64 AxADDR = app_addr[ADDR_WIDTH-1:0], 3'b000
AXI4 Slave Interface Signals
The following table lists the AXI4 slave interface specific signal. ui_clk andui_clk_sync_rst to the interface is provided from the Memory Controller. AXI interface issynchronous to ui_clk.
Table 32: AXI4 Slave Interface Signals
Name Width I/O ActiveState Description
ui_clk 1 O Output clock from the core to theinterface.
ui_clk_sync_rst 1 O High Output reset from the core to theinterface.
aresetn 1 I Low Input reset to the AXI Shim and itshould be in synchronous with VersalACAP logic clock.
s_axi_awid C_S_AXI_ID_WIDTH I Write address ID
s_axi_awaddr C_S_AXI_ADDR_WIDTH I Write address
s_axi_awlen 8 I Burst length. The burst length gives theexact number of transfers in a burst.
s_axi_awsize 3 I Burst size. This signal indicates the sizeof each transfer in the burst.
s_axi_awburst 2 I Burst type. Only INCR/WRAPsupported.
s_axi_awlock 1 I Lock type (This is not used in thecurrent implementation.)
Note: When an unsupported value isselected, awburst defaults to an INCRburst type.
s_axi_awcache 4 I Cache type (This is not used in thecurrent implementation.)
s_axi_awprot 3 I Protection type (This is not used in thecurrent implementation.)
s_axi_awqos 4 I Quality of service (This is not used inthe current implementation.)
s_axi_awvalid 1 I High Write address valid. This signalindicates that valid write address andcontrol information are available.
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The AXI4 protocol calls for independent read and write address channels. The MemoryController has one address channel. The following arbitration options are available for arbitratingbetween the read and write address channels.
Time Division Multiplexing (TDM)
Equal priority is given to read and write address channels in this mode. The grant to the read andwrite address channels alternate every clock cycle. The read or write requests from the AXImaster has no bearing on the grants. For example, the read requests are served in alternativeclock cycles, even when there are no write requests. The slots are fixed and they are served intheir respective slots only.
Round-Robin
Equal priority is given to read and write address channels in this mode. The grant to the read andwrite channels depends on the last served request granted from the AXI master. For example, ifthe last performed operation is write, then it gives precedence for read operation to be servedover write operation. Similarly, if the last performed operation is read, then it gives precedencefor write operation to be served over read operation.
Read Priority (RD_PRI_REG)
Read and write address channels are served with equal priority in this mode. The requests fromthe write address channel are processed when one of the following occurs:
• No pending requests from read address channel.
• Read starve limit of 256 is reached. It is only checked at the end of the burst.
• Read wait limit of 16 is reached.
The requests from the read address channel are processed in a similar method.
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Read Priority with Starve Limit (RD_PRI_REG_STARVE_LIMIT)
The read address channel is always given priority in this mode. The requests from the writeaddress channel are processed when there are no pending requests from the read addresschannel or the starve limit for read is reached.
Write address channel is always given priority in this mode. The requests from the read addresschannel are processed when there are no pending requests from the write address channel.Arbitration outputs are registered in WRITE_PRIORITY_REG mode.
The AXI4-Lite Slave Control register block provides a processor accessible interface to the ECCmemory option. The interface is available when ECC is enabled and the primary slave interface isAXI4. The block provides interrupts, interrupt enable, ECC status, ECC enable/disable, ECCcorrectable errors counter, first failing correctable/uncorrectable data, ECC, and address. Faultinjection registers for software testing is provided when the ECC_TEST_FI_XOR (C_ECC_TEST)parameter is ON. The AXI4-Lite interface is fixed at 32 data bits and signaling follows thestandard AMBA AXI4-Stream Protocol Specification (ARM IHI 0051A).
The AXI4-Lite Control/Status register interface block is implemented in parallel to the AXI4memory-mapped interface. The block monitors the output of the native interface to capturecorrectable (single bit) and uncorrectable (multiple bit) errors. When a correctable and/oruncorrectable error occurs, the interface also captures the byte address of the failure along withthe failing data bits and ECC bits. Fault injection is provided by an XOR block placed in the writedatapath after the ECC encoding has occurred.
Only the first memory beat in a transaction can have errors inserted. For example, in a memoryconfiguration with a data width of 72 and a mode register set to burst length 8, only the first 72bits are corruptible through the fault injection interface. Interrupt generation based on either acorrectable or uncorrectable error can be independently configured with the register interface.SLVERR response is seen on the read response bus (rresp) in case of uncorrectable errors (if ECCis enabled).
ECC Enable/Disable
The ECC_ON_OFF register enables/disables the ECC decode functionality. However, encoding isalways enabled. The default value at start-up can be parameterized withC_ECC_ONOFF_RESET_VALUE. Assigning a value of 1 for the ECC_ON_OFF bit of this registerresults in the correct_en signal input into the mem_intfc to be asserted. Writing a value of 0to the ECC_ON_OFF bit of this register results in the correct_en signal to be deasserted.When correct_en is asserted, decoding is enabled, and the opposite is true when this signal isdeasserted. ECC_STATUS/ECC_CE_CNT are not updated when ECC_ON_OFF = 0. The FI_D0,FI_D1, FI_D2, and FI_D3 registers are not writable when ECC_ON_OFF = 0.
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Two vectored signals from the Memory Controller indicate an ECC error: ecc_single andecc_multiple. The ecc_single signal indicates if there has been a correctable error and theecc_multiple signal indicates if there has been an uncorrectable error. The widths ofecc_multiple and ecc_single are based on the C_NCK_PER_CLK parameter.
There can be between 0 and C_NCK_PER_CLK × 2 errors per cycle with each data beat signaledby one of the vector bits. Multiple bits of the vector can be signaled per cycle indicating thatmultiple correctable errors or multiple uncorrectable errors have been detected. Theecc_err_addr signal (discussed in the Fault Collection section) is valid during the assertion ofeither ecc_single or ecc_multiple.
The ECC_STATUS register sets the CE_STATUS bit and/or UE_STATUS bit for correctable errordetection and uncorrectable error detection, respectively.
CAUTION! Multiple bit error is a serious failure of memory because it is uncorrectable. In such cases,application cannot rely on contents of the memory. It is suggested to not perform any further transactionsto memory.
Related Information
Fault Collection
Interrupt Generation
When interrupts are enabled with the CE_EN_IRQ and/or UE_EN_IRQ bits of the ECC_EN_IRQregister, and a correctable error or uncorrectable error occurs, the interrupt signal is asserted.
Fault Collection
To aid the analysis of ECC errors, there are two banks of storage registers that collect informationon the failing ECC decode. One bank of registers is for correctable errors, and another bank is foruncorrectable errors. The failing address, undecoded data, and ECC bits are saved into theseregister banks as CE_FFA, CE_FFD, and CE_FFE for correctable errors. UE_FFA, UE_FFD, andUE_FFE are for uncorrectable errors. The data in combination with the ECC bits can helpdetermine which bit(s) have failed. CE_FFA stores the address from the ecc_err_addr signaland converts it to a byte address. Upon error detection, the data is latched into the appropriateregister. Only the first data beat with an error is stored.
When a correctable error occurs, there is also a counter that counts the number of correctableerrors that have occurred. The counter can be read from the CE_CNT register and is fixed as an8-bit counter. It does not rollover when the maximum value is incremented.
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The ECC Fault Injection registers, FI_D and FI_ECC, facilitates testing of the software drivers.When set, the ECC Fault Injection register XORs with the DDR4 SDRAM datapath to simulateerrors in the memory. It is ideal for injection to occur here because this is after the encoding hasbeen completed. There is only support to insert errors on the first data beat, therefore there aretwo to four FI_D registers to accommodate this. During operation, after the error has beeninserted into the datapath, the register clears itself.
Name Width I/O Active State Descriptions_axi_ctrl_bresp2 2 O Write response
s_axi_ctrl_bready 1 I High Response ready
s_axi_ctrl_araddr C_S_AXI_CTRL_ADDR_WIDTH I Read address
s_axi_ctrl_arvalid 1 I High Read address valid
s_axi_ctrl_arready 1 O High Read address
s_axi_ctrl_rdata C_S_AXI_CTRL_DATA_WIDTH O Read data
s_axi_ctrl_rresp 2 O Read response
s_axi_ctrl_rvalid 1 O Read valid
s_axi_ctrl_rready 1 I Read ready
interrupt 1 O High IP Global Interrupt signal
AXI4-Lite Slave Control/Status Register Map
ECC register map is shown in the following table. The register map is Little Endian. Writeaccesses to read-only or reserved values are ignored. Read accesses to write-only or reservedvalues return the value 0xDEADDEAD.
0x200 UE_FFD [31:00] R 0x0 Uncorrectable Error First Failing DataRegister
0x204 UE_FFD [63:32] R 0x0 Uncorrectable Error First Failing DataRegister
0x208 UE_FFD [95:64]1 R 0x0 Uncorrectable Error First Failing DataRegister
0x20C UE_FFD [127:96]1 R 0x0 Uncorrectable Error First Failing DataRegister
(0x210–0x27C) Reserved
0x280 UE_FFE R 0x0 Uncorrectable Error First Failing ECCRegister
(0x284–0x2BC) Reserved
0x2C0 UE_FFA[31:0] R 0x0 Uncorrectable Error First Failing Address
0x2C4 UE_FFA[63:32] R 0x0 Uncorrectable Error First Failing Address
(0x2C8–0x2FC) Reserved
0x300 FI_D[31:0]2 W 0x0 Fault Inject Data Register
0x304 FI_D[63:32]2 W 0x0 Fault Inject Data Register
0x308 FI_D[95:64]12 W 0x0 Fault Inject Data Register
0x30C FI_D[127:96]12 W 0x0 Fault Inject Data Register
(0x340–0x37C) Reserved
0x380 FI_ECC2 W 0x0 Fault Inject ECC Register
Notes:1. Data bits 64-127 are only enabled if the DQ width is 144 bits.2. FI_D* and FI_ECC* are only enabled if ECC_TEST parameter has been set to 1.
ECC_STATUS
This register holds information on the occurrence of correctable and uncorrectable errors. Thestatus bits are independently set to 1 for the first occurrence of each error type. The status bitsare cleared by writing a 1 to the corresponding bit position; that is, the status bits can only becleared to 0 and not set to 1 using a register write. The ECC Status register operatesindependently of the ECC Enable Interrupt register.
Table 36: ECC Status Register
Bits Name Core Access Reset Value Description1 CE_STATUS R/W 0 If 1, a correctable error has occurred. This bit is
cleared when a 1 is written to this bit position.
0 UE_STATUS R/W 0 If 1, an uncorrectable error has occurred. This bitis cleared when a 1 is written to this bit position.
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This register determines if the values of the CE_STATUS and UE_STATUS bits in the ECC Statusregister assert the Interrupt output signal (ECC_Interrupt). If both CE_EN_IRQ and UE_EN_IRQare set to 1 (enabled), the value of the Interrupt signal is the logical OR between the CE_STATUSand UE_STATUS bits.
Table 37: ECC Interrupt Enable Register
Bits Name Core Access Reset Value Description1 CE_EN_IRQ R/W 0 If 1, the value of the CE_STATUS bit of ECC Status
register is propagated to the Interrupt signal. If 0,the value of the CE_STATUS bit of ECC Statusregister is not propagated to the Interrupt signal.
0 UE_EN_IRQ R/W 0 If 1, the value of the UE_STATUS bit of ECC Statusregister is propagated to the Interrupt signal. If 0,the value of the UE_STATUS bit of ECC Statusregister is not propagated to the Interrupt signal.
ECC_ON_OFF
The ECC On/Off Control register allows the application to enable or disable ECC checking. Thedesign parameter, C_ECC_ONOFF_RESET_VALUE (default on) determines the reset value for theenable/disable setting of ECC. This facilitates start-up operations when ECC might or might notbe initialized in the external memory. When disabled, ECC checking is disabled for read but ECCgeneration is active for write operations.
Table 38: ECC On/Off Control Register
Bits Name CoreAccess Reset Value Description
0 ECC_ON_OFF R/W Specified by designparameter, C_ECC_ONOFF_
RESET_VALUE
If 0, ECC checking is disabled on readoperations. (ECC generation is enabledon write operations when C_ECC = 1).If 1, ECC checking is enabled on readoperations. All correctable anduncorrectable error conditions arecaptured and status is updated.
CE_CNT
This register counts the number of occurrences of correctable errors. It can be cleared or presetto any value using a register write. When the counter reaches its maximum value, it does notwrap around, but instead it stops incrementing and remains at the maximum value. The width ofthe counter is defined by the value of the C_CE_COUNTER_WIDTH parameter. The value of theCE counter width is fixed to eight bits.
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Bits Name Core Access Reset Value Description7:0 CE_CNT R/W 0 Holds the number of correctable errors
encountered.
CE_FFA[31:0]
This register stores the lower 32 bits of the decoded DRAM address (Bits[31:0]) of the firstoccurrence of an access with a correctable error. The address format is defined in the ErrorAddress section. When the CE_STATUS bit in the ECC Status register is cleared, this register isre-enabled to store the address of the next correctable error. Storing of the failing address isenabled after reset.
Table 40: Correctable Error First Failing Address[31:0] Register
Bits Name Core Access Reset Value Description31:0 CE_FFA[31:0] R 0 Address (Bits[31:0]) of the first occurrence of a
correctable error.
Related Information
Error Address
CE_FFA[63:32]
This register stores the upper 32 bits of the decoded DRAM address (Bits[55:32]) of the firstoccurrence of an access with a correctable error. The address format is defined in the ErrorAddress section. In addition, the upper byte of this register stores the ecc_single signal. Whenthe CE_STATUS bit in the ECC Status register is cleared, this register is re-enabled to store theaddress of the next correctable error. Storing of the failing address is enabled after reset.
Table 41: Correctable Error First Failing Address[63:32] Register
Bits Name Core Access Reset Value Description31:24 CE_FFA[63:56] R 0 ecc_single[7:0]. Indicates which bursts of the BL8
transaction associated with the logged addresshad a correctable error. Bit[24] corresponds to thefirst burst of the BL8 transfer.
23:0 CE_FFA[55:32] R 0 Address (Bits[55:32]) of the first occurrence of acorrectable error.
Related Information
Error Address
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This register stores the (corrected) failing data (Bits[31:0]) of the first occurrence of an accesswith a correctable error. When the CE_STATUS bit in the ECC Status register is cleared, thisregister is re-enabled to store the data of the next correctable error. Storing of the failing data isenabled after reset.
Table 42: Correctable Error First Failing Data[31:0] Register
Bits Name Core Access Reset Value Description31:0 CE_FFD[31:0] R 0 Data (Bits[31:0]) of the first occurrence of a
correctable error.
CE_FFD[63:32]
This register stores the (corrected) failing data (Bits[63:32]) of the first occurrence of an accesswith a correctable error. When the CE_STATUS bit in the ECC Status register is cleared, thisregister is re-enabled to store the data of the next correctable error. Storing of the failing data isenabled after reset.
Table 43: Correctable Error First Failing Data[63:32] Register
Bits Name Core Access Reset Value Description31:0 CE_FFD[63:32] R 0 Data (Bits[63:32]) of the first occurrence of a
correctable error.
CE_FFD[95:64]
Note: This register is only used when DQ_WIDTH == 144.
This register stores the (corrected) failing data (Bits[95:64]) of the first occurrence of an accesswith a correctable error. When the CE_STATUS bit in the ECC Status register is cleared, thisregister is re-enabled to store the data of the next correctable error. Storing of the failing data isenabled after reset.
Table 44: Correctable Error First Failing Data[95:64] Register
Bits Name Core Access Reset Value Description31:0 CE_FFD[95:64] R 0 Data (Bits[95:64]) of the first occurrence of a
correctable error.
CE_FFD[127:96]
Note: This register is only used when DQ_WIDTH == 144.
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This register stores the (corrected) failing data (Bits[127:96]) of the first occurrence of an accesswith a correctable error. When the CE_STATUS bit in the ECC Status register is cleared, thisregister is re-enabled to store the data of the next correctable error. Storing of the failing data isenabled after reset.
Table 45: Correctable Error First Failing Data[127:96] Register
Bits Name Core Access Reset Value Description31:0 CE_FFD[127:96] R 0 Data (Bits[127:96]) of the first occurrence of a
correctable error.
CE_FFE
This register stores the ECC bits of the first occurrence of an access with a correctable error.When the CE_STATUS bit in the ECC Status register is cleared, this register is re-enabled to storethe ECC of the next correctable error. Storing of the failing ECC is enabled after reset.
The table describes the register bit usage when DQ_WIDTH = 72.
Table 46: Correctable Error First Failing ECC Register for 72-Bit External MemoryWidth
Bits Name Core Access Reset Value Description7:0 CE_FFE R 0 ECC (Bits[7:0]) of the first occurrence of a
correctable error.
The table describes the register bit usage when DQ_WIDTH = 144.
Table 47: Correctable Error First Failing ECC Register for 144-Bit External MemoryWidth
Bits Name Core Access Reset Value Description15:0 CE_FFE R 0 ECC (Bits[15:0]) of the first occurrence of a
correctable error.
UE_FFA[31:0]
This register stores the decoded DRAM address (Bits[31:0]) of the first occurrence of an accesswith an uncorrectable error. The address format is defined in Error Address section. When theUE_STATUS bit in the ECC Status register is cleared, this register is re-enabled to store theaddress of the next uncorrectable error. Storing of the failing address is enabled after reset.
Table 48: Uncorrectable Error First Failing Address[31:0] Register
Bits Name Core Access Reset Value Description31:0 UE_FFA[31:0] R 0 Address (Bits[31:0]) of the first occurrence of an
uncorrectable error.
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This register stores the decoded address (Bits[55:32]) of the first occurrence of an access with anuncorrectable error. The address format is defined in the Error Address section. In addition, theupper byte of this register stores the ecc_multiple signal. When the UE_STATUS bit in theECC Status register is cleared, this register is re-enabled to store the address of the nextuncorrectable error. Storing of the failing address is enabled after reset.
Table 49: Uncorrectable Error First Failing Address[31:0] Register
Bits Name Core Access Reset Value Description31:24 UE_FFA[63:56] R 0 ecc_multiple[7:0]. Indicates which bursts of the
BL8 transaction associated with the loggedaddress had an uncorrectable error. Bit[24]corresponds to the first burst of the BL8 transfer.
23:0 UE_FFA[55:32] R 0 Address (Bits[55:32]) of the first occurrence of acorrectable error.
Related Information
Error Address
UE_FFD[31:0]
This register stores the (uncorrected) failing data (Bits[31:0]) of the first occurrence of an accesswith an uncorrectable error. When the UE_STATUS bit in the ECC Status register is cleared, thisregister is re-enabled to store the data of the next uncorrectable error. Storing of the failing datais enabled after reset.
Table 50: Uncorrectable Error First Failing Data[31:0] Register
Bits Name Core Access Reset Value Description31:0 UE_FFD[31:0] R 0 Data (Bits[31:0]) of the first occurrence of an
uncorrectable error.
UE_FFD[63:32]
This register stores the (uncorrected) failing data (Bits[63:32]) of the first occurrence of an accesswith an uncorrectable error. When the UE_STATUS bit in the ECC Status register is cleared, thisregister is re-enabled to store the data of the next uncorrectable error. Storing of the failing datais enabled after reset.
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Table 51: Uncorrectable Error First Failing Data[63:32] Register
Bits Name Core Access Reset Value Description31:0 UE_FFD[63:32] R 0 Data (Bits[63:32]) of the first occurrence of an
uncorrectable error.
UE_FFD[95:64]
Note: This register is only used when the DQ_WIDTH == 144.
This register stores the (uncorrected) failing data (Bits[95:64]) of the first occurrence of an accesswith an uncorrectable error. When the UE_STATUS bit in the ECC Status register is cleared, thisregister is re-enabled to store the data of the next uncorrectable error. Storing of the failing datais enabled after reset.
Table 52: Uncorrectable Error First Failing Data[95:64] Register
Bits Name Core Access Reset Value Description31:0 UE_FFD[95:64] R 0 Data (Bits[95:64]) of the first occurrence of an
uncorrectable error.
UE_FFD[127:96]
Note: This register is only used when the DQ_WIDTH == 144.
This register stores the (uncorrected) failing data (Bits[127:96]) of the first occurrence of anaccess with an uncorrectable error. When the UE_STATUS bit in the ECC Status register iscleared, this register is re-enabled to store the data of the next uncorrectable error. Storing of thefailing data is enabled after reset.
Table 53: Uncorrectable Error First Failing Data[127:96] Register
Bits Name Core Access Reset Value Description31:0 UE_FFD[127:96] R 0 Data (Bits[127:96]) of the first occurrence of an
uncorrectable error.
UE_FFE
This register stores the ECC bits of the first occurrence of an access with an uncorrectable error.When the UE_STATUS bit in the ECC Status register is cleared, this register is re-enabled to storethe ECC of the next uncorrectable error. Storing of the failing ECC is enabled after reset.
The table describes the register bit usage when DQ_WIDTH = 72.
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Table 54: Uncorrectable Error First Failing ECC Register for 72-Bit External MemoryWidth
Bits Name Core Access Reset Value Description7:0 UE_FFE R 0 ECC (Bits[7:0]) of the first occurrence of an
uncorrectable error.
The table describes the register bit usage when DQ_WIDTH = 144.
Table 55: Uncorrectable Error First Failing ECC Register for 144-Bit External MemoryWidth
Bits Name Core Access Reset Value Description15:0 UE_FFE R 0 ECC (Bits[15:0]) of the first occurrence of an
uncorrectable error.
FI_D0
This register is used to inject errors in data (Bits[31:0]) written to memory and can be used to testthe error correction and error signaling. The bits set in the register toggle the corresponding databits (word 0 or Bits[31:0]) of the subsequent data written to the memory without affecting theECC bits written. After the fault has been injected, the Fault Injection Data register is clearedautomatically.
The register is only implemented if C_ECC_TEST = ON or ECC_TEST_FI_XOR = ON and ECC =ON in a DDR4 SDRAM design in the Vivado IP catalog.
Injecting faults should be performed in a critical region in software; that is, writing this registerand the subsequent write to the memory must not be interrupted.
Table 56: Fault Injection Data (Word 0) Register
Bits Name Core Access Reset Value Description31:0 FI_D0 W 0 Bit positions set to 1 toggle the corresponding
Bits[31:0] of the next data word written to thememory. This register is automatically clearedafter the fault has been injected.
Special consideration must be given across FI_D0, FI_D1, FI_D2, and FI_D3 such that only asingle error condition is introduced.
FI_D1
This register is used to inject errors in data (Bits[63:32]) written to memory and can be used totest the error correction and error signaling. The bits set in the register toggle the correspondingdata bits (word 1 or Bits[63:32]) of the subsequent data written to the memory without affectingthe ECC bits written. After the fault has been injected, the Fault Injection Data register is clearedautomatically.
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This register is only implemented if C_ECC_TEST = ON or ECC_TEST_FI_XOR = ON and ECC =ON in a DDR4 SDRAM design in the Vivado IP catalog.
Injecting faults should be performed in a critical region in software; that is, writing this registerand the subsequent write to the memory must not be interrupted.
Table 57: Fault Injection Data (Word 1) Register
Bits Name Core Access Reset Value Description31:0 FI_D1 W 0 Bit positions set to 1 toggle the corresponding
Bits[63:32] of the next data word written to thememory. This register is automatically clearedafter the fault has been injected.
FI_D2
Note: This register is only used when DQ_WIDTH =144.
This register is used to inject errors in data (Bits[95:64]) written to memory and can be used totest the error correction and error signaling. The bits set in the register toggle the correspondingdata bits (word 2 or Bits[95:64]) of the subsequent data written to the memory without affectingthe ECC bits written. After the fault has been injected, the Fault Injection Data register is clearedautomatically.
This register is only implemented if C_ECC_TEST = ON or ECC_TEST_FI_XOR = ON and ECC =ON in a DDR4 SDRAM design in the Vivado IP catalog.
Injecting faults should be performed in a critical region in software; that is, writing this registerand the subsequent write to the memory must not be interrupted.
Table 58: Fault Injection Data (Word 2) Register
Bits Name Core Access Reset Value Description31:0 FI_D2 W 0 Bit positions set to 1 toggle the corresponding
Bits[95:64] of the next data word written to thememory. This register is automatically clearedafter the fault has been injected.
Special consideration must be given across FI_D0, FI_D1, FI_D2, and FI_D3 such that only asingle error condition is introduced.
FI_D3
Note: This register is only used when DQ_WIDTH =144.
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This register is used to inject errors in data (Bits[127:96]) written to memory and can be used totest the error correction and error signaling. The bits set in the register toggle the correspondingdata bits (word 3 or Bits[127:96]) of the subsequent data written to the memory withoutaffecting the ECC bits written. After the fault has been injected, the Fault Injection Data registeris cleared automatically.
The register is only implemented if C_ECC_TEST = ON or ECC_TEST_FI_XOR = ON and ECC =ON in a DDR4 SDRAM design in the Vivado IP catalog.
Injecting faults should be performed in a critical region in software; that is, writing this registerand the subsequent write to the memory must not be interrupted.
Table 59: Fault Injection Data (Word 3) Register
Bits Name Core Access Reset Value Description31:0 FI_D3 W 0 Bit positions set to 1 toggle the corresponding
Bits[127:96] of the next data word written to thememory. The register is automatically clearedafter the fault has been injected.
FI_ECC
This register is used to inject errors in the generated ECC written to the memory and can be usedto test the error correction and error signaling. The bits set in the register toggle thecorresponding ECC bits of the next data written to memory. After the fault has been injected, theFault Injection ECC register is cleared automatically.
The register is only implemented if C_ECC_TEST = ON or ECC_TEST_FI_XOR = ON and ECC =ON in a DDR4 SDRAM design in the Vivado IP catalog.
Injecting faults should be performed in a critical region in software; that is, writing this registerand the subsequent write to memory must not be interrupted.
The table describes the register bit usage when DQ_WIDTH = 72.
Bits Name Core Access Reset Value Description15:0 FI_ECC R 0 Bit positions set to 1 toggle the corresponding bit
of the next ECC written to the memory. Theregister is automatically cleared after the fault hasbeen injected.
PHY Only InterfaceThis section describes the Versal ACAP logic interface signals and key parameters of the DDR4PHY. The goal is to implement a “PHY Only” solution that connects your own custom MemoryController directly to the DDR4 SDRAM generated PHY, instead of interfacing to the userinterface or AXI Interface of a DDR4 SDRAM generated Memory Controller. The PHY interfacetakes DRAM commands, like Activate, Precharge, Refresh, etc. at its input ports and issues themdirectly to the DRAM bus.
The PHY does not take in “memory transactions” like the user and AXI interfaces, which translatetransactions into one or more DRAM commands that meet DRAM protocol and timingrequirements. The PHY interface does no DRAM protocol or timing checking. When using a PHYOnly option, you are responsible for meeting all DRAM protocol requirements and timingspecifications of all DRAM components in the system.
The PHY runs at the system clock frequency, or 1/4 of the DRAM clock frequency. The PHYtherefore accepts four DRAM commands per system clock and issues them serially onconsecutive DRAM clock cycles on the DRAM bus. In other words, the PHY interface has fourcommand slots: slots 0, 1, 2, and 3, which it accepts each system clock. The command in slotposition 0 is issued on the DRAM bus first, and the command in slot 3 is issued last. The PHYdoes have limitations as to which slots can accept read and write CAS commands. For moreinformation, see the CAS Command Timing Limitations section. Except for CAS commands, eachslot can accept arbitrary DRAM commands.
The PHY Versal ACAP logic interface has an input port for each pin on a DDR4 bus. Each PHYcommand/address input port has a width that is eight times wider than its corresponding DRAMbus pin. For example, a DDR4 bus has one act_n pin, and the PHY has an 8-bit mc_ACT_n inputport. Each pair of bits in the mc_ACT_n port corresponds to a "command slot." The two LSBs areslot0 and the two MSBs are slot3. The PHY address input port for a DDR4 design with 18address pins is 144 bits wide, with each byte corresponding to the four command slots for oneDDR4 address pin. There are two bits for each command slot in each input port of the PHY.
This is due to the underlying design of the PHY and its support for double data rate data buses.But as the DRAM command/address bus is single data rate, you must always drive the two bitsthat correspond to a command slot to the same value. See the following interface tables foradditional descriptions and examples in the timing diagrams that show how bytes and bitscorrespond to DRAM pins and command slots.
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The PHY interface has read and write data ports with eight bits for each DRAM DQ pin. Eachport bit represents one data bit on the DDR DRAM bus for a BL8 burst. Therefore one BL8 databurst for the entire DQ bus is transferred across the PHY interface on each system clock. ThePHY only supports BL8 data transfers. The data format is the same as the user interface dataformat. For more information, see the PHY section.
The PHY interface also has several control signals that you must drive and/or respond to when aread or write CAS command is issued. The control signals are used by the PHY to manage thetransfer of read and write data between the PHY interface and the DRAM bus. See the followingsignal tables and timing diagrams.
Your custom Memory Controller must wait until the PHY output calDone is asserted beforesending any DRAM commands to the PHY. The PHY initializes and trains the DRAM beforeasserting calDone. For more information on the PHY internal structures and training algorithms,see the PHY section. After calDone is asserted, the PHY is ready to accept any DRAMcommands.
The only required DRAM or PHY commands are related to VT tracking and DRAM refresh/ZQ.These requirements are detailed in VT Tracking and Refresh and ZQ sections.
Related Information
CAS Command Timing LimitationsPHYVT TrackingRefresh and ZQ
PHY Interface Signals
The PHY interface signals to the Versal ACAP logic can be categorized into six groups:
• Clocking and Reset
• Command and Address
• Write Data
• Read Data
• PHY Control
• Debug
Clocking and Reset and Debug signals are described in other sections or documents. See thecorresponding references. In this section, a description is given for each signal in the remainingfour groups and timing diagrams show examples of the signals in use.
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For more information on the clocking and reset, see the Clocking section.
Related Information
Clocking
Command and Address
The following table shows the command and address signals for a PHY only option.
Table 62: Command and Address
Signal I/O Descriptionmc_ACT_n[7:0] I DRAM ACT_n command signal for four DRAM clock cycles.
Bits[1:0] correspond to the first DRAM clock cycle, Bits[3:2] tothe second, Bits[5:4] to the third, and Bits[8:7] to the fourth.For center alignment to the DRAM clock with 1N timing, bothbits of a given bit pair should be asserted to the same value.See timing diagrams for examples. All of the command/addressports in this table follow the same eight bits per DRAM pinformat. Active-Low.
mc_ADR[ADDR_WIDTH × 8 – 1:0] I DRAM address. Eight bits in the PHY interface for each addressbit on the DRAM bus.Bits[7:0] corresponds to DRAM address Bit[0] on four DRAMclock cycles.Bits[15:8] corresponds to DRAM address Bit[1] on four DRAMclock cycles, etc.See the timing diagrams for examples. All of the multi-bit DRAMsignals in this table follow the same format of 1-byte of the PHYinterface port corresponding to four commands for one DRAMpin. Mixed active-Low and High depending on which type ofDRAM command is being issued, but follows the DRAM pinactive-High/Low behavior. The function of each byte of themc_ADR port depends on whether the memory type is DDR4and the particular DRAM command that is being issued. Thesefunctions match the DRAM address pin functions.For example, with DDR4 memory and the mc_ACT_n port bitsasserted High, mc_ADR[135:112] have the function of RAS_n,CAS_n, and WE_n pins.
mc_BA[BANK_WIDTH × 8 – 1:0] I DRAM bank address. Eight bits for each DRAM bank address.
mc_BG[BANK_GROUP_WIDTH × 8 – 1:0] I DRAM bank group address. Eight bits for each DRAM pin.
mc_C[LR_WIDTH × 8 – 1:0] I DDR4 DRAM Chip ID pin. Valid for 3DS RDIMMs only. LR_WIDTHis log2 (StackHeight) where StackHeight (S_HEIGHT) is 2 or 4.
mc_CKE[CKE_WIDTH × 8 – 1:0] I DRAM CKE. Eight bits for each DRAM pin.
mc_CS_n[CS_WIDTH × 8 – 1:0] I DRAM CS_n. Eight bits for each DRAM pin. Active-Low.
mc_ODT[ODT_WIDTH × 8 – 1:0] I DRAM ODT. Eight bits for each DRAM pin. Active-High.
mc_PAR[7:0] I DRAM address parity. Eight bits for one DRAM parity pin.
Note: This signal is valid for RDIMMs/LRDIMMs only.
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The following figure shows the functional relationship between the PHY command/address inputsignals and a DDR4 command/address bus. The diagram shows an Activate command on systemclock cycle N in the slot1 position. The mc_ACT_n[3:2] and mc_CS_n[3:2] are both assertedLow in cycle N, and all the other bits in cycle N are asserted High, generating an Activate in theslot1 position roughly two system clocks later and NOP/DESELECT commands on the othercommand slots.
On cycle N + 3, mc_CS_n and the mc_ADR bits corresponding to CAS/A15 are set to 0xFC. Thisasserts mc_ADR[121:120] and mc_CS_n[1:0] Low, and all other bits in cycle N + 3 High,generating a read command on slot0 and NOP/DESELECT commands on the other commandslots two system clocks later. With the Activate and read command separated by three systemclock cycles and taking into account the command slot position of both commands within theirsystem clock cycle, expect the separation on the DDR4 bus to be 11 DRAM clocks, as shown inthe DDR bus portion of the following figure.
Note: The following figure shows the relative position of commands on the DDR bus based on the PHYinput signals. Although the diagram shows some latency in going through the PHY to be somewhatrealistic, this diagram does not represent the absolute command latency through the PHY to the DDR bus,or the system clock to DRAM clock phase alignment. The intention of this diagram is to show the conceptof command slots at the PHY interface.
Figure 22: PHY Command/Address Input Signal with DDR4 Command/Address Bus
The following figure shows an example of using all four command slots in a single system clock.This example shows three commands to rank0, and one to rank1, in cycle N. BG and BA addresspins are included in the diagram to spread the commands over different banks to not violateDRAM protocol. The following table lists the command in each command slot.
To understand how DRAM commands to different command slots are packed together, thefollowing detailed example shows how to convert DRAM commands at the PHY interface tocommands on the DRAM command/address bus. To convert PHY interface commands to DRAMcommands, write out the PHY signal for one system clock in binary and reverse the bit order ofeach byte. You can also drop every other bit after the reversal because the bit pairs are requiredto have the same value. In the subsequent example, the mc_BA[15:0] signal has a cycle N valueof 0x0C3C:
Hex 0x0C3C
Binary 16'b0000_1100_0011_1100
Reverse bits in each byte 16'b0011_0000_0011_1100
Take the upper eight bits for DRAM BA[1] and the lower eight bits for DRAM BA[0] and theexpected pattern on the DRAM bus is:
BA[1] 00 11 00 00
0 1 0 0
Low High Low Low
BA[0] 00 11 11 00
0 1 1 0
Low High High Low
This matches the DRAM BA[1:0] signal values of 0, 3, 1, and 0 shown in Figure 23: PHYCommand/Address with All Four Command Slots.
Write Data
The table shows the write data signals for a PHY only option.
Table 64: Write Data
Signal I/O DescriptionwrData[DQ_WIDTH × 8 – 1:0] I DRAM write data. Eight bits for each DQ lane on the
DRAM bus. This port transfers data for an entire BL8write on each system clock cycle.Write data must be provided to the PHY one cycle afterthe wrDataEn output signal asserts, or two cycles after ifthe ECC parameter is set to ON. This protocol must befollowed. There is no data buffering in the PHY.
wrDataMask[DM_WIDTH × 8 – 1:0] I DRAM write DM/DBI port. One bit for each byte of thewrData port, corresponding to one bit for each byte ofeach burst of a BL8 transfer. wrDataMask is transferredon the same system clock cycle as wrData. Active-High.For DDR4 interface, wrDataMask port appears in the“Data Mask and DBI” Vivado IDE option values ofDM_NO_DBI and DM_DBI_RD.
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Signal I/O DescriptionwrDataEn O Write data required. PHY asserts this port for one cycle
for each write CAS command.Your design must provide wrData and wrDataMask atthe PHY input ports on the cycle after wrDataEn asserts,or two cycles after if the ECC parameter is set to ON.
wrDataAddr[DATA_BUF_ADDR_WIDTH – 1:0] O Optional control signal. PHY stores and returns a databuffer address for each in-flight write CAS command.The wrDataAddr signal returns the stored addresses. Itis only valid when the PHY asserts wrDataEn.You can use this signal to manage the process ofsending write data into the PHY for a write CAScommand, but this is completely optional.
tCWL[5:0] O Optional control signal. This output indicates the CASwrite latency used in the PHY.
dBufAdr[DATA_BUF_ADDR_WIDTH – I Reserved. Should be tied Low.
Read Data
The table shows the read data signals for a PHY only option.
Table 65: Read Data
Signal I/O DescriptionrdData[DQ_WIDTH × 8 – 1:0] O DRAM read data. Eight bits for each DQ lane on the
DRAM bus. This port transfers data for an entire BL8read on each system clock cycle. rdData is only validwhen the rdDataEn, per_rd_done, or rmw_rd_done isasserted. Your design must consume the read datawhen rdDataEn one of these “data valid” signals asserts.There is no data buffering in the PHY.
rdDataEn O Read data valid. This signal asserts High to indicate thatthe rdData and rdDataAddr signals are valid. rdDataEnasserts High for one system clock cycle for each BL8read, unless the read was tagged as a special type ofread.See the optional per_rd_done and rmw_rd_done signalsfor details on special reads. rdData must be consumedwhen rdDataEn asserts or data is lost. Active-High.
rdDataAddr[DATA_BUF_ADDR_WIDTH – 1:0] O Optional control signal. PHY stores and returns a databuffer address for each in-flight read CAS command.The rdDataAddr signal returns the stored addresses. It isonly valid when the PHY asserts rdDataEn, per_rd_done,or rmw_rd_done. Your design can use this signal tomanage the process of capturing and storing read dataprovided by the PHY, but this is completely optional.
per_rd_done O Optional read data valid signal. This signal indicates thata special type of read has completed and its associatedrdData and rdDataAddr signals are valid.When PHY input winInjTxn is asserted High at the sametime as mcRdCAS, the read is tagged as a special type ofread, and per_rd_done asserts instead of rdDataEn whendata is returned.
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Signal I/O Descriptionrmw_rd_done O Optional read data valid signal. This signal indicates that
a special type of read has completed and its associatedrdData and rdDataAddr signals are valid.When PHY input winRmw is asserted High at the sametime as mcRdCAS, the read is tagged as a special type ofread, and rmw_rd_done asserts instead of rdDataEnwhen data is returned.
rdDataEnd O Unused. Tied High.
PHY Control
The table shows the PHY control signals for a PHY only option.
Table 66: PHY Control
Signal I/O DescriptioncalDone O Indication that the DRAM is powered up, initialized, and
calibration is complete. This indicates that the PHYinterface is available to send commands to the DRAM.Active-High.
mcRdCAS I Read CAS command issued. This signal must be assertedfor one system clock if and only if a read CAS commandis asserted on one of the command slots at the PHYcommand/address input ports. Hold at 0x0 until calDoneasserts. Active-High.
mcWrCAS I Write CAS command issued. This signal must beasserted for one system clock if and only if a write CAScommand is asserted on one of the command slots atthe PHY command/address input ports. Hold at 0x0 untilcalDone asserts. Active-High.
winRank[1:0] I Target rank for CAS commands. This value indicateswhich rank a CAS command is issued to. It must be validwhen either mcRdCAS or mcWrCAS is asserted. The PHYpasses the value from this input to the XPHY to selectthe calibration results for the target rank of a CAScommand in multi-rank systems. In a single-ranksystem, this input port can be tied to 0x0.
mcCasSlot[1:0] I CAS command slot select. The PHY only supports CAScommands on even command slots. mcCasSlot indicateswhich of these two possible command slots a read CASor write CAS was issued on. mcCasSlot is used by thePHY to generate XPHY control signals, like DQ outputenables, that need DRAM clock cycle resolution relativeto the command slot used for a CAS command.Valid values after calDone asserts are 0x0 and 0x2. Holdat 0x0 until calDone asserts. This signal must be valid ifmcRdCAS or mcWrCAS is asserted. For moreinformation, see the CAS Command Timing Limitationssection.
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Signal I/O DescriptionmcCasSlot2 I CAS slot 2 select. mcCasSlot2 serves a similar purpose as
the mcCasSlot[1:0] signal, but mcCasSlot2 is used intiming critical logic in the PHY. Ideally mcCasSlot2should be driven from separate flops frommcCasSlot[1:0] to allow synthesis/implementation tobetter optimize timing. mcCasSlot2 and mcCasSlot[1:0]must always be consistent if mcRdCAS or mcWrCAS isasserted.To be consistent, the following must be TRUE:mcCasSlot2==mcCasSlot[1]. Hold at 0x0 until calDoneasserts. Active-High.
winInjTxn I Optional read command type indication. WhenwinInjTxn is asserted High on the same cycle asmcRdCAS, the read does not generate an assertion onrdDataEn when it completes. Instead, the per_rd_donesignal asserts, indicating that a special type of read hascompleted and that its data is valid on the rdDataoutput.In DDR4 SDRAM controller designs, the winInjTxn/per_rd_done signals are used to track non-system readtraffic by asserting winInjTxn only on read commandsissued for the purpose of VT tracking.
winRmw I Optional read command type indication. When winRmwis asserted High on the same cycle as mcRdCAS, the readdoes not generate an assertion on rdDataEn when itcompletes. Instead, the rmw_rd_done signal asserts,indicating that a special type of read has completed andthat its data is valid on the rdData output.In DDR4 SDRAM controller designs, the winRmw/rmw_rd_done signals are used to track reads issued aspart of a read-modify-write flow. The DDR4 SDRAMcontroller asserts winRmw only on read commands thatare issued for the read phase of a RMW sequence.
winBuf[DATA_BUF_ADDR_WIDTH- 1:0] I Optional control signal. When either mcRdCAS ormcWrCAS is asserted, PHY stores the value on thewinBuf signal. The value is returned on rdDataAddr orwrDataAddr, depending on whether mcRdCAS ormcWrCAS was used to capture winBuf.In DDR4 SDRAM controller designs, these signals areused to track the data buffer address used to sourcewrite data or sink read return data.
gt_data_ready I Update VT Tracking. This signal triggers the PHY to readRIU registers in the XPHY that measure how well theDQS Gate signal is aligned to the center of the read DQSpreamble, and then adjust the alignment if needed. Thissignal must be asserted periodically to keep the DQSGate aligned as voltage and temperature drift. For moreinformation, see the VT Tracking section. Hold at 0x0until calDone asserts. Active-High.
The following figure shows a write command example. On cycle N, write command “A” isasserted on the PHY command/address inputs in the slot0 position. The mcWrCAS input is alsoasserted on cycle N, and a valid rank value is asserted on the winRank signal. In the followingfigure, there is only one CS_n pin, so the only valid winRank value is 0x0. ThemcCasSlot[1:0] and mcCasSlot2 signals are valid on cycle N, and specify slot0.
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Write command “B” is then asserted on cycle N + 1 in the slot2 position, with mcWrCAS,winRank, mcCasSlot[1:0], and mcCasSlot2 asserted to valid values as well. On cycle M,PHY asserts wrDataEn to indicate that wrData and wrDataMask values corresponding tocommand A need to be driven on cycle M + 1.
The following figure shows the data and mask widths assuming an 8-bit DDR4 DQ bus width.The delay between cycle N and cycle M is controlled by the PHY, based on the CWL and ALsettings of the DRAM. wrDataEn also asserts on cycle M + 1 to indicate that wrData andwrDataMask values for command B are required on cycle M + 2. Although this example showsthat wrDataEn is asserted on two consecutive system clock cycles, you should not assume thiswill always be the case, even if mcWrCAS is asserted on consecutive clock cycles as is shownhere. There is no data buffering in the PHY and data is pulled into the PHY just in time.Depending on the CWL/AL settings and the command slot used, consecutive mcWrCASassertions might not result in consecutive wrDataEn assertions.
Figure 24: Write Command Example
System Clock
RAS/A16 - mc_ADR[135:128]
mc_ACT_n[7:0]
CAS/A15 - mc_ADR[127:120]
WE/A14 - mc_ADR[119:112] 0xCF
0xCF
0xFF
0xFF 0xFF
0xFF
0xFF
0xFF
mc_CS_n[7:0] 0xCF 0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
Cycle N Cycle N+1 Cycle M Cycle M+1 Cycle M+2
0xFF
0xFF
0xFC
0xFC
0xFC
WriteCommand
ASlot0
WriteCommand
BSlot2
mcWrCAS
winRank[1:0]
mcCasSlot[1:0]
mcCasSlot2
mcRdCAS
Rank A Rank B
0x0 0x2
wrDataEn
wrData[63:0]
wrDataMask[7:0]
Data A Data B
DM A DM B
X23090-080619
The following figure shows a read command example. Read commands are issued on cycles Nand N + 1 in slot positions 0 and 2, respectively. The mcRdCAS, winRank, mcCasSlot, andmcCasSlot2 are asserted on these cycles as well. On cycles M + 1 and M + 2, PHY assertsrdDataEn and rdData.
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Note: The separation between N and M + 1 is much larger than in the write example (previous figure). Inthe read case, the separation is determined by the full round trip latency of command output, DRAMCL/AL, and data input through PHY.
Figure 25: Read Command Example
System Clock
RAS/A16 - mc_ADR[135:128]
mc_ACT_n[7:0]
CAS/A15 - mc_ADR[127:120]
WE/A14 - mc_ADR[119:112] 0xFF
0xCF
0xFF
0xFF 0xFF
0xFF
0xFF
0xFF
mc_CS_n[7:0] 0xCF 0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
Cycle N Cycle N+1 Cycle M Cycle M+1 Cycle M+2
0xFF
0xFF
0xFC
0xFF
0xFC
ReadCommand
ASlot0
ReadCommand
BSlot2
mcWrCAS
winRank[1:0]
mcCasSlot[1:0]
mcCasSlot2
mcRdCAS
Rank A Rank B
0x0 0x2
rdDataEn
rdData[63:0] Data A Data B
X23089-080619
Related Information
CAS Command Timing LimitationsVT Tracking
Debug
The debug signals are explained in the Debug Tools section.
Related Information
Debug Tools
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All PHY parameters are configured by the DDR4 SDRAM software. The table describes the PHYparameters. These parameter values must not be modified in the DDR4 SDRAM generateddesigns. The parameters are set during core generation. The core must be regenerated to changeany parameter settings.
Table 67: PHY Only Parameters
Parameter Name Default Value Allowable Values DescriptionADDR_WIDTH 18 18.. 17 Number of DRAM Address pins
BANK_WIDTH 2 2 Number of DRAM Bank Addresspins
BANK_GROUP_WIDTH 2 2.. 1 Number of DRAM Bank Group pins
CK_WIDTH 1 2.. 1 Number of DRAM Clock pins
CKE_WIDTH 1 2.. 1 Number of DRAM CKE pins
CS_WIDTH 1 2.. 1 Number of DRAM CS pins
ODT_WIDTH 1 4.. 1 Number of DRAM ODT pins
DRAM_TYPE “DDR4” “DDR4” DRAM Technology
DQ_WIDTH 16 Minimum = 8Must be multiple of 8
Number of DRAM DQ pins in thechannel
DQS_WIDTH 2 Minimum = 1x8 DRAM - 1 per DQ
bytex4 DRAM - 1 per DQ
nibble
Number of DRAM DQS pins in thechannel
DM_WIDTH 2 Minimum = 0x8 DRAM - 1 per DQ
bytex4 DRAM - 0
Number of DRAM DM pins in thechannel
DATA_BUF_ADDR_WIDTH 5 5 Number of data buffer addressbits stored for a read or writetransaction
ODTWR 0x8421 0xFFFF .. 0x0000 Reserved for future use
ODTWRDEL 8 Set to CWL Reserved for future use
ODTWRDUR 6 7.. 6 Reserved for future use
ODTRD 0x0000 0xFFFF.. 0x0000 Reserved for future use
ODTRDDEL 11 Set to CL Reserved for future use
ODTRDDUR 6 7.. 6 Reserved for future use
ODTWR0DELODTWR0DURODTRD0DELODTRD0DURODTNOP
N/A N/A Reserved for future use
MR0 0x630 Legal SDRAMconfiguration
DRAM MR0 setting
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Parameter Name Default Value Allowable Values DescriptionMR1 0x101 Legal SDRAM
configurationDRAM MR1 setting
MR2 0x10 Legal SDRAMconfiguration
DRAM MR2 setting
MR3 0x0 Legal SDRAMconfiguration
DRAM MR3 setting
MR4 0x0 Legal SDRAMconfiguration
DRAM MR4 setting. DDR4 only.
MR5 0x400 Legal SDRAMconfiguration
DRAM MR5 setting. DDR4 only.
MR6 0x800 Legal SDRAMconfiguration
DRAM MR6 setting. DDR4 only.
SLOT0_CONFIG 0x1 0x10x30x50xF
For more information, see theSLOT0_CONFIG section.
SLOT1_CONFIG 0x0 0x00x20xC0xA
For more information, see theSLOT0_CONFIG section.
SLOT0_FUNC_CS 0x1 0x10x30x50xF
Memory bus CS_n pins used tosend all DRAM commandsincluding MRS to memory. Each bitof the parameter represents 1-bitof the CS_n bus, for example, theLSB indicates CS_n[0], and the MSBindicates CS_n[3]. For DIMMs thisparameter specifies the CS_n pinsconnected to DIMM slot 0.
Note: slot 0 used here should notbe confused with the "commandslot0" term used in the descriptionof the PHY command/addressinterface.
SLOT1_FUNC_CS 0x0 0x00x20xC0xA
See the SLOT0_FUNC_CSdescription. The only difference isthat SLOT1_FUNC_CS specifiesCS_n pins connected to DIMM slot1.
REG_CTRL OFF ONOFF
Enable RDIMM RCD initializationand calibration
CA_MIRROR OFF ONOFF
Enable Address mirroring. Thisparameter is set to ON for theDIMMs that support addressmirroring.
DDR4_REG_RC03 0x30 Legal RDIMM RCDconfiguration
RDIMM RCD control word 03
DDR4_REG_RC04 0x40 Legal RDIMM RCDconfiguration
RDIMM RCD control word 04
DDR4_REG_RC05 0x50 Legal RDIMM RCDconfiguration
RDIMM RCD control word 05
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Parameter Name Default Value Allowable Values DescriptiontCK 938 Minimum 833 DRAM clock period in ps
tXPR 72 Minimum 1.DRAM tXPR
specification in systemclocks
See JEDEC DDR SDRAMspecification.
tMOD 6 Minimum 1.DRAM tMOD
specification in systemclocks
See JEDEC DDR SDRAMspecification.
tMRD 2 Minimum 1.DRAM tMRD
specification in systemclocks
See JEDEC DDR SDRAMspecification.
tZQINIT 256 Minimum 1.DRAM tZQINIT
specification in systemclocks
See JEDEC DDR SDRAMspecification.
TCQ 100 100 Flop clock to Q in ps. Forsimulation purposes only.
EARLY_WR_DATA “OFF” OFF Reserved for future use
EXTRA_CMD_DELAY 0 2.. 0 Added command latency in systemclocks. Added command latency isrequired for some configurations.See details in CL/CWL section.
ECC “OFF” OFF Enables early wrDataEn timing forDDR4 SDRAM generatedcontrollers when set to ON. PHYonly designs must set this to OFF.
DM_DBI “DM_NODBI” “NONE”“DM_NODBI”“DM_DBIRD”
“NODM_DBIWR”“NODM_DBIRD”
“NODM_DBIWRRD”“NODM_NODBI”
DDR4 DM/DBI configuration. Fordetails, see the DM_DBI PHYParameters section.
USE_CS_PORT 1 0 = no CS_n pins1 = CS_n pins used
Controls whether or not CS_n pinsare connect to DRAM. If there areno CS_n pins the PHY initializationand training logic issues NOPsbetween DRAM commands. Ifthere are no CS_n pins, The DRAMchip select pin (CS#) must be tiedLow externally at the DRAM.
DRAM_WIDTH 8 16, 8, 4 DRAM component DQ width
RANKS 1 4, 2, 1 Number of ranks in the memorysubsystem
nCK_PER_CLK 4 4 Number of DRAM clocks persystem clock
C_FAMILY “kintexu” "kintexu""virtexu"
Device information used byMicroBlaze controller in the PHY.
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Parameter Name Default Value Allowable Values DescriptionCAL_JITTER "FULL" "FULL", "NONE" Reserved for verification. Speed up
calibration simulation. Must be setto "FULL" for all hardware testcases.
t200us 53305 decimal 0x3FFFF.. 1 Wait period after BISC complete toDRAM reset_n deassertion insystem clocks
t500us 133263 decimal 0x3FFFF.. 1 Wait period after DRAM reset_ndeassertion to CKE assertion insystem clocks
Related Information
SLOT0_CONFIGDM_DBI Parameter
EXTRA_CMD_DELAY Parameter
Depending on the number of ranks, ECC mode, and DRAM latency configuration, PHY must beprogrammed to add latency on the DRAM command address bus. This provides enough pipelinestages in the PHY programmable logic to close timing and to process mcWrCAS. Added commandlatency is generally needed at very low CWL in single-rank configurations, or in multi-rankconfigurations. Enabling ECC might also require adding command latency, but this depends onwhether your controller design (outside the PHY) depends on receiving the wrDataEn signal asystem clock cycle early to allow for generating ECC check bits.
The EXTRA_CMD_DELAY parameter is used to add one or two system clock cycles of delay onthe DRAM command/address path. The parameter does not delay the mcWrCAS or mcRdCASsignals. This gives the PHY more time from the assertion of mcWrCAS or mcRdCAS to generateXPHY control signals. To the PHY, an EXTRA_CMD_DELAY setting of one or two is the same ashaving a higher CWL or AL setting.
The table shows the required EXTRA_CMD_DELAY setting for various configurations of CWL,CL, and AL.
Table 68: EXTRA_CMD_DELAY Configuration Settings
DRAM Configuration Required EXTRA_CMD_DELAYDRAM CAS Write
Latency CWLDRAM CASLatency CL
DRAM AdditiveLatency MR1[4:3]
Single-Rankwithout ECC
Single-Rank withECC or Multi-Rank
5 5 0 1 2
5 5 1 0 1
5 5 2 1 2
5 5 3 1 2
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DRAM Configuration Required EXTRA_CMD_DELAYDRAM CAS Write
Latency CWLDRAM CASLatency CL
DRAM AdditiveLatency MR1[4:3]
Single-Rankwithout ECC
Single-Rank withECC or Multi-Rank
8 9 1 0 0
8 9 2 0 0
8 9 3 0 0
8 10 0 1 2
8 10 1 0 0
8 10 2 0 0
8 10 3 0 0
8 11 0 1 2
8 11 1 0 0
8 11 2 0 0
8 11 3 0 0
9 to 12 X 0 0 1
9 to 12 X 1, 2, or 3 0 0
≥ 13 X 0 0 0
≥ 13 X 1, 2, or 3 0 0
DM_DBI Parameter
The PHY supports the DDR4 DBI function on the read path and write path. The table shows howread and write DBI can be enabled separately or in combination.
When write DBI is enabled, Data Mask is disabled. The DM_DBI parameter only configures thePHY and the MRS parameters must also be set to configure the DRAM for DM/DBI.
Table 69: DM_DBI PHY Settings
DM_DBI Parameter Value PHY Read DBI PHY Write DBI PHY Write Data MaskNone Disabled Disabled Disabled
DM_NODBI Disabled Disabled Enabled
DM_DBIRD Enabled Disabled Enabled
NODM_DBIWR Disabled Enabled Disabled
NODM_DBIRD Enabled Disabled Disabled
NODM_DBIWRRD Enabled Enabled Disabled
NODM_NODBI Disabled Disabled Disabled
The allowed values for the DM_DBI option in the GUI are as follows for x8 and x16 parts (“✓”indicates supported and “–” indicates not supported):
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For x4 parts, the supported DM_DBI option value is "NONE."
DBI can be enabled to reduce power consumption in the interface by reducing the total numberof DQ signals driven Low and thereby reduce noise in the VCCO supply. For more information onimproved signal integrity, see AR 70006.
CAS Command Timing Limitations
The PHY only supports CAS commands on even command slots, that is, 0 and 2. This limitation isdue to the complexity of the PHY logic driven by the PHY control inputs, like the mcWrCAS andmcRdCAS signals, not the actual DRAM command signals like mc_ACT_n[7:0], which just passthrough the PHY after calDone asserts. The PHY logic is complex because it generates XPHYcontrol signals based on the DRAM CWL and CL values with DRAM clock resolution, not justsystem clock resolution.
Supporting two different command slots for CAS commands adds a significant amount of logic onthe XPHY control paths. There are very few pipeline stages available to break up the logic due toprotocol requirements of the XPHY. CAS command support on all four slots would furtherincrease the complexity and degrade timing.
Minimum Write CAS Command Spacing
The minimum Write CAS to Write CAS command spacing to different ranks is eight DRAMclocks. This is a PHY limitation. If you violate this timing, the PHY might not have enough time toswitch its internal delay settings and drive Write DQ/DQS on the DDR bus with correct timing.The internal delay settings are determined during calibration, and it varies with system layout.
Following the memory system layout guidelines ensures that a spacing of eight DRAM clocks issufficient for correct operation. Write to Write timing to the same rank is limited only by theDRAM specification and the command slot limitations for CAS commands discussed earlier.
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System layout and timing uncertainties should be considered in how your custom controller setsminimum CAS command spacing. The controller must space the CAS commands so that there areno DRAM timing violations and no DQ/DQS bus drive fights. When a DDR4 SDRAM generatedmemory controller is instantiated, the layout guidelines are considered and command spacing isadjusted accordingly for a worst case layout.
Consider Read to Write command spacing, the JEDEC DRAM specification shows the componentrequirement as: RL + BL/2 + 2 - WL. This formula only spaces the Read DQS post-amble andWrite DQS preamble by one DRAM clock on an ideal bus with no timing skews. Any DQS flighttime, write leveling uncertainty, jitter, etc. reduces this margin. When these timing errors add upto more than one DRAM clock, there is a drive fight at the Versal ACAP DQS pins which likelycorrupts the Read transaction. A DDR4 SDRAM generated controller uses the following formulato delay Write CAS after a Read CAS to allow for a worst case timing budget for a systemfollowing the layout guidelines: RL + BL/2 + 4 - WL.
Read CAS to Read CAS commands to different ranks must also be spaced by your customcontroller to avoid drive fights, particularly when reading first from a "far" rank and then from a"near" rank. A DDR4 SDRAM generated controller spaces the Read CAS commands to differentranks by at least six DRAM clock cycles.
Write CAS to Read CAS to the same rank is defined by the JEDEC DRAM specification. Yourcontroller must follow this DRAM requirement, and it ensures that there is no possibility of drivefights for Write to Read to the same rank. Write CAS to Read CAS spacing to different ranks,however, must also be limited by your controller. This spacing is not defined by the JEDECDRAM specification directly.
Write to Read to different ranks can be spaced much closer together than Write to Read to thesame rank, but factors to consider include write leveling uncertainty, jitter, and tDQSCK. A DDR4SDRAM generated controller spaces Write CAS to Read CAS to different ranks by at least sixDRAM clocks.
Additive Latency
The PHY supports DRAM additive latency. The only effect on the PHY interface due to enablingAdditive Latency (AL) in the MRS parameters is in the timing of the wrDataEn signal aftermcWrCAS assertion. The PHY takes the AL setting into account when scheduling wrDataEn. Youcan also find the rdDataEn asserts much later after mcRdCAS because the DRAM returns datamuch later. The AL setting also has an impact on whether or not the EXTRA_CMD_DELAYparameter needs to be set to a non-zero value.
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The PHY requires read commands to be issued at a minimum rate to keep the read DQS gatesignal aligned to the read DQS preamble after calDone is asserted. In addition, thegt_data_ready signal needs to be pulsed at regular intervals to instruct the PHY to update itsread DQS training values in the RIU. Finally, the PHY requires periodic gaps in read traffic toallow the XPHY to update its gate alignment circuits with the values the PHY programs into theRIU. Specifically, the PHY requires the following after calDone asserts:
1. At least one read command every 1 µs. For a multi-rank system any rank is acceptable withinthe same channel. For a Ping Pong PHY, there are multiple channels. In that case, it isnecessary to read command on each channel.
2. The gt_data_ready signal is asserted for one system clock cycle after rdDataEn orper_rd_done signal asserts at least once within each 1 µs interval.
3. There is a three contiguous system clock cycle period with no read CAS commands assertedat the PHY interface every 1 µs.
The PHY cannot interrupt traffic to meet these requirements. It is therefore your customMemory Controller's responsibility to issue DRAM commands and assert the gt_data_readyinput signal in a way that meets the above requirements.
The following figure shows two examples where the custom controller must interrupt normaltraffic to meet the VT tracking requirements. The first example is a High read bandwidthworkload with mcRdCAS asserted continuously for almost 1 µs. The controller must stop issuingread commands for three contiguous system clocks once each 1 µs period, and assertgt_data_ready once per period.
The second example is a High write bandwidth workload with mcWrCAS asserted continuouslyfor almost 1 µs. The controller must stop issuing writes, issue at least one read command, andthen assert gt_data_ready once per 1 µs period.
IMPORTANT! The controller must not violate DRAM protocol or timing requirements during this process.
Note: The VT tracking diagrams are not drawn to scale.
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A workload that has a mix of read and write traffic in every 1 µs interval might naturally meet thefirst and third VT tracking requirements listed above. In this case, the only extra step required isto assert the gt_data_ready signal every 1 µs and regular traffic would not be interrupted atall. The custom controller, however, is responsible for ensuring all three requirements are met forall workloads. DDR4 SDRAM generated controllers monitor the mcRdCAS and mcWrCAS signalsand decide each 1 µs period what actions, if any, need to be taken to meet the VT trackingrequirements. Your custom controller can implement any scheme that meets the requirementsdescribed here.
Refresh and ZQ
After calDone is asserted by the PHY, periodic DRAM refresh and ZQ calibration are theresponsibility of your custom Memory Controller. Your controller must issue refresh and ZQcommands, meet DRAM refresh and ZQ interval requirements, while meeting all other DRAMprotocol and timing requirements. For example, if a refresh is due and you have open pages inthe DRAM, you must precharge the pages, wait tRP, and then issue a refresh command, etc. ThePHY does not perform the precharge or any other part of this process for you.
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PerformanceThe efficiency of a memory system is affected by many factors including limitations due to thememory, such as cycle time (tRC) within a single bank, or Activate to Activate spacing to thesame DDR4 bank group (tRRD_L). When given multiple transactions to work on, the MemoryController schedules commands to the DRAM in a way that attempts to minimize the impact ofthese DRAM timing requirements. But there are also limitations due to the Memory Controllerarchitecture itself. This section explains the key controller limitations and options for obtainingthe best performance out of the controller.
Address MapThe app_addr to the DRAM address map is described in the User Interface section. Six mappingoptions are included:
• ROW_COLUMN_BANK
• ROW_BANK_COLUMN
• BANK_ROW_COLUMN
• ROW_COLUMN_LRANK_BANK
• ROW_LRANK_COLUMN_BANK
• ROW_COLUMN_BANK_INTLV
For a purely random address stream at the user interface, all of the options would result in asimilar efficiency. For a sequential app_addr address stream, or any workload that tends to havea small stride through the app_addr memory space, the ROW_COLUMN_BANK mappinggenerally provides a better overall efficiency. This is due to the Memory Controller architectureand the interleaving of transactions across the Group FSMs. The Group FSMs are described inthe Memory Controller section. This controller architecture impact on efficiency should beconsidered even for situations where DRAM timing is not limiting efficiency. The table showstwo mapping options for the 4 Gb (x8) DRAM components.
Table 71: DDR4 4 Gb (x8) DRAM Address Mapping without 3DS Options
DRAM AddressDDR4 4 Gb (x8)
ROW_BANK_COLUMN ROW_COLUMN_BANKRow 15 – –
Row 14 28 28
Row 13 27 27
Row 12 26 26
Row 11 25 25
Row 10 24 24
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Table 71: DDR4 4 Gb (x8) DRAM Address Mapping without 3DS Options (cont'd)
DRAM AddressDDR4 4 Gb (x8)
ROW_BANK_COLUMN ROW_COLUMN_BANKRow 9 23 23
Row 8 22 22
Row 7 21 21
Row 6 20 20
Row 5 19 19
Row 4 18 18
Row 3 17 17
Row 2 16 16
Row 1 15 15
Row 0 14 14
Column 9 9 13
Column 8 8 12
Column 7 7 11
Column 6 6 10
Column 5 5 9
Column 4 4 8
Column 3 3 7
Column 2 2 2
Column 1 1 1
Column 0 0 0
Bank 2 - -
Bank 1 11 6
Bank 0 10 5
Bank Group 1 13 4
Bank Group 0 12 3
Note: Highlighted bits are used to map addresses to Group FSMs in the controller.
From the DDR4 map, you might expect reasonable efficiency with the ROW_BANK_COLUMNoption with a simple address increment pattern. The increment pattern would generate page hitsto a single bank, which DDR4 could handle as a stream of back-to-back CAS commands resultingin high efficiency. But looking at the emphasized bank bits in the previous table show that theaddress increment pattern also maps the long stream of page hits to the same controller GroupFSM.
The same address to Group FSM mapping issue applies to x16 DRAMs. The map for DDR4 4 Gb(x16) is shown in this table. The ROW_COLUMN_BANK option gives the best efficiency withsequential address patterns. The bits used to map to the Group FSMs are highlighted.
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DRAM Address ROW_BANK_COLUMN ROW_COLUMN_BANKRow 15 – –
Row 14 27 27
Row 13 26 26
Row 12 25 25
Row 11 24 24
Row 10 23 23
Row 9 22 22
Row 8 21 21
Row 7 20 20
Row 6 19 19
Row 5 18 18
Row 4 17 17
Row 3 16 16
Row 2 15 15
Row 1 14 14
Row 0 13 13
Column 9 9 12
Column 8 8 11
Column 7 7 10
Column 6 6 9
Column 5 5 8
Column 4 4 7
Column 3 3 6
Column 2 2 2
Column 1 1 1
Column 0 0 0
Bank 2 – –
Bank 1 12 5
Bank 0 11 4
Bank Group 1 – –
Bank Group 0 10 3
For example, the following table shows how the first 12 app_addr decodes to the DRAMaddress and maps to the Group FSMs for the ROW_COLUMN_BANK mapping option.
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As mentioned in the Memory Controller section, a Group FSM can issue one CAS commandevery three system clock cycles, or every 12 DRAM clock cycles, even for page hits. Thereforewith only a single Group FSM issuing page hit commands to the DRAM for long periods, themaximum efficiency is 33%.
The same Group FSM issue exists for DDR4. With an address increment pattern and the DDR4ROW_BANK_COLUMN option, the first 4k transactions map to a single Group FSM, as well asmapping to banks within a single DRAM bank group. The DRAM would limit the addressincrement pattern efficiency due to the tCCD_L timing restriction. The controller limitation in thiscase is even more restrictive, due to the single Group FSM. Again the efficiency would be limitedto 33%.
With the ROW_COLUMN_BANK option, the address increment pattern interleaves across all theDRAM banks and bank groups and all of the Group FSMs over a small address range.
The following figure shows how the DDR4 4 Gb (x8) ROW_COLUMN_BANK address map for thefirst 128 bytes of app_addr. This graph shows how the addresses map evenly across all DRAMbanks and bank groups, and all four controller Group FSMs.
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When considering whether an address pattern at the user interface results in good DRAMefficiency, the mapping of the pattern to the controller Group FSMs is just as important as themapping to the DRAM address. The app_addr bits that map app_addr addresses to the GroupFSMs are shown in the table for 4 Gb and 8 Gb components.
Table 74: DDR4 Map Options for 4 Gb and 8 Gb
Memory Type DDR4
Map Option ROW_BANK_COLUMN ROW_COLUMN_BANK
DRAM Component Width x4, x8 x16 x4, x8, x16
Component Density – – –
4 Gb 13,12 12,10 4,3
8 Gb 13,12 12,10 4,3
Related Information
User InterfaceMemory Controller
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Controller Head of Line Blocking and Look AheadAs described in the Memory Controller section, each Group FSM has an associated transactionFIFO that is intended to improve efficiency by reducing “head of line blocking.” Head of lineblocking occurs when one or more Group FSMs are fully occupied and cannot accept any newtransactions for the moment, but the transaction presented to the user interface command portmaps to one of the unavailable Group FSMs. This not only causes a delay in issuing newtransactions to those busy FSMs, but to all the other FSMs as well, even if they are idle.
For good efficiency, you want to keep as many Group FSMs busy in parallel as you can. You couldtry changing the transaction presented to the user interface to one that maps to a different FSM,but you do not have visibility at the user interface as to which FSMs have space to take newtransactions. The transaction FIFOs prevent this type of head of line blocking until a UI commandmaps to an FSM with a full FIFO.
A Group FSM FIFO structure can hold up to six transactions, depending on the page status of thetarget rank and bank. The FIFO structure is made up of two stages that also implement a “LookAhead” function. New transactions are placed in the first FIFO stage and are operated on whenthey reach the head of the FIFO. Then depending on the transaction page status, the Group FSMeither arbitrates to open the transaction page, or if the page is already open, the FSM pushes thepage hit into the second FIFO stage. This scheme allows multiple page hits to be queued upwhile the FSM looks ahead into the logical FIFO structure for pages that need to be opened.Looking ahead into the queue allows an FSM to interleave DRAM commands for multipletransactions on the DDR bus. This helps to hide DRAM tRCD and tRP timing associated withopening and closing pages.
The following conceptual timing diagram shows the transaction flow from the UI to the DDRcommand bus, through the Group FSMs, for a series of transactions. The diagram is conceptual inthat the latency from the UI to the DDR bus is not considered and not all DRAM timingrequirements are met. Although not completely timing accurate, the diagram does follow DRAMprotocol well enough to help explain the controller features under discussion.
Four transactions are presented at the UI, the first three mapping to the Group FSM0 and thefourth to FSM1. On system clock cycle 1, FSM0 accepts transaction 1 to Row 0, Column 0, andBank 0 into its stage 1 FIFO and issues an Activate command.
On clock 2, transaction 1 is moved into the FSM0 stage 2 FIFO and transaction 2 is accepted intoFSM0 stage 1 FIFO. On clock cycles 2 through 4, FSM0 is arbitrating to issue a CAS commandfor transaction 1, and an Activate command for transaction 2. FSM0 is looking ahead to schedulecommands for transaction 2 even though transaction 1 is not complete. Note that the time whenthese DRAM commands win arbitration is determined by DRAM timing such as tRCD andcontroller pipeline delays, which explains why the commands are spaced on the DDR commandbus as shown.
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On cycle 3, transaction 3 is accepted into FSM0 stage 1 FIFO, but it is not processed until clockcycle 5 when it comes to the head of the stage 1 FIFO. Cycle 5 is where FSM0 begins lookingahead at transaction 3 while also arbitrating to issue the CAS command for transaction 2. Finallyon cycle 4, transaction 4 is accepted into FSM1 stage 1 FIFO. If FSM0 did not have at least athree deep FIFO, transaction 4 would have been blocked until cycle 6.
This diagram does not show a high efficiency transaction pattern. There are no page hits and onlytwo Group FSMs are involved. But the example does show how a single Group FSM interleavesDRAM commands for multiple transactions on the DDR bus and minimizes blocking of the UI,thereby improving efficiency.
AutoprechargeThe Memory Controller defaults to a page open policy. It leaves banks open, even when there areno transactions pending. It only closes banks when a refresh is due, a page miss transaction isbeing processed, or when explicitly instructed to issue a transaction with a RDA or WRA CAScommand. The app_autoprecharge port on the UI allows you to explicitly instruct thecontroller to issue a RDA or WRA command in the CAS command phase of processing atransaction, on a per transaction basis. You can use this signal to improve efficiency when youhave knowledge of what transactions will be sent to the UI in the future.
The following diagram is a modified version of the “look ahead” example from the previoussection. The page miss transaction that was previously presented to the UI in cycle 3 is nowmoved out to cycle 9. The controller can no longer “look ahead” and issues the Precharge to Bank0 in cycle 6 because it does not know about the page miss until cycle 9. But if you know thattransaction 1 in cycle 1 is the only transaction to Row 0 in Bank0, assert theapp_autoprecharge port in cycle 1. Then, the CAS command for transaction 1 in cycle 5 is aRDA or WRA, and the transaction to Row 1, Bank 0 in cycle 9 is no longer a page miss. Thetransaction in cycle 9 is only needed as an Activate command instead of a Precharge followed byan Activate tRP later.
A general rule for improving efficiency is to assert app_autoprecharge on the last transactionto a page. An extreme example is an address pattern that never generates page hits. In thissituation, it is best to assert app_autoprecharge on every transactions issued to the UI.
The controller has an option to automatically inject an autoprecharge on a transaction. When theForce Read and Write commands to use AutoPrecharge option is selected, the MemoryController issues a transaction to memory with an AutoPrecharge if Column address bit A3 is setHigh. This feature disables the app_autoprecharge input signal on the User Interface. TheForce option when used with the ROW_COLUMN_BANK_INTLV address mapping improvesefficiency for transaction patterns with bursts of 16 sequential addresses before switching to adifferent random address. Patterns like this are often seen in typical AXI configurations.
User Refresh and ZQCSThe Memory Controller can be configured to automatically generate DRAM refresh and ZQCSmaintenance commands to meet DRAM timing requirements. In this mode, the controller blocksthe UI transactions on a regular basis to issue the maintenance commands, reducing efficiency.
If you have knowledge of the UI traffic pattern, you might be able to schedule DRAMmaintenance commands with less impact on system efficiency. You can use the app_ref andapp_zq ports at the UI to schedule these commands when the controller is configured for UserRefresh and ZQCS. In this mode, the controller does not schedule the DRAM maintenancecommands and only issues them based on the app_ref and app_zq ports. You are responsiblefor meeting all DRAM timing requirements for refresh and ZQCS.
Consider a case where the system needs to move a large amount of data into or out of theDRAM with the highest possible efficiency over a 50 µs period. If the controller schedules themaintenance commands, this 50 µs data burst would be interrupted multiple times for refresh,reducing efficiency roughly 4%. In User Refresh mode, however, you can decide to postponerefreshes during the 50 µs burst and make them up later. The DRAM specification allows up toeight refreshes to be postponed, giving you flexibility to schedule refreshes over a 9 × tREFIperiod, more than enough to cover the 50 µs in this example.
While User Refresh and ZQCS enable you to optimize efficiency, their incorrect use can lead toDRAM timing violations and data loss in the DRAM. Use this mode only if you thoroughlyunderstand DRAM refresh and ZQCS requirements as well as the operation of the app_ref andapp_zq UI ports. The UI port operation is described in the User Interface section.
Related Information
User Interface
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Periodic ReadsThe Versal ACAP DDR PHY requires at least one DRAM RD or RDA command to be issued every1 µs. This requirement is described in the User Interface section. If this requirement is not met bythe transaction pattern at the UI, the controller detects the lack of reads and injects a readtransaction into Group FSM0. This injected read is issued to the DRAM following the normalmechanisms of the controller issuing transactions. The key difference is that no read data isreturned to the UI. This is wasted DRAM bandwidth.
User interface patterns with long strings of write transactions are affected the most by the PHYperiodic read requirement. Consider a pattern with a 50/50 read/write transaction ratio, butorganized such that the pattern alternates between 2 µs bursts of 100% page hit reads and 2 µsbursts of 100% page hit writes. There is at least one injected read in the 2 µs write burst,resulting in a loss of efficiency due to the read command and the turnaround time to switch theDRAM and DDR bus from writes to reads back to writes. This 2 µs alternating burst pattern isslightly more efficient than alternating between reads and writes every 1 µs. A 1 µs or shorteralternating pattern would eliminate the need for the controller to inject reads, but there wouldstill be more read-write turnarounds.
Bus turnarounds are expensive in terms of efficiency and should be avoided if possible. Longbursts of page hit writes, > 2 µs in duration, are still the most efficient way to write to theDRAM, but the impact of one write-read-write turnaround each 1 µs must be taken into accountwhen calculating the maximum write efficiency.
Related Information
User Interface
DIMM ConfigurationsDDR4 SDRAM memory interface supports UDIMM, RDIMM, LRDIMM, and SODIMM in multipleslot configurations.
IMPORTANT! Note that the chip select order generated by Vivado is dependent to your board design.Also, the DDR4 IP core does not read SPD. If the DIMM configuration changes, the IP must be regenerated.
In the following configurations, the empty slot is not used and it is optional to be implemented onthe board.
DDR4 UDIMM/SODIMMThe following table and figure show the four configurations supported for DDR4 UDIMM andSODIMM.
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For a dual-rank DIMM, Dual Slot configuration, follow the chip select order shown in thefollowing figure, where CS0 and CS1 are connected to Slot0 and CS2 and CS3 are connected toSlot1.
Table 77: DDR4 UDIMM Configuration
Slot0 Slot1Single-rank Empty
Dual-rank Empty
Dual-rank Dual-rank
Single-rank Single-rank
Figure 29: DDR4 UDIMM Configuration
DDR4 UDIMM
Rank = 1CS0
Rank = 1CS1
Rank = 1CS0
Rank = 2CS0
CS1
Slot 0Slot 1
Slot 0Slot 1
Slot 0Slot 1
Rank = 2CS2
CS3Rank = 2
CS0
CS1
Slot 0Slot 1
X23038-080619
DDR4 RDIMMThe following table and figure show the four configurations supported for DDR4 RDIMM.
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For a dual-rank DIMM, Dual Slot configuration, follow the chip select order shown in thefollowing figure, where CS0 and CS1 are connected to Slot0 and CS2 and CS3 are connected toSlot1.
Table 78: DDR4 RDIMM Configuration
Slot0 Slot1Single-rank Empty
Single-rank Single-rank
Dual-rank Empty
Dual-rank Dual-rank
Figure 30: DDR4 RDIMM Configuration
Rank = 1CS0
Rank = 1CS1
Rank = 1CS0
Rank = 2CS0
CS1
Slot 0Slot 1
Slot 0Slot 1
Slot 0Slot 1
Rank = 2CS2
CS3Rank = 2
CS0
CS1
Slot 0Slot 1
DDR4 RDIMM
X23086-101619
SLOT0_CONFIGIn a given DIMM configuration, the logic chip select is mapped to physical slot using an 8-bitnumber per SLOT. Each bit corresponds to a logic chip select connectivity in a SLOT.
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Example 1: Dual-Rank DIMM, Dual Slot system (total of four ranks):
SLOT0_CONFIG = 8'b0000_0011 // describes CS0 and CS1 are connected to SLOT0.SLOT1_CONFIG = 8'b0000_1100 // describes CS2 and CS3 are connected to SLOT1.SLOT0_FUNC_CS = 8'b0000_0011 // describes CS0 and CS1 in SLOT0 are functional chip select.SLOT1_FUNC_CS = 8'b0000_1100 // describes CS2 and CS3 in SLOT1 are functional chip select.SLOT0_ODD_CS = 8'b0000_0010 // describes CS1 bit corresponding to ODD functional chip select located in slot0.SLOT1_ODD_CS = 8'b0000_1000 // describes CS3 bit corresponding to ODD functional chip select located in slot1.
Example 2: Single-Rank DIMM, Dual Slot system (total of two ranks):
SLOT0_CONFIG = 8'b0000_0001 // describes CS0 is connected to SLOT0.SLOT1_CONFIG = 8'b0000_0010 // describes CS1 is connected to SLOT1.SLOT0_FUNC_CS = 8'b0000_0001 // describes CS0 in SLOT0 is functional chip select.SLOT1_FUNC_CS = 8'b0000_0010 // describes CS1 in SLOT1 is functional chip select.SLOT0_ODD_CS = 8'b0000_0000 // describes there is no ODD functional chip select located in slot0.SLOT1_ODD_CS = 8'b0000_0000 // describes there is no ODD functional chip select located in slot1.
DDR4 LRDIMMThe following table and figure show the three configurations supported for DDR4 LRDIMM.
For Dual Slot, dual-rank configuration, follow the chip select order shown in the following figure,where CS0 and CS1 are connected to Slot0 and CS2 and CS3 are connected to Slot1.
Table 79: DDR4 LRDIMM Configuration
Slot0 Slot1Dual-rank Empty
Quad-rank Empty
Dual-rank Dual-rank
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Setting Timing OptionsThe DDR4 interface is on the edge of meeting timing for certain configurations. Due to controllercomplexity, designs are failing in timing with levels of logic from eight to 11 in controller modules(u_ddr_mc instance). To meet timing for such cases, Tcl command options are supported. TheseTcl commands are supported for Controller/PHY mode of the Controller and Physical Layer.Based on the Tcl command set in the console, a few RTL parameters are going to change whichare listed in the following table. These parameters are valid for all DDR4 designs.
Table 80: Parameter Values Based on Tcl Command Option
Parameters DefaultBetter timing, +4tCK Latency
(TIMING_OP1 Tcl Option)
Best timing, +4 to +8tCKLatency Depending on
Transaction Pattern(TIMING_OP2 Tcl Option)
CAS_FIFO_BYPASS ON ON OFF
PER_RD_PERF 1’b1 1’b1 1’b0
TXN_FIFO_BYPASS ON OFF OFF
TXN_FIFO_PIPE OFF ON ON
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The table shows the default values for the four parameters. These parameters can be changedthrough the Tcl command using user parameter TIMING_OP1 or TIMING_OP2 forController/PHY mode of the Controller and Physical Layer. These Tcl options are not valid forany PHY_ONLY (Physical Layer Only and Physical Layer Ping Pong) designs.
Steps to Change RTL Parameters1. Generate DDR4 IP with Controller and Physical Layer selected.
2. In the Generate Output Products option do not select Generate instead select Skip.
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For example: set_property -dict [list config.TIMING_OP2 {true}] [get_ips ddr4_0]
4. Generate output files by selecting Generate Output Products after right-clicking IP.
The generated output files have the RTL parameter values set as per the Parameter Values Basedon Tcl Command Option table in the Setting Timing Options section.
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Timing Improvements for 3DS DesignsThe DDR4 3DS interfaces are not meeting timing for certain configurations. The failing timingpaths are in the controller modules (u_ddr_mc instance). To meet timing for such cases, the Tclcommand option is supported. Tcl command is supported for the Controller/PHY mode ofController and Physical Layer and valid for 3DS parts only (S_HEIGHT parameter value of 2 or 4).Based on the Tcl command that is set in the console, a few RTL parameters are going to changewhich are listed in the following table.
Table 81: Parameter Values Based on Tcl Command Option for 3DS
Parameters DefaultBetter Timing
(TIMING_3DS Tcl Option)
ALIAS_PAGE OFF ON
ALIAS_P_CNT OFF ON
DRAM pages are kept open as long as possible to reduce number of precharges. The controllercontains a page table per bank and rank for each bank group. With 3DS, a third dimension isadded to these page tables for logical ranks. This increases gate counts and makes timingclosures harder. But the DRAM access performance is improved. ALIAS_PAGE = ON removes thisdimension.
Similarly for 3DS, another dimension is added for logical rank to some per rank/bank counterswhich keeps track of tRAS, tRTP, and tWTP. ALIAS_P_CNT = ON removes the logical rankdimension.
Removing the third dimension does not affect correct operation of DRAM. However, it removessome of the performance advantages.
The default values of two parameters are given in the table. These parameters can be changedthrough the Tcl command using user parameter TIMING_3DS for Controller/PHY mode ofController and Physical Layer. These Tcl options are not valid for any PHY_ONLY (Physical LayerOnly and Physical Layer Ping Pong) designs.
Steps to Change RTL Parameters for 3DS Designs1. Generate DDR4 IP with Controller and Physical Layer selected.
2. In the Generate Output Products option do not select Generate instead select Skip.
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Memory IPs provide two possibilities to select the Reference Input Clock Speed. The valueallowed for Reference Input Clock Speed (ps) is always ≥ Memory Device Interface Speed (ps).
• Memory IP lists the possible Reference Input Clock Speed values based on the targetedmemory frequency (based on selected Memory Device Interface Speed).
• Otherwise, select M and D Options and target for desired Reference Input Clock Speed whichis calculated based on selected CLKFBOUT_MULT (M), DIVCLK_DIVIDE (D), andCLKOUT_DIVIDE (O) values.
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The required Reference Input Clock Speed is calculated from the M, D, and O values entered inthe GUI using the following formulas:
• XPLL_CLKOUT (MHz) = tCK / Phy_Clock_Ratio
Where tCK is the Memory Device Interface Speed selected in the Basic tab.
• CLKIN (MHz) = (XPLL_CLKOUT (MHz) × D × O) / M
CLKIN (MHz) is the calculated Reference Input Clock Speed.
• VCO (MHz) = (CLKIN (MHz)) / D
VCO (MHz) is the calculated VCO frequency.
Calculated Reference Input Clock Speed from M, D, and O values are validated as per clockingguidelines. For more information on clocking rules, see the Clocking section.
Apart from the memory specific clocking rules, validation of the possible XPLL input frequencyrange and XPLL VCO frequency range values are completed for M, D, and O in the GUI.
For Versal Prime series, see the Versal Prime Series Data Sheet: DC and AC Switching Characteristics(DS956) for XPLL Input frequency range and XPLL VCO frequency range values.
For Versal AI Core series, see the Versal AI Core Series Data Sheet: DC and AC SwitchingCharacteristics (DS957) for XPLL Input frequency range and XPLL VCO frequency range values.
For possible M, D, and O values and detailed information on clocking and the XPLL, see theVersal ACAP Clocking Resources Architecture Manual (AM003).
Related Information
DDR4 Memory Options TabDDR4 Basic TabClocking
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Design Flow StepsThis section describes customizing and generating the core, constraining the core, and thesimulation, synthesis, and implementation steps that are specific to this IP core. More detailedinformation about the standard Vivado® design flows and the IP integrator can be found in thefollowing Vivado Design Suite user guides:
• Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994)
• Vivado Design Suite User Guide: Designing with IP (UG896)
• Vivado Design Suite User Guide: Getting Started (UG910)
• Vivado Design Suite User Guide: Logic Simulation (UG900)
Customizing and Generating the CoreCAUTION! Microsoft Windows operating system has a 260-character limit for path lengths, which canaffect the Vivado® Integrated Design Environment (IDE). To avoid this issue, use the shortest possiblenames and directory locations when creating projects, defining IP or managed IP projects, and creatingblock designs.
CAUTION! For Versal® Soft DDR4 IP standalone/Vivado IP integrator designs with no debug cores (ILA/VIO), the Vivado IDE requires the CIPS IP with PL clock and PL reset ports enabled to be present in thedesign. Access the CIPS IP in the Vivado IP catalog and instantiate the CIPS IP using the defaultconfiguration with PL clock and PL reset port enabled.
This section includes information about using Xilinx® tools to customize and generate the core inthe Vivado® Design Suite.
If you are customizing and generating the core in the Vivado IP integrator, see the Vivado DesignSuite User Guide: Designing IP Subsystems using IP Integrator (UG994) for detailed information. IPintegrator might auto-compute certain configuration values when validating or generating thedesign. To check whether the values do change, see the description of the parameter in thischapter. To view the parameter value, run the validate_bd_design command in the Tclconsole.
You can customize the IP for use in your design by specifying values for the various parametersassociated with the IP core using the following steps:
Chapter 6: Design Flow Steps
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IMPORTANT! All parameters shown in the controller options dialog box are limited selection options inthis release.
For the Vivado IDE, all controllers can be created and available for instantiation.
In IP integrator, only one controller instance of Versal® Soft DDR4 Memory Controller can becreated for instantiation:
1. After a controller is added in the pull-down menu, select the Mode and Interface for thecontroller. Select the AXI4 Interface or have the option to select the Generate the PHYcomponent only.
2. Select the settings in the Clocking.
In Clocking, the Memory Time period sets the speed of the interface. The speed entereddrives the available Input Clock Time period. For more information on the clocking structure,see the Clocking section.
Related Information
Clocking
DDR4 Memory Options TabThe following figure shows the DDR4 Memory Options tab.
Chapter 6: Design Flow Steps
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• Mode Register Settings: Select the desired CAS Latency and CAS Write Latency.
DDR4 Address Mapping Options TabThe following figure shows the DDR4 Address Mapping Options tab. Select between four predefined address map options listed below. With the selection of each option, the mapping of theuser interface address to the memory address is displayed:
• ROW BANK COLUMN
• BANK ROW COLUMN
• ROW COLUMN BANK
• ROW COLUMN BANK INTLV
Figure 34: DDR4 Address Mapping Options Tab
Chapter 6: Design Flow Steps
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• Traffic Generator Options: Allows you to select Traffic Generator Options between Simpleand Advanced Traffic Generators.
• Other Advanced Options: Includes 2T timing and Force Reads and Writes with AutoPrecharge are also provided.
Setting Burst Type for PHY_ONLY DesignsFor DDR4, the default value of Burst Type is set to Sequential. This can be changed through theTcl command using the user parameter C0.DDR4_BurstType. The following table shows details ofthe C0.DDR4_BurstType user parameter.
Table 82: Burst Type User Parameter
User Parameter Value Format Default Value Possible ValuesC0.DDR4_BurstType String Sequential Sequential, Interleaved
Follow these steps to change the Burst Type value.
1. Generate DDR4 PHY_ONLY IP.
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4. Generate output files by selecting Generate Output Products after right-clicking IP.
The generated output files have the Burst Type value set as per the selected value.
Setting Additive Latency for PHY_ONLY DesignsFor DDR4, the default value of Additive Latency is set to 0. This can be changed through the Tclcommand using the user parameter AL_SEL for any PHY_ONLY (Physical Layer Only and PhysicalLayer Ping Pong designs). The table shows the AL_SEL user parameter information.
Chapter 6: Design Flow Steps
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I/O PlanningDDR4 SDRAM I/O pin planning is completed with the full design pin planning using the VivadoI/O Pin Planner. DDR4 SDRAM I/O pins can be selected through several Vivado I/O Pin Plannerfeatures including assignments using I/O Ports view, Package view, or Memory Bank/BytePlanner. Pin assignments can additionally be made through importing an XDC or modifying theexisting XDC file.
These options are available for all DDR4 SDRAM designs and multiple DDR4 SDRAM IPinstances can be completed in one setting. To learn more about the available Memory IP pinplanning options, see the Vivado Design Suite User Guide: I/O and Clock Planning (UG899).
Constraining the CoreRequired Constraints
For DDR4 SDRAM Vivado IDE, you specify the pin location constraints. For more information onI/O standard and other constraints, see the Vivado Design Suite User Guide: I/O and Clock Planning(UG899). The location is chosen by the Vivado IDE according to the banks and byte lanes chosenfor the design.
The I/O standard is chosen by the memory type selection and options in the Vivado IDE and bythe pin type. A sample for dq[0] is shown here.
For more information on clocking, see the related information.
Clock Placement
This section is not applicable for this IP core.
Banking
This section is not applicable for this IP core.
Transceiver Placement
This section is not applicable for this IP core.
I/O Standard and Placement
The DDR4 SDRAM tool generates the appropriate I/O standards and placement based on theselections made in the Vivado IDE for the interface type and options.
IMPORTANT! The set_input_delay and set_output_delay constraints are not needed on theexternal memory interface pins in this design due to the calibration process that automatically runs atstart-up. Warnings seen during implementation for the pins can be ignored.
Related Information
Clocking
SimulationFor comprehensive information about Vivado® simulation components, as well as informationabout using supported third-party tools, see the Vivado Design Suite User Guide: Logic Simulation(UG900).
For more information on simulation, see the related information.
Note: The Example Design is a Mixed Language IP and simulations should be run with the SimulationLanguage set to Mixed. If the Simulation Language is set to Verilog, then it attempts to run a netlistsimulation.
Related Information
Example Design
Chapter 6: Design Flow Steps
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Example DesignThis section contains information about the example design provided in the Vivado® DesignSuite. Vivado supports Open IP Example Design flow. To create the example design using thisflow, right-click the IP in the Source Window, as shown in the following figure and select OpenIP Example Design.
Figure 36: Open IP Example Design
This option creates a new Vivado project. Upon selecting the menu, a dialog box to enter thedirectory information for the new design project opens.
Select a directory, or use the defaults, and click OK. This launches a new Vivado with all of theexample design files and a copy of the IP.
Chapter 7: Example Design
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The following figure shows the example design with the PHY only option selected (controllermodule does not get generated).
Figure 37: Open IP Example Design with PHY Only Option Selected
Simulating the Example Design (Designs withStandard User Interface)
The example design provides a synthesizable test bench to generate a fixed simple data pattern.DDR4 SDRAM generates the Simple Traffic Generator (STG) module as example_tb for nativeinterface and example_tb_phy for PHY only interface. The STG native interface generates 100writes and 100 reads. The STG PHY only interface generates 10 writes and 10 reads.
The example design can be simulated using one of the methods in the following sections.
RECOMMENDED: If a custom wrapper is used to simulate the example design, the following parametershould be used in the custom wrapper: parameter SIMULATION = "TRUE"
The parameter SIMULATION is used to disable the calibration during simulation.
Chapter 7: Example Design
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Project-Based SimulationThis method can be used to simulate the example design using the Vivado Design Suite (IDE).Memory IP delivers IEEE encrypted memory models for DDR4.
The Vivado simulator, Questa Advanced Simulator, IES, and VCS tools are used for DDR4 IPverification at each software release. The Vivado simulation tool is used for DDR4 IP verificationfrom 2021.2 Vivado software release. The following subsections describe steps to run a project-based simulation using each supported simulator tool.
Project-Based Simulation Flow Using VivadoSimulator1. In the Open IP Example Design Vivado project, under Flow Navigator, select Simulation
Settings.
2. Select Target simulator as Vivado Simulator.
Under the Simulation tab, set the xsim.simulate.runtime to 1 ms (there are simulationRTL directives which stop the simulation after certain period of time, which is less than 1 ms)as shown in the following figure. The Generate Scripts Only option generates simulationscripts only. To run behavioral simulation, Generate Scripts Only option must be de-selected.
3. Set the Simulation Language to Mixed.
Chapter 7: Example Design
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5. In the Flow Navigator window, select Run Simulation and select Run Behavioral Simulationoption as shown:
6. Vivado invokes Vivado simulator and simulations are run in the Vivado simulator tool. Formore information, see the Vivado Design Suite User Guide: Logic Simulation (UG900).
Chapter 7: Example Design
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Project-Based Simulation Flow Using QuestaAdvanced Simulator1. Open a DDR4 SDRAM example Vivado project (Open IP Example Design...), then under Flow
Navigator, select Simulation Settings.
2. Select Target simulator as Questa Advanced Simulator.
a. Browse to the compiled libraries location and set the path on Compiled libraries locationoption.
b. Under the Simulation tab, set the modelsim.simulate.runtime to 1 ms (there aresimulation RTL directives which stop the simulation after certain period of time, which isless than 1 ms) as shown in the following figure. The Generate Scripts Only optiongenerates simulation scripts only. To run behavioral simulation, Generate Scripts Onlyoption must be de-selected.
3. Apply the settings and select OK.
4. In the Flow Navigator window, select Run Simulation and select Run Behavioral Simulationoption as shown:
Chapter 7: Example Design
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5. Vivado invokes Questa Advanced Simulator and simulations are run in the Questa AdvancedSimulator tool. For more information, see the Vivado Design Suite User Guide: Logic Simulation(UG900).
Project-Based Simulation Flow Using IES1. Open a DDR4 SDRAM example Vivado project (Open IP Example Design...), then under Flow
Navigator, select Simulation Settings.
2. Select Target simulator as Incisive Enterprise Simulator (IES).
a. Browse to the compiled libraries location and set the path on Compiled libraries locationoption.
b. Under the Simulation tab, set the ies.simulate.runtime to 1 ms (there aresimulation RTL directives which stop the simulation after certain period of time, which isless than 1 ms) as shown in the following figure. The Generate Scripts Only optiongenerates simulation scripts only. To run behavioral simulation, Generate Scripts Onlyoption must be de-selected.
Chapter 7: Example Design
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a. Browse to the compiled libraries location and set the path on Compiled libraries locationoption.
b. Under the Simulation tab, set the vcs.simulate.runtime to 1 ms (there aresimulation RTL directives which stop the simulation after certain period of time, which isless than 1 ms) as shown in the following figure. The Generate Scripts Only optiongenerates simulation scripts only. To run behavioral simulation, Generate Scripts Onlyoption must be de-selected.
3. Apply the settings and select OK.
4. In the Flow Navigator window, select Run Simulation and select Run Behavioral Simulationoption as shown:
Chapter 7: Example Design
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OverviewThis section describes the setup and behavior of the Traffic Generator. In the Versal®architecture, Traffic Generator is instantiated in the example design (example_top.sv) to drivethe memory design through the application interface as shown in the following figure.
Figure 38: Traffic Generator and Application Interface
Traffic Generator Memory IP
ApplicationInterface
app_en, app_cmd, app_addr, app_wdf_data,
app_wdf_wren, ….
app_rdy, app_wdf_rdy, app_rd_data_valid,
app_rd_data,….
X25805-100421
Two Traffic Generators are available to drive the memory design and they include:
• Simple Traffic Generator
• Advanced Traffic Generator
By default, Vivado® connects the memory design to the Simple Traffic Generator. You can chooseto use the Advanced Traffic Generator from Traffic Generator Options available under DDR4Advanced Options tab during IP configuration as shown in the following figure.
Chapter 8: Traffic Generator
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Figure 39: Selecting ATG from Traffic Generator Option
The Simple Traffic Generator is referred to as STG and the Advanced Traffic Generator is referredto as ATG for the remainder of this section.
Simple Traffic GeneratorMemory IP generates the STG modules as ddr4_tg for native interface and example_tb_phyfor PHY only interface. The STG native interface generates 100 writes and 100 reads. The STGPHY only interface generates 32 writes and 32 reads. Both address and data increase linearly.Data check is performed during reads. Data error is reported using the compare_error signal.
Chapter 8: Traffic Generator
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Advanced Traffic GeneratorIn the example design created by Vivado, the ATG is set to default setting which is described inthe next section. The default setting is recommended for most to get started. The ATG could beprogrammed differently to test memory interface with different traffic patterns. For furtherinformation on ATG programming, see the Traffic Generator Description section.
After memory initialization and calibration are done, the ATG starts sending write commands andread commands. If the memory read data does not match with the expected read data, the ATGflags compare errors through the status interface.
Related Information
Traffic Generator Description
Traffic Generator StructureIn this section, the ATG logical structure and data flow is discussed.
The ATG data flow is summarized in the following figure. The ATG is controlled and programmedthrough the VIO interface. Based on current instruction pointer value, an instruction is issued bythe ATG state machine.
Based on the traffic pattern programmed in Read/Write mode, Read and/or Write requests aresent to the application interface. Write patterns are generated by the Write Data Generation,Write Victim Pattern, and Write Address Generation engines (gray). Similarly, Read patterns aregenerated by Read Address Generation engine (dark gray).
When Write-Read-mode or Write-Once-Read-forever mode is programmed, Read data check isperformed. Read data is compared against Expected Read pattern generated by the ExpectedData Generation, Expected Victim Pattern, and Expected Address Generation engines (gray andwhite). Data compare is done in the Error Checker block. Error status is presented to the VIOinterface.
Chapter 8: Traffic Generator
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The following figure and table show the ATG state machine and its states. The ATG resets at the"Start" state. After calibration completion (init_calib_complete) and the tg_start isasserted, the ATG state moves to instruction load called the "Load" state. The "Load" stateperforms next instruction load. When the instruction load is completed, the ATG state moves toData initialization called the "Dinit" state. The "Dinit" state initializes all Data/Address generationengines. After completion of data initialization, the ATG state moves to execution called the"exe" state. The "Exe" state issues Read and/or Write requests to the application interface.
At the "Exe" state, you can pause the ATG and the ATG state moves to the "Pause" state. At the"Pause" state, the ATG can be restarted by issuing tg_restart through the VIO, or un-pausethe ATG back to the "Exe" state
At the "Exe" state, the ATG state goes through RWWait → RWload → Dinit states if Write-Readmode or Write-once-Read-forever modes are used. At the RWload state, the ATG transitionsfrom Write mode to Read mode for DDR4.
Chapter 8: Traffic Generator
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At the "Exe" state, the ATG state goes through LDWait → Load if the current instruction iscompleted. At the LDWait, the ATG waits for all Read requests to have data returned.
At the "Exe" state, the ATG state goes through DNWait → Done if the last instruction iscompleted. At the DNWait, the ATG waits for all Read requests to have data returned.
At the "Exe" state, the ATG state goes through ERRWait → ERRChk if an error is detected. At theERRWait, the ATG waits for all Read requests to have data returned. The "ERRChk" stateperforms read test by issuing read requests to the application interface and determining whether"Read" or "Write" error occurred. After read test completion, the ATG state moves to "ERRDone".
At "Done," "Pause," and "ErrDone" states, the ATG can be restarted ATG by issuing tg_restart.
Chapter 8: Traffic Generator
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Table 84: Traffic Generator State Machine States (cont'd)
State Enum DescriptionRWLoad 4 Update "Read" and/or "Write" requests to be made in "EXE" state based on read/
write mode.
ERRWait 5 Waiting until all outstanding "Read" traffic has returned and checked.
ERRChk 6 Perform read test to determine if error type is "Read" or "Write" error.
ERRDone 7 Stopped after an error. You could continue or restart TG.
Pause 8 Pause traffic.
LDWait 9 Waiting until all outstanding "Read" traffic has returned and checked. Go to Loadstate after all outstanding “Read” traffic are completed.
RWWait 10 Waiting until all outstanding "Read" traffic has returned and checked. Go to RWLoadstate after all outstanding “Read” traffic are completed.
DNWait 11 Waiting until all outstanding "Read" traffic has returned and checked. Go to Donestate after all outstanding “Read” traffic are completed.
Done 12 All instruction completed. Program or restart TG.
PauseWait 13 Waiting until all outstanding "Read" traffic has returned and checked. Go to Pausestate after all outstanding “Read” traffic are completed.
Traffic Generator Default BehaviorIn the default settings (parameter DEFAULT_MODE = 2015.3), the ATG performs memory writesfollowed by memory reads and data checks. Three types of patterns are generated sequentially:
1. PRBS23 data pattern
• PRBS23 data pattern is used per data bit. Each data bit has a different default startingseed value.
• Linear address pattern is used to cover entire memory address space.
2. Hammer Zero data pattern
• Hammer Zero pattern is used for all data bits.
• Linear address pattern is used to cover entire memory address space.
3. PRBS address pattern
• PRBS23 data pattern is used per data bit. Each data bit has a different default startingseed value.
• PRBS address pattern is used to cover entire memory address space.
The ATG repeats memory writes and reads on each of the three patterns infinitely. Forsimulations, ATG performs 1,000 PRBS23 pattern followed by 1,000 Hammer Zero pattern and1,000 PRBS address pattern.
Chapter 8: Traffic Generator
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Traffic Generator DescriptionThis section provides detailed information on using the ATG beyond the default settings.
Feature Support
In this section, the ATG basic feature support and mode of operation is described. The ATGallows you to program different traffic patterns, read-write mode, and the duration of traffic burstbased on their application.
The ATG provides one traffic pattern for a simple traffic test in the direct instruction mode orprogram up to 32 traffic patterns into the traffic pattern table for a regression test in the traffictable mode.
Each traffic pattern can be programmed with the following options:
• Address Mode: Linear, PRBS, walking1/0.
• Data Mode: Linear, PRBS 8/10/23, walking1/0, and hammer1/0.
• Read/Write Submode: When read/write mode is set to write-read, you can choose how tosend write and read commands. The first choice sends all write commands follow by readcommands. The second choice sends write and read command pseudo-randomly.
• Victim Aggressor Delay: Victim or aggressor delay when the Victim mode of "delayedaggressor" or "delayed victim" modes is used.
• Victim Select: Victim selected from the ATG VIO input or victim rotates per nibble/perbyte/per interface width.
• Number of Command Per Traffic Pattern: Number of command per traffic pattern.
• Number of NOPs After Bursts: Number of NOPs after bursts.
• Number of Bursts Before NOP: Number of bursts before NOP.
• Next Instruction Pointer: Next instruction pointer.
You can create one traffic pattern for simple traffic test using the direct instruction mode(vio_tg_direct_instr_en) or create a sequence of traffic patterns by programming a "nextinstruction" (vio_tg_instr_nxt_instr) pointer pointing to one of the 32 traffic patternentries for regression test in traffic table mode.
The example in the following table shows four traffic patterns programmed in the table mode.
Chapter 8: Traffic Generator
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The first pattern has PRBS data traffic written in Linear address space. The 1,000 writecommands are issued followed by 1,000 read commands. Twenty cycles of NOPs are insertedbetween every 100 cycle of commands. After completion of instruction0, the next instructionpoints at instruction1.
Similarly, instruction1, instruction2, and instruction3 is executed and then looped back toinstruction0
The ATG waits for calibration to complete (init_calib_complete andtg_startassertion). After the calibration complete and assertion of tg_start, the ATGstarts sending the default traffic sequence according to traffic pattern table or direct instructionprogrammed. Memory Read/Write requests are then sent through the application interface,Memory Controller, and PHY. Either program the instruction table before asserting tg_start orpause the traffic generator (by asserting vio_tg_pause), reprogram the instruction table, andrestart the test traffic for custom traffic pattern. For more information, see the Usage section.
The ATG performs error check when a traffic pattern is programmed to read/write modes thathave write requests followed by read request (that is, Write-read-mode or Write-once-Read-forever-mode). The ATG first sends all write requests to the memory. After all write requests aresent, the ATG sends read requests to the same addresses as the write requests. Then the readdata returning from memory is compared with the expected read data.
If there is no mismatch error and the ATG is not programmed into an infinite loop,vio_tg_status_done asserts to indicate run completion
Chapter 8: Traffic Generator
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The ATG has watchdog logic. The watchdog logic checks if the ATG has any request sent to theapplication interface or the application interface has any read data return within N (parameterTG_WATCH_DOG_MAX_CNT) number of cycles. This provides information on whether memorytraffic is running or stalled (because of reasons other than data mismatch).
Usage
In this section, basic usage and programming of the ATG is covered.
The ATG is programmed and controlled using the VIO interface. Instruction table programmingoptions are listed in the following table.
Table 86: Traffic Generator Instruction Options
Name BitWidth Description
Instruction Number 5 Instruction select. From 0 to 31.
Addr Mode 4 Address mode to be programmed.0 = LINEAR; (with user-defined start address)1 = PRBS; (PRBS supported range from 8 to 34 based on addresswidth.)2 = WALKING13 = WALKING04-15 = Reserved
Data Mode 4 Data mode to be programmed.0 = LINEAR1 = PRBS (PRBS supported 8, 10, 23)2 = WALKING13 = WALKING04 = HAMMER15 = HAMMER06 = Block RAM7 = CAL_CPLX8-15 = Reserved
Read/Write Mode 4 0 = Read Only (No data check)1 = Write Only (No data check)2 = Write/Read (Read performs after Write and data value is checkedagainst expected write data.)3 = Write once and Read forever (Data check on Read data)4-15 = Reserved
Read/Write Submode 2 Read/Write submode to be programmed.This is a submode option when vio_tg_instr_rw_mode is set to"WRITE_READ" mode.00 = WRITE_READ (Send all Write commands followed by Readcommands defined in the instruction.)01 = WRITE_READ_SIMULTANEOUSLY (Send Write and Readcommands pseudo-randomly.)
Note: Write is always ahead of Read.
2 and 3 = Reserved
Chapter 8: Traffic Generator
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Victim Mode 3 Victim mode to be programmed.One victim bit could be programmed using global registervio_tg_victim_bit. The rest of the bits on signal bus areconsidered to be aggressors.The following program options define aggressor behavior:0 = NO_VICTIM1 = HELD1 (All aggressor signals held at 1.)2 = HELD0 (All aggressor signals held at 0.)3 = NONINV_AGGR (All aggressor signals are same as victim.)4 = INV_AGGR (All aggressor signals are inversion of victim.)5 = DELAYED_AGGR (All aggressor signals are delayed version ofvictim. Num of cycle of delay is programmed atvio_tg_victim_aggr_delay.)6 = DELAYED_VICTIM (Victim signal is delayed version of allaggressors.)7 = CAL_CPLX (Complex Calibration pattern)
Victim Aggressor Delay 5 Define aggressor/victim pattern to be N-delay cycle of victim/aggressor, where 0 ≤ N ≤ 24.It is used when victim mode "DELAY_AGGR" or "DELAY VICTIM" modeis used in traffic pattern.
Victim Select 3 Victim bit behavior to be programmed.0 = VICTIM_EXTERNAL (Use Victim bit provided invio_tg_glb_victim_bit.)1 = VICTIM_ROTATE4 (Victim bit rotates from Bits[3:0] for everyNibble.)2 = VICTIM_ROTATE8 (Victim bit rotates from Bits[7:0] for every Byte.)3 = VICTIM_ROTATE_ALL (Victim bit rotates through all bits.)4-7 = RESERVED
Number of instruction iteration 32 Number of Read and/or Write commands to be sent.N = APP_ADDR_WIDTH – 3
Note: APP_ADDR_WIDTH is defined in example_top.sv.
Linear Address Space Calculation: Max No. of iterations = 2N
PRBS Address Space Calculation: Max No. of iterations = 2N – 1Walking1/0 Address Space Calculation: Max No. of iterations = N
Insert M NOPs between N-burst (M) 10 M = Number of NOP cycles in between Read/Write commands at userinterface at general interconnect clock, where M ≥ 1.
Insert M NOPs between N-burst (N) 32 N = Number of Read/Write commands before NOP cycle insertion atuser interface at general interconnect clock, where N ≥ 1.
Next Instruction 6 Next instruction to run.To end traffic, next instruction should point at EXIT instruction.6’b000000-6’b011111 – valid instruction6’b1????? – EXIT instruction
Using VIO to Control ATG
VIO is instantiated for the DDR4 example design to exercise the Traffic Generator modes whenthe design is generated with the ATG option.
Chapter 8: Traffic Generator
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The expected write data and the data that is read back are added to the ILA instance. Write andread data can be viewed in ILA for one byte and half burst only. Data of various bytes can beviewed by driving the appropriate value for vio_rbyte_sel which is driven through VIO.vio_rbyte_sel is a 5-bit signal and you need to pass the value through VIO for a requiredbyte and burst. Based on the value driven for vio_rbyte_sel through VIO, a correspondingDQ byte write and read data are listed in ILA.
The ATG default control connectivity in the example design created by Vivado is listed in thefollowing tables.
Note: Application interface signals are not shown in these tables. See the corresponding memory sectionfor application interface address/data width.
Table 87: General Control
Signal I/O Width DescriptionGeneral Control
vio_tg_start I 1 Enable traffic generator to proceed from"START" state to "LOAD" state aftercalibration completes.If you do not plan to programinstruction table or PRBS data seed, tiethis signal to 1'b1.If you plan to program instruction tableor PRBS data seed, set this bit to 0during reset. After reset deassertion anddone with instruction/seedprogramming, set this bit to 1 to starttraffic generator.
vio_tg_rst I 1 Reset traffic generator (synchronousreset, level sensitive).If there is outstanding traffic in memorypipeline, assert this signal long enoughuntil all outstanding transactions havecompleted.
vio_tg_restart I 1 Restart traffic generator after trafficgeneration is complete, paused, orstopped with error (level sensitive).If there is outstanding traffic in memorypipeline, assert this signal long enoughuntil all outstanding transactions havecompleted.
vio_tg_pause I 1 Pause traffic generator (level sensitive).
vio_tg_err_chk_en I 1 If enabled, stop upon first errordetected. Read test is performed todetermine whether "READ" or "WRITE"error occurred. If not enabled, continuetraffic without stop.
vio_tg_err_clear I 1 Clear all errors excluding sticky error bit(positive edge sensitive).Only use this signal whenvio_tg_status_state is eitherTG_INSTR_ERRDONE orTG_INSTR_PAUSE. Error is cleared twocycles after vio_tg_err_clear isasserted.
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Signal I/O Width Descriptionvio_tg_err_clear_all I 1 Clear all errors including sticky error bit
(positive edge sensitive)Only use this signal whenvio_tg_status_state is eitherTG_INSTR_ERRDONE orTG_INSTR_PAUSE. Error is cleared twocycles after vio_tg_err_clear isasserted.
vio_tg_err_continue I 1 Continue traffic after error(s) atTG_INSTR_ERRDONE state (positive edgesensitive).
vio_rbyte_sel I 5 Based on the value driven forvio_rbyte_sel through VIO, acorresponding DQ byte half burst writeand read data are listed in ILA.
Instruction Table Programming
vio_tg_direct_instr_en I 1 0 = Traffic Table Mode (Traffic Generatoruses traffic patterns programmed in 32-entry traffic table.)1 = Direct Instruction Mode (TrafficGenerator uses current traffic patternpresented at VIO interface.)
vio_tg_instr_program_en I 1 Enable instruction table programming(level sensitive).
vio_tg_instr_num I 5 Instruction number to be programmed.
vio_tg_instr_addr_mode I 4 Address mode to be programmed.0 = LINEAR; (with user-defined startaddress)1 = PRBS; (PRBS supported range from 8to 34 based on address width.)2 = WALKING13 = WALKING04-15 = Reserved
vio_tg_instr_data_mode I 4 Data mode to be programmed.0 = LINEAR1 = PRBS (PRBS supported 8, 10, 23)2 = WALKING13 = WALKING04 = HAMMER15 = HAMMER06 = Block RAM7 = CAL_CPLX X (Must be programmedalong with victim mode CAL_CPLX)8-15 = Reserved
vio_tg_instr_rw_mode I 4 0 = Read Only (No data check)1 = Write Only (No data check)2 = Write/Read (Read performs afterWrite and data value is checked againstexpected write data.)3 = Write once and Read forever (Datacheck on Read data)4-15 = Reserved
Chapter 8: Traffic Generator
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Signal I/O Width Descriptionvio_tg_instr_rw_submode I 2 Read/Write submode to be
programmed.This is a submode option whenvio_tg_instr_rw_mode is set to"WRITE_READ" mode.00 = WRITE_READ (Send all Writecommands followed by Read commandsdefined in the instruction.)01 = WRITE_READ_SIMULTANEOUSLY(Send Write and Read commandspseudo-randomly.)
Note: Write is always ahead of Read.
2 and 3 = Reserved
vio_tg_instr_victim_mode I 3 Victim mode to be programmed.One victim bit could be programmedusing global registervio_tg_victim_bit. The rest of thebits on signal bus are considered to beaggressors.The following program options defineaggressor behavior:0 = NO_VICTIM1 = HELD1 (All aggressor signals held at1.)2 = HELD0 (All aggressor signals held at0.)3 = NONINV_AGGR (All aggressor signalsare same as victim.)4 = INV_AGGR (All aggressor signals areinversion of victim.)5 = DELAYED_AGGR (All aggressorsignals are delayed version of victim.Num of cycle of delay is programmed atvio_tg_victim_aggr_delay.)6 = DELAYED_VICTIM (Victim signal isdelayed version of all aggressors.)7 = CAL_CPLX (Complex Calibrationpattern must be programed along withData Mode CAL_CPLX)
vio_tg_instr_victim_aggr_delay I 5 Define aggressor/victim pattern to be N-delay cycle of victim/aggressor, where 0≤ N ≤ 24.It is used when victim mode"DELAY_AGGR" or "DELAY VICTIM"mode is used in traffic pattern.
Chapter 8: Traffic Generator
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Signal I/O Width Descriptionvio_tg_instr_victim_select I 3 Victim bit behavior to be programmed.
0 = VICTIM_EXTERNAL (Use Victim bitprovided in vio_tg_glb_victim_bit.)1 = VICTIM_ROTATE4 (Victim bit rotatesfrom Bits[3:0] for every Nibble.)2 = VICTIM_ROTATE8 (Victim bit rotatesfrom Bits[7:0] for every Byte.)3 = VICTIM_ROTATE_ALL (Victim bitrotates through all bits.)4-7 = RESERVED
vio_tg_instr_num_of_iter I 32 Number of Read/Write commands toissue (number of issue must be > 0 foreach instruction programmed)
vio_tg_instr_m_nops_btw_n_burst_m I 10 M: Number of NOP cycles in betweenRead/Write commands at User interfaceat general interconnect clock.N: Number of Read/Write commandsbefore NOP cycle insertion at Userinterface at general interconnect clock.
vio_tg_instr_m_nops_btw_n_burst_n I 32 M: Number of NOP cycles in betweenRead/Write commands at User interfaceat general interconnect clock.N: Number of Read/Write commandsbefore NOP cycle insertion at Userinterface at general interconnect clock.
vio_tg_instr_nxt_instr I 6 Next instruction to run.To end traffic, next instruction shouldpoint at EXIT instruction.6’b000000-6’b011111 – valid instruction6’b1????? – EXIT instruction
PRBS Data Seed Programming
vio_tg_seed_program_en I 1 Enable seed programming (levelsensitive).
vio_tg_seed_num I 8 Seed number to be programmed.
vio_tg_seed_data I PRBS_DATA_WIDTH PRBS seed to be programmed for aselected seed number(vio_tg_seed_num).PRBS_DATA_WIDTH is by default 23.PRBS_DATA_WIDTH can support 8, 10,and 23.
Global Registers
vio_tg_glb_victim_bit I 8 Global register to define which bit indata bus is victim. It is used when victimmode is used in traffic pattern.
vio_tg_glb_start_addr I APP_ADDR_WIDTH Global register to define Start addressseed for Linear Address Mode.
Status Registers
vio_tg_status_state O 4 Traffic Generator state machine state.
vio_tg_status_err_bit_valid O 1 Error detected. It is used as trigger todetect read error.
Chapter 8: Traffic Generator
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Signal I/O Width Descriptionvio_tg_status_err_bit O APP_DATA_WIDTH Error bit mismatch. Bitwise mismatch
pattern. A1 indicates error detected inthat bit location.
vio_tg_status_err_addr O APP_ADDR_WIDTH Error Address (Address location of failedread.)
vio_tg_status_err_cnt O 32 Saturated counter that counts thenumber of assertion of the signalvio_tg_status_err_bit_valid.The counter is reset byvio_tg_err_clear andvio_tg_err_clear_all.
vio_tg_status_exp_bit_valid O 1 Expected read data valid.
vio_tg_status_exp_bit O APP_DATA_WIDTH Expected read data.
vio_tg_status_read_bit_valid O 1 Memory read data valid.
vio_tg_status_read_bit O APP_DATA_WIDTH Memory read data.
vio_tg_status_first_err_bit_valid O 1 If vio_tg_err_chk_en is set to 1,first_err_bit_valid is set to 1 whenfirst mismatch error is encountered.This register is not overwritten untilvio_tg_err_clear,vio_tg_err_continue,vio_tg_restart is triggered.
vio_tg_status_first_err_bit O APP_DATA_WIDTH Ifvio_tg_status_first_err_bit_valid is set to 1, only the first errormismatch bit pattern is stored in thisregister.
vio_tg_status_first_err_addr O APP_ADDR_WIDTH Ifvio_tg_status_first_err_bit_valid is set to 1, only the first error addressis stored in this register.
vio_tg_status_first_exp_bit_valid O 1 If vio_tg_err_chk_en is set to 1, thisrepresents expected read data validwhen first mismatch error isencountered.
vio_tg_status_first_exp_bit O APP_DATA_WIDTH Ifvio_tg_status_first_exp_bit_valid is set to 1, expected read data for thefirst mismatch error is stored in thisregister.
vio_tg_status_first_read_bit_valid O 1 If vio_tg_err_chk_en is set to 1, thisrepresents read data valid when firstmismatch error is encountered.
vio_tg_status_first_read_bit O APP_DATA_WIDTH Ifvio_tg_status_first_read_bit_valid is set to 1, read data from memoryfor the first mismatch error is stored inthis register.
Chapter 8: Traffic Generator
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Signal I/O Width Descriptionvio_tg_status_err_bit_sticky_valid O 1 Accumulated error mismatch valid over
time.This register is reset byvio_tg_err_clear,vio_tg_err_continue, andvio_tg_restart.
vio_tg_status_err_bit_sticky O APP_DATA_WIDTH Ifvio_tg_status_err_bit_sticky_valid is set to 1, this representsaccumulated error bit
vio_tg_status_err_cnt_sticky O 32 Saturated counter that counts thenumber of assertion of the signalvio_tg_status_err_bit_sticky_valid.The counter is reset byvio_tg_err_clear_all.
vio_tg_status_err_type_valid O 1 If vio_tg_err_chk_en is set to 1, readtest is performed upon the firstmismatch error. Read test returns errortype of either "READ" or "WRITE" error.This register stores valid status of readtest error type.
vio_tg_status_err_type O 1 If vio_tg_status_err_type_valid isset to 1, this represents error type resultfrom read test.0 = Write Error1 = Read Error
vio_tg_status_done O 1 All traffic programmed completes.
Note: If infinite loop is programmed,vio_tg_status_done does not assert.
vio_tg_status_wr_done O 1 This signal pulses after a WRITE-READmode instruction completes.
vio_tg_status_watch_dog_hang O 1 Watchdog hang. This register is set to 1if there is no READ/WRITE commandsent or no READ data return for a periodof time (defined in tg_param.vh).
The ATG includes multiple data error reporting features. When using the Traffic GeneratorDefault Behavior, check if there is a memory error in the Status register(vio_tg_status_err_sticky_valid) or if memory traffic stops(vio_tg_status_watch_dog_hang).
Chapter 8: Traffic Generator
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After the first memory error is seen, the ATG logs the error address(vio_tg_status_first_err_addr) and bit mismatch(vio_tg_status_first_err_bit).
The VIO signal vio_tg_err_chk_en is used to enable error checking and can report readversus write data errors on vio_tg_status_err_type whenvio_tg_status_err_type_valid is High. When using vio_tg_err_chk_en, the ATG canbe programmed to have two different behaviors when traffic error is detected.
1. Stop traffic after first error is seen.
The ATG stops traffic after first error. The ATG then performs a read-check to detect if themismatch seen is a "WRITE" error or "READ" error. When vio_tg_status_state reachesERRD one state, the read-check is completed. The vio_tg_restart can be pulsed to clearand restart ATG or the vio_tg_err_continue can be pulsed to continue traffic.
2. Continue traffic with error.
The ATG continues sending traffic. The traffic can be restarted by asserting pause(vio_tg_pause), followed by pulse restart (vio_tg_restart), then deasserting pause.
In both cases, bitwise sticky bit mismatch is available in VIO for accumulated mismatch.
When a mismatch error is encountered, use the vio_tg_status_err_bit_valid to triggerthe Vivado Logic Analyzer. All error status are presented in the vio_tg_status_* registers.
Error status can be cleared when the ATG is in either ERRDone or Pause states. Send a pulse tothe vio_tg_clear to clear all error status except sticky bit. Send a pulse to thevio_tg_clear_all to clear all error status including sticky bit.
If vio_tg_err_chk_en is enabled, the ATG performs an error check to categorize whether a“READ” or “WRITE” error is encountered. The ATG categorizes error type using the followingmechanism. When an error is first seen, the error is logged in the vio_tg_status_first*status registers. The error address would be read by the ATG for 1,024 times. If all the readsreturn data differently from the vio_tg_status_first_exp_bit register and all the readsreturn the same data, the error is categorized as “WRITE” error. Otherwise, the error iscategorized as “READ” error.
How to Program Traffic Generator Instruction
After calibration is completed, the ATG starts sending current traffic pattern presented at theVIO interface if direct instruction mode is on or default traffic sequence according to the trafficpattern table if the direct instruction mode is off.
If it is desired to run a custom traffic pattern, either program the instruction table before the ATGstarts or pause the ATG. Program the instruction table and restart the test traffic through theVIO.
Chapter 8: Traffic Generator
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Steps to program the instruction table (wait for at least one general interconnect cycle betweeneach step) are listed here.
Programming instruction table after reset:
1. Set the vio_tg_start to 0 to stop the ATG before reset deassertion.
2. Check if the vio_tg_status_state is TG_INSTR_START (hex0). Then go to commonsteps.
Programming instruction table after traffic started:
1. Set the vio_tg_start to 0 and set vio_tg_pause to 1 to pause the ATG.
2. Check and wait until the vio_tg_status_state is TG_INSTR_DONE (hexC),TG_INSTR_PAUSE (hex8), or TG_INSTR_ERRDONE (hex7).
3. Send a pulse to the vio_tg_restart. Then, go to common steps.
Common steps:
1. Set the vio_tg_instr_num_instr to the instruction number to be programmed.
2. Set all of the vio_tg_instr_* registers (instruction register) with desired traffic pattern.
3. Wait for four general interconnect cycles (optional for relaxing VIO write timing).
4. Set the vio_tg_instr_program_en to 1. This enables instruction table programming.
5. Wait for four general interconnect cycles (optional for relaxing VIO write timing).
6. Set the vio_tg_instr_program_en to 0. This disables instruction table programming.
7. Wait for four general interconnect cycles (optional for relaxing VIO write timing).
8. Repeat steps 1 to 7 if more than one instruction is programmed.
9. Optionally set the vio_tg_glb* registers (global register) if related features areprogrammed.
10.Optionally set the vio_tg_err_chk_en if you want the ATG to stop and perform read testin case of mismatch error.
11. Set the vio_tg_pause to 0 and set vio_tg_start to 1. This starts the ATG with new theprogramming.
How to Program Victim Mode/Victim Select/Victim Aggressor Delay
Basic cross-coupling patterns are supported in the victim mode. In a given Victim mode, thevictim and aggressor behaviors are controlled by the Victim Select and the Victim AggressorDelay.
First, program Victim mode to choose victim/aggressor relationship.
• Held1: All aggressors held at 1.
Chapter 8: Traffic Generator
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• NONINV_AGGR: All aggressors signals are same as victim pattern.
• INV_AGGR: All aggressor signals are inversion of victim pattern.
• DELAYED_AGGR: All aggressors are presented as delayed version of victim pattern. Delay isprogrammable (vio_tg_victim_aggr_delay).
• DELAYED_VICTIM: Victim is presented as delayed version of aggressor pattern. Delay isprogrammable (vio_tg_victim_aggr_delay).
• CAL_CPLX: Both victim and aggressor are defined as calibration complex pattern. Both DataMode and Victim Mode have to be programmed to CAL_CPLX.
After a Victim mode is selected, program the victim/aggressor select.
• Use the external VIO signal to choose victim bit (vio_tg_glb_victim_bit).
• Rotate victim per nibble (from Bits[3:0]) for every nibble.
• Rotate victim per byte (from Bits[7:0]) for every byte.
• Rotate victim in the whole memory interface.
If you selected Victim mode as DELAYED_AGGR or DELAYED_VICTIM, the number of UI cycleshifted is programmed in vio_tg_victim_aggr_delay (where 0 ≤ N ≤ 24).
Note: CAL_CPLX is a Xilinx internal mode that is used for the Calibration Complex Pattern.
How to Program PRBS Data Seed
One of the programmable traffic pattern data modes is PRBS data mode. In PRBS data mode, thePRBS Data Seed can be programmed per data bit using the VIO interface.
The following are steps to program PRBS Data Seed (wait for at least one general interconnectcycle between each step):
1. Set the vio_tg_start to 0 to stop ATG before reset deassertion.
2. Check the vio_tg_status_state to be TG_INSTR_START (hex0).
3. Set the vio_tg_seed_num and vio_tg_seed_data with the desired seed addressnumber and seed.
4. Wait for four general interconnect cycles (optional for relaxing VIO write timing).
5. Set the vio_tg_seed_program_en to 1. This enables seed programming.
6. Wait for four general interconnect cycles (optional for relaxing VIO write timing).
7. Set the vio_tg_seed_program_en to 0. This disables seed programming.
8. Wait for four general interconnect cycles (optional for relaxing VIO write timing).
Chapter 8: Traffic Generator
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DebuggingThis appendix includes details about resources available on the Xilinx® Support website anddebugging tools.
Finding Help on Xilinx.comTo help in the design and debug process when using the core, the Xilinx Support web pagecontains key resources such as product documentation, release notes, answer records,information about known issues, and links for obtaining further product support. The XilinxCommunity Forums are also available where members can learn, participate, share, and askquestions about Xilinx solutions.
DocumentationThis product guide is the main document associated with the core. This guide, along withdocumentation related to all products that aid in the design process, can be found on the XilinxSupport web page or by using the Xilinx® Documentation Navigator. Download the XilinxDocumentation Navigator from the Downloads page. For more information about this tool andthe features available, open the online help after installation.
Solution CentersSee the Xilinx Solution Centers for support on devices, software tools, and intellectual propertyat all stages of the design cycle. Topics include design assistance, advisories, and troubleshootingtips.
Answer RecordsAnswer Records include information about commonly encountered problems, helpful informationon how to resolve these problems, and any known issues with a Xilinx product. Answer Recordsare created and maintained daily ensuring that users have access to the most accurateinformation available.
Appendix B: Debugging
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Answer Records for this core can be located by using the Search Support box on the main Xilinxsupport web page. To maximize your search results, use keywords such as:
• Product name
• Tool message(s)
• Summary of the issue encountered
A filter search is available after results are returned to further target the results.
Technical SupportXilinx provides technical support on the Xilinx Community Forums for this LogiCORE™ IP productwhen used as described in the product documentation. Xilinx cannot guarantee timing,functionality, or support if you do any of the following:
• Implement the solution in devices that are not defined in the documentation.
• Customize the solution beyond that allowed in the product documentation.
• Change any section of the design labeled DO NOT MODIFY.
To ask questions, navigate to the Xilinx Community Forums.
Debug ToolsThere are many tools available to address DDR4 design issues. It is important to know whichtools are useful for debugging various situations.
XSDB DebugMemory IP includes XSDB debug support. The Memory IP stores useful core configuration,calibration, and data window information within internal block RAM. The Memory IP debugXSDB interface can be used at any point to read out this information and get valuable statisticsand feedback from the Memory IP. The information can be viewed through a Memory IP DebugGUI or through available Memory IP Debug Tcl commands.
Memory IP Debug GUI Usage
After configuring the device, the Memory IP debug core and contents are visible in the HardwareManager (see figure).
Appendix B: Debugging
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Figure 42: Memory IP Debug Properties and Configuration Windows
To export information about the properties to a spreadsheet, see the figure below which showsthe Memory IP Core Properties window. Under the Properties view, right-click anywhere in thefield, and select the Export to Spreadsheet... option in the context menu. Select the location andname of the file to save, use all the default options, and then click OK to save the file.
For more information on the Properties window menu commands, see the “Properties WindowPopup Menu Commands” section in the Vivado Design Suite User Guide: Getting Started (UG910).
Appendix B: Debugging
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The following Tcl commands are available from the Vivado® Tcl Console when connected to thehardware.
This outputs all XSDB Memory IP content that is displayed in the GUIs.
• get_hw_softmcs: Displays what Soft Memory IP cores exist in the design
• refresh_hw_device: Refreshes the whole device including all cores
• refresh_hw_mig [lindex [get_hw_softmcs] 0]: Refreshes only the Memory IP core denoted byindex (index begins with 0)
• report_property [lindex [get_hw_softmcs] 0]: Reports all of the parameters available for theMemory IP core. Where 0 is the index of the Memory IP core to be reported (index beginswith 0).
• report_debug_core: Reports all debug core peripherals connected to the Debug Hub(dbg_hub). Associates the debug core "Index" with the "Instance Name." Useful whenmultiple instances of Memory IP are instantiated within the design to associate the debugcore index with the each IP instantiation.
Example DesignGeneration of a DDR4 design through the Memory IP tool allows an example design to begenerated using the Vivado Generate IP Example Design feature. The example design includes asynthesizable test bench with a traffic generator that is fully verified in simulation and hardware.This example design can be used to observe the behavior of the Memory IP design and can alsoaid in identifying board-related problems.
For complete details on the example design, see Example Design chapter. The following sectionsdescribe using the example design to perform hardware validation.
Appendix B: Debugging
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Debug SignalsThe Versal® ACAP Memory IP designs include an XSDB debug interface that can be used to veryquickly identify calibration status and read and write window margin. This debug interface isalways included in the generated Versal ACAP Memory IP designs.
Additional debug signals for use in the Vivado Design Suite debug feature can be enabled usingthe Debug Signals option in the FPGA Options Memory IP window. Enabling this feature allowsexample design signals to be monitored using the Vivado Design Suite debug feature. Selectingthis option brings the debug signals to the top-level and connect it to a debug ILA core.
Furthermore, a VIO core can be added as needed. The debug port is disabled for functionalsimulation and can only be enabled if the signals are actively driven by the user design.
Vivado Design Suite Debug FeatureThe Vivado® Design Suite debug feature inserts logic analyzer and virtual I/O cores directly intoyour design. The debug feature also allows you to set trigger conditions to capture applicationand integrated block port signals in hardware. Captured signals can then be analyzed. Thisfeature in the Vivado IDE is used for logic debugging and validation of a design running in Xilinx®
devices.
The Vivado logic analyzer is used to interact with the logic debug LogiCORE IP cores, including:
• ILA 2.0 (and later versions)
• VIO 2.0 (and later versions)
See the Vivado Design Suite User Guide: Programming and Debugging (UG908).
Hardware DebugHardware issues can range from link bring-up to problems seen after hours of testing. Thissection provides debug steps for common issues. The Vivado Design Suite debug feature is avaluable resource to use in hardware debug. The signal names mentioned in the followingindividual sections can be probed using the Vivado Design Suite debug feature for debugging thespecific issues.
Appendix B: Debugging
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Memory IP UsageTo focus the debug of calibration or data errors, use the provided Memory IP example design onthe targeted board with the Debug Feature enabled through the Memory IP Versal® adaptivecompute acceleration platform (ACAP) GUI.
Note: Using the Memory IP example design and enabling the Debug Feature is not required to capturecalibration and window results using XSDB, but it is useful to focus the debug on a known workingsolution.
However, the debug signals and example design are required to analyze the provided IntegratedLogic Analyzer (ILA) and VIO debug signals within the Vivado Design Suite debug feature. Thelatest Memory IP release should be used to generate the example design.
General ChecksEnsure that all the timing constraints for the core were properly incorporated from the exampledesign and that all constraints were met during implementation.
1. Ensure all guidelines referenced in the Designing with the Core section (see relatedinformation) and the Versal ACAP PCB Design User Guide (UG863) have been followed.
2. See the Designing with the Core section for information on clocking, pin/bank, and resetrequirements. The Versal ACAP PCB Design User Guide (UG863) includes PCB guidelines suchas trace matching, topology and routing, noise, termination, and I/O standard requirements.Adherence to these requirements, along with proper board design and signal integrityanalysis is critical to the success of high-speed memory interfaces.
3. Measure all voltages on the board during idle and non-idle times to ensure the voltages areset appropriately and noise is within specifications.
• Ensure the termination voltage regulator (VTT) is powered on to VCCO/2.
• Ensure VREF is measured when External VREF is used and set to VCCO/2.
4. Whenever applicable, check vrp resistors.
5. Look at clock inputs to ensure that they are clean. Information on the clock inputspecification can be found in the DC and AC Switching Characteristics data sheets (LVDSinput requirements and XPLL requirements should be considered).
6. Check the reset to ensure the polarity is correct and the signal is clean.
7. Check termination. The Versal ACAP PCB Design User Guide (UG863) should be used as aguideline.
8. Perform general signal integrity analysis
• Memory IP sets the most ideal ODT setting based on the memory parts and is described inthe RTL (module ddr4_pl_0_ddr4.sv) as parameter MR1. IBIS simulations should berun to ensure terminations, the most ideal ODT, and output drive strength settings areappropriate.
Appendix B: Debugging
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• Observe dq/dqs on a scope at the memory. View the alignment of the signals, VIL/VIH,and analyze the signal integrity during both writes and reads.
• Observe the Address and Command signals on a scope at the memory. View thealignment, VIL/VIH, and analyze the signal integrity.
9. Verify the memory parts on the board(s) in test are the correct part(s) set through theMemory IP. The timing parameters and signals widths (that is, address, bank address) mustmatch between the RTL and physical parts. Read/write failures can occur due to a mismatch.
10. Driving Chip Select (cs_n) from the FPGA is not required in single-rank designs. It caninstead be tied low at the memory device according to the memory vendor’srecommendations. Ensure the appropriate selection (cs_n enable or disable) is made whenconfiguring the IP. Calibration sends commands differently based on whether cs_n isenabled or disabled. If the pin is tied low at the memory, ensure cs_n is disabled during IPconfiguration.
11. ODT is required for all DDR4 interfaces and therefore must be driven from the FPGA.Memory IP sets the most ideal ODT setting based on extensive simulation. The most idealODT value is described in the RTL (module ddr4_pl_0_ddr4.sv) as parameter MR1.External to the memory device, terminate ODT as specified in Versal ACAP PCB Design UserGuide (UG863).
12. Check for any floating pins.
• The par input for command and address parity, alert_n input/output, and the TENinput for Connectivity Test Mode are not supported by the DDR4 Versal ACAP interface.Consult the memory vendor for information on the proper connection for these pins whennot used.
• Floating reset_n or address pins can result in inconsistent failures across multiple resetsand/or power supplies. If inconsistent calibration failures are seen, check the reset_nand address pins.
13. Measure the ck/ck_n, dqs/dqs_n, and system clocks for duty cycle distortion and generalsignal integrity.
14. If Internal VREF is used, ensure that the constraints are set appropriately in the XDCconstraints file.
15. Verify trace matching requirements are met as documented in the Versal ACAP PCB DesignUser Guide (UG863).
16. Ensure that all XPLLs used in the design have obtained lock by monitoring the locked port.
17. Bring the init_calib_complete out to a pin and check with a scope or view whethercalibration completed successfully in Hardware Manager in the Memory IP Debug window.
18. Verify the configuration of the Memory IP. The XSDB output can be used to verify theMemory IP settings. For example, the clock frequencies, version of Memory IP, Mode registersettings, and the memory part configuration (see step 9) can be determined using followingtable.
Appendix B: Debugging
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MR1_RTT_NOM RTT_NOM for Ranks 1, 2, and 3 - [10:8]
MR2_8_0 MR2[8:0] Settings
MR2_17_9 MR2[17:9] Settings
MR3_8_0 MR3 [ 8:0] Settings
MR3_17_9 MR3[17:9] Settings
MR4_8_0 MR4[8:0] Settings
MR4_17_9 MR4[17:9] Settings
MR5_8_0 MR5 [8:0] Settings
MR5_17_9 MR5 [17:9] Settings
MR5_RTT_PARK RTT_NOM for Ranks 1, 2, and 3 - [8:6]
MR6_8_0 MR6 [8:0] Settings
MR6_17_9 MR6[17:9] Settings
READ_LATENCY Read Latency
WRITE_LATENCY Write Latency
DRAM_2T_MODE DRAM 2T mode disable = 0, DRAM 2T mode enable =1
DM_DBI_EN Data Mask or DBI disable = 0, Data Mask or DBI enable = 1
ADD_CMD_DLY Address command delay
PAR_ALERT_EN Parity Alert enable
19. Copy all the data reported and submit it as part of a WebCase. For more information onopening a WebCase, see the Technical Support section in the related information.
Appendix B: Debugging
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The following figure shows the overall flow of memory initialization and the different stages ofcalibration. The dark gray color is not available for this release.
Figure 46: PHY Overall Initialization and Calibration Sequence
LRDIMM Data Buffer Calibration
Read DQ Per-bit Deskew and Centering (Simple)
Enable VT Tracking
Write Leveling Calibration
Read VREF Training
DQS Gate Calibration
System Reset
XPHY BISC
Calibration Done
DDR4 SDRAM Initialization
Read DBI Deskew and Centering
Write Latency Calibration
Write DQ/DBI Per-bit Deskew and Centering (Simple)
Write DQS to DQ/DBI Centering (Complex)
Write VREF Training
Read DQS to DQ/DBI Centering (Complex)
X24736-102020
Appendix B: Debugging
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After deassertion of the system reset, the built-in self-calibration (BISC) of the PHY is run. BISCis used in the PHY to compute internal skews for use in voltage and temperature tracking aftercalibration is completed. In this calibration stage, internal delays are measured to determine thenumber of fine taps required to equal a quarter clock memory period. This is referred to as acoarse tap.
Memory Initialization
The PHY executes a JEDEC-compliant DDR4 initialization sequence after the completion ofBISC. Each DDR4 SDRAM has a series of Mode registers accessed through Mode register set(MRS) commands. These Mode registers determine various SDRAM behaviors, such as burstlength, read and write CAS latency, and additive latency. Memory IP designs do not issue acalibration failure during Memory Initialization.
LRDIMM MREP Training
MREP training aligns the Read MDQS phase with the data buffer clock. In this training mode, thememory controller sends a sequence of read commands, the DRAM sends out the MDQS, thedata buffer samples the strobe with the clock and feeds the result back on DQ. Calibrationcontinues to perform this training to find the 0 to 1 transition on the Read MDQS sampled withthe data buffer clock.
Table 89: MREP Training Register
XSDB Reg Usage Signal DescriptionBRAM_DB_MREP_MRD_LAT_RANK*_NIBBLE* One value per rank per nibble MRD latency [8:6] and MREP phase
[5:0]
LRDIMM MRD Cycle Training
This training finds the correct cycle to maintain the set Read Latency value at the data buffer. Inthis training mode, the controller pre-programs the data buffer MPR registers with the expectedpattern and issues read commands. The data buffer compares the read data with the expecteddata and feeds back the result on the DQ bus. Calibration selects the correct cycle based on theresult of the comparison.
There are no debug registers associated with this calibration stage.
LRDIMM MRD Center Training
This training aligns Read MDQS in the center of the Read MDQ window at the data buffer. In thistraining mode, the controller pre-programs the data buffer MPR registers with the expectedpattern and issues the commands. The data buffer compares the read data with the expecteddata and feeds back the result on the DQ bus. Calibration finds the left and right edges of theRead MDQ valid window and centers Read MDQS in it.
Appendix B: Debugging
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XSDB Reg Usage Signal DescriptionBRAM_DB_MRD_CENTER_RANK*_NIBBLE* One value per rank per nibble Data Buffer MRD taps [4:0]
LRDIMM DWL Training
This training aligns the Write MDQS phase with the DRAM clock. In this training mode, the databuffer drives the MDQS pulses, the DRAM samples the clock with MDQS and feeds back theresult on MDQ. The data buffer forwards this result from MDQ to DQ. Calibration continues toperform this training to find a 0 to 1 transition on the clock sampled with the Write MDQS at theDRAM.
Table 91: DWL Training Register
XSDB Reg Usage Signal DescriptionBRAM_DB_DWL_MWD_LAT_RANK*_NIBBLE* One value per rank per nibble Data Buffer phase [8:6] and Data Buffer
to DRAM latency [5:0]
LRDIMM MWD Cycle Training
This training finds the correct cycle to maintain the set Write Latency value in the DRAM. In thistraining mode, the controller pre-programs the data buffer MPR registers with the expectedpattern, issues write commands to load the data into memory, and issues reads to the memory.The data buffer compares the read data with the expected data and feeds back the result on tothe DQ bus. Calibration identifies the correct cycle based on the result of the comparison.
There are no debug registers associated with this calibration stage.
LRDIMM MWD Center Training
This training center aligns Write MDQS in the Write MDQ window at the DRAM. In this trainingmode, the controller pre-programs the data buffer MPR registers with the expected pattern,issues write commands to load the data into memory, and issues reads to the memory. The databuffer compares the read data with the expected data and feeds back the result on the DQ bus.Calibration finds the left and right edges of the MDQ valid window and centers MDQS in it.
Table 92: MWD Center Training Register
XSDB Reg Usage Signal DescriptionBRAM_DB_MWD_CENTER_RANK*_NIBBLE* One value per rank per nibble Data Buffer MWD Taps [4:0]
Appendix B: Debugging
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There are two types of debug signals used in Memory IP Versal ACAP debug. The first set is apart of a debug interface that is always included in generated Memory IP Versal ACAP designs.These signals include calibration status and tap settings that can be read at any time throughoutoperation when the Hardware Manager is open using either Tcl commands or the Memory IPDebug GUI.
The second type of debug signals are fully integrated in the IP when the Debug Signals option inthe Memory IP tool is enabled and when using the Memory IP Example Design. These signals arebrought up to the top-level and connected to a debug ILA core. These signals are documented inthe following tables.
DDR4 Debug Signals Used in Vivado Design Suite Debug Feature
The following table shows the DDR4 debug signals.
Table 93: DDR4 Debug Signals Used in Vivado Design Suite Debug Feature
Signal Signal Width Signal Description
init_calib_complete [0:0]Signifies the status of calibration.1’b0 = Calibration not complete.1’b1 = Calibration completed successfully.
cal_r*_status [127:0]
Signifies the status of each stage ofcalibration. See Table 94 for decodinginformation. See the following relevant debugsections for usage information.
Note: The * indicates the rank value. Eachrank has a separate cal_r*_status bus.
cal_post_status [8:0]Signifies the status of the memory core aftercalibration has finished. See Table 95 fordecoding information.
dbg_cal_seq [2:0]
Calibration sequence indicator, when RTL isissuing commands to the DRAM.[0] = 1’b0 -> Single Command Mode, oneDRAM command only. 1’b1 -> Back-to-BackCommand Mode. RTL is issuing back-to-backcommands.[1] = Write Leveling Mode[2] = Extended write mode enabled, whereextra data and DQS pulses are sent to theDRAM before and after the regular writeburst.
dbg_cal_seq_cnt [31:0]
Calibration command sequence count usedwhen RTL is issuing commands to the DRAM.Indicates how many DRAM commands arerequested (counts down to 0 when allcommands are sent out).
dbg_cal_seq_rd_cnt [7:0]Calibration read data burst count (countsdown to 0 when all expected bursts return),used when RTL is issuing read commands tothe DRAM.
Appendix B: Debugging
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Table 93: DDR4 Debug Signals Used in Vivado Design Suite Debug Feature (cont'd)
Signal Signal Width Signal Descriptiondbg_rd_valid [0:0] Read Data Valid
dbg_cmp_byte [5:0]Calibration byte selection (used to determinewhich byte is currently selected and displayedin dbg_rd_data).
dbg_rd_data [63:0] Read Data from Input FIFOs.
dbg_rd_data_cmp [63:0] Comparison of dbg_rd_data anddbg_expected_data.
dbg_expected_data [63:0]Displays the expected data during calibrationstages that use general interconnect-baseddata pattern comparison such as Read per-bitdeskew or read DQS centering (complex).
dbg_cplx_config [15:0]
Complex Calibration Configuration[0] = Start[1] = 1’b0 selects the read pattern. 1’b1 selectsthe write pattern.[3:2] = Rank selection[8:4] = Byte selection[15:9] = Number of loops through datapattern.
The following table shows the DDR4 cal_post_status signal.
Table 95: DDR4 Post-Calibration Status
Debug Signal Bit Description Post-Calibration Step
cal_post_status
0 Running
DQS Gate Tracking1 Idle
2 Fail
3 Running Read Margin Check (Reserved)
4 Running Write Margin Check (Reserved)
5 Handshake Failure (Reserved)
6 Margin Check Failure (Reserved)
7 Reserved
8 Reserved
Determining the Falling Calibration Stage
XSDB can be used to very quickly determine which stage of calibration is failing, which byte/nibble/bit is causing the failure, and how the algorithm is failing.
Configure the device and while the Hardware Manager is open, perform one of the following:
• XSDB Memory IP GUI
• Manually Analyzing the XSDB Output
XSDB Memory IP GUI
Use the available XSDB Memory IP GUI to identify which stages have completed, which, if any,has failed, and review the Memory IP properties window for a message on the failure. Here is asample of the GUI for a passing and failing case:
Appendix B: Debugging
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The value of CAL_POINTER can be used to determine which stages of calibration have passed.The first six bits [5:0] represent the calibration stage and the higher three bits [8:6] represent itsstatus. See the following tables for calibration stage decoding and calibration stage statusdecoding.
Appendix B: Debugging
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Table 97: CAL_POINTER Calibration Stage Status Decoding
XSDB Reg Name XSDB Bit [8:6] Calibration Status Description
CAL_POINTER
0 Calibration is enabled and yet to start this stage.
1
Calibration to skip. It can be due to any of the followingreasons.• Calibration stage is invalid.• Calibration stage is valid, but it can be skipped due
to low frequency of operation.• Calibration stage is valid, but it can be skipped in
functional simulations to cut down simulation times.
2Calibration to load. Calibration stage is valid and valuesneed to be loaded. This is to cut down simulation timein functional simulations to re-run the simulationsquickly.
3 Calibration in progress
4 Calibration skipped
5 Calibration loaded
6 Calibration passed
7 Calibration failed
Appendix B: Debugging
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When the calibration stage causing the failure is known, the failing rank, byte, nibble, and/or bitposition and error status for the failure can be identified using the XSDB registers listed here.
Table 98: Calibration Error Related XSDB Register
XSDB Reg Name DescriptionCAL_ERROR_BIT_*_* Bit position failing
CAL_ERROR_DATA_NIBBLE_*_* Data nibble or byte position failing
CAL_ERROR_PHY_NIBBLE_*_* PHY nibble or byte position failing
CAL_ERROR_RANK Rank failing
CAL_ERROR_CODE Error code specific to the failing stage of calibration.
Debugging DQS Gate Calibration Failures
Calibration Overview
The XPHY is used to capture read data from the DDR4 SDRAM by using the DQS strobe to clockin read data and transfer the data to an internal FIFO using that strobe. The first step in capturingdata is to evaluate where that strobe is so the XPHY can open the gate and allow the DQS toclock the data into the rest of the PHY.
The XPHY uses an internal clock to sample the DQS during a read burst and provides a singlebinary value back called GT_STATUS. This sample is used as part of a training algorithm todetermine where the first rising edge of the DQS is in relation to the sampling clock.
Calibration logic issues individual read commands to the DDR4 SDRAM and asserts theclb2phy_rd_en signal to the XPHY to open the gate which allows the sample of the DQS tooccur. The clb2phy_rd_en signal has control over the timing of the gate opening on a DRAM-clock-cycle resolution. This signal is controlled on a per-byte basis in the PHY and is set in theddr_mc_pi block for use by both calibration and the controller.
Calibration is responsible for determining the value used on a per-byte basis for use by thecontroller. The XPHY provides for additional granularity in the time to open the gate throughcoarse and fine taps. Coarse taps offer 90° DRAM clock-cycle granularity (16 available) and eachfine tap provides a 2 to 3 ps granularity for each tap (512 available). BISC provides the number oftaps for 1/4 of a memory clock cycle by taking (BRAM_BISC_PQTR_NIBBLE* -BRAM_BISC_ALIGN_PQTR_NIBBLE*) or (BRAM_BISC_NQTR_NIBBLE* -BRAM_BISC_ALIGN_NQTR_NIBBLE*). These are used to estimate the per-tap resolution for agiven nibble.
DQS gate calibration algorithm is divided into four parts as shown in flowchart below.
Appendix B: Debugging
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Find Width of the Noise of the Third Edge and Get Center in It
Multi Rank Adjustment
DQS Gate Calibration End
X24719-101420
Detecting the Third Edge of DQS
The search for the DQS begins with an estimate of when the DQS is expected back. The totallatency for the read is a function of the delay through the PHY, PCB delay, and the configuredlatency of the DDR4 SDRAM (CAS latency, Additive latency, etc.). The search starts two DRAMclock cycles before the expected return of the DQS. The algorithm must start sampling beforethe first rising edge of the DQS, preferably in the preamble region. DDR4 preambles for the DQSis shown below.
Figure 50: DDR4 DQS Preamble
Preamble training mode
Pulled High
DQSPreamble
X24715-101420
To detect the third edge, a combination of the read latency and the coarse taps is used to adddelay on the internal sampling clock signal. The delay is added until the third edge is detected forall the bytes. Delay update is masked for the byte group whose third edge of DQS is alreadydetected.
Appendix B: Debugging
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The following figure shows an example of samples of a DQS burst with the expected samplingpattern to be found as the coarse taps are adjusted. The pattern is the expected level seen on theDQS over time as the sampling clock is adjusted in relation to the DQS.
Figure 51: Example DQS Gate Samples Using Coarse Taps
Coarse Resolution
1 Memory Clock Cycle
Preamble Training Mode
Expected Pattern
Coarse Taps
Can be a 0 or 1
Read latency increased by one
3rd Edge
0 0 0 X 1 X 0 X 1 X
0 1 2 3 0 1 2 3 0 1
X24723-101420
Each individual element of the pattern is 32 read bursts from the DRAM and samples from theXPHY. The gate in the XPHY is opened and a new sample is taken to indicate the level seen onthe DQS. If each of the samples matches with the first sample taken, the value is accepted. If allsamples are not the same value that value is marked as X in the pattern. The X in the patternshown is to allow for jitter and DCD between the clocks, and to deal with uncertainty whendealing with clocks with an unknown alignment. Depending on how the clocks line up they canresolve to all 0s, all 1s, or a mix of values, and yet the DQS pattern can still be found properly.
The coarse taps in the XPHY are incremented and the value is recorded at each individual coarsetap location, looking for the full pattern 000X1X0X1. Detection of pattern 000X1X0X1 isequivalent to finding the third edge of the DQS strobe.
If all allowable values of clb2phy_rd_en for a given latency are checked and the expectedpattern is still not found, the search begins again from the start but this time the sampling isoffset by an estimated 45° using fine taps (half a coarse tap). This allows the sampling to occur ata different phase than the initial relationship. Each time through if the pattern is not found, theoffset is reduced by half until all offset values have been exhausted.
The following figure shows an extreme case of DCD on the DQS that would result in the patternnot being found until an offset being applied using fine taps.
Appendix B: Debugging
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Figure 52: DQS Gate Calibration Fine Offset Example
DDR4
Preamble Training
ModeCoarse Taps
Fine Offset
Fails to Find Pattern
Pattern Found
0 0 0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1 0 0
0 1 2 3 0 1 2 3 0 1
0 1 2 3 0 1 2 3 0 1X24718-101420
Stable 0 Confirmation Before Third Edge of DQS
Both the DQS strobe and the sampling clock can have jitter in relation to one another. Forexample, when they are lined up each sample can have a different result compared to theprevious sample. Therefore, the fine search must begin in an area where all samples return a 0 soit is relatively stable, as shown below.
Figure 53: DQS Gate Fine Adjustment, Sample a 0
Sample Clock
DQS
Stable “0” Region
X24720-101420
Confirmation of stable 0 before the third edge of DQS is required before starting the search ofnoise window of third edge of DQS. Confirmation of the stable 0 tells that fine tap increment willstart from left most edge of the noise.
For confirming the stable 0 few fine taps are incremented and if it still sees stable 0 for all thefine taps then it means it is in the stable 0 region before the noise of 0 to 1 transaction. If it doesnot find the stable 0 this way then one coarse tap is decremented for that byte, and stable 0 isconfirmed again. If it does not find stable 0 even after decrementing coarse tap, it indicates error.
Noise Window Detection and Centering
The Fine taps are incremented for the internal sampling clock until a non-zero value is returned(which indicates the left edge of the unstable region) as shown below.
Appendix B: Debugging
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The fine taps are incremented again until all samples taken return a 1, as shown below. This isrecorded as the right edge of the uncertain region.
Figure 55: DQS Gate Fine Adjustment, Uncertain Region
Left of Noise Region
Sample Clock
DQS
Right of Noise Region
Sample Clock
DQS
X24722-101420
The final fine tap is computed as the midpoint of the uncertain region, (right – left)/2 + left. Thisensures optimal placement of the gate in relation to the DQS. For simulation, speeding up afaster search is implemented for the fine tap adjustment. This is performed by using a binarysearch to jump the fine taps by larger values to quickly find the 0 to 1 transition.
After centering the sampling clock into the noise region, read latency is incremented by 2memory clocks to pass all edges of the DQS burst. At the end of this step coarse tap overflowstatus, read latency, coarse tap and fine tap values are updated in respective register of XSDBBRAM as shown in the table.
Now read latency and coarse tap values are adjusted in such a way that coarse tap value falls inthe range of 6 to 9. Updated read latency and coarse tap values are saved asBRAM_DQSGATE_STG2_READ_LAT_RANK*_BYTE* andBRAM_DQSGATE_STG2_RLDLYRNK_CRSE_RANK*_BYTE*.
Table 99: DQS Gate XSDB Reg Update
Status/Settings XSDB RegCoarse tap overflow status BRAM_DQSGATE_STG1_OVERFLOW_*
Status/Settings XSDB RegCoarse tap value BRAM_DQSGATE_STG1_RLDLYRNK_CRSE_RANK*_BYTE*
Fine tap value BRAM_DQSGATE_STG1_RLDLYRNK_CRSE_RANK*_BYTE*
Multi-Rank Adjustment
For multi-rank systems, separate control exists in the XPHY for each rank and every rank can betrained separately for coarse and fine taps. After all ranks have been calibrated, an adjustment isrequired before normal operation to ensure fast rank-to-rank switching.
Across all ranks within a byte, the read latency and general interconnect delay(clb2phy_rd_en) must match. The coarse taps are incremented/decremented accordingly toadjust the timing of the gate signal to match the timing found in calibration. If a commonclb2phy_rd_en setting cannot be found for a given byte across all ranks, an error is asserted.Additionally, the coarse taps have to be within four taps within the same byte lane across allranks. The following table shows the DQS Gate adjustment examples.
Table 100: DQS Gate Adjustment Example
Example SettingCalibration After Multi-Rank Adjustment
Rank 0 Rank 1 Rank 0 Rank 1 Result
1Read latency 14 15 14 14
PassCoarse taps 8 6 8 10
2Read latency 22 21 21 21
PassCoarse taps 6 9 10 9
3Read latency 10 15 N/A N/A
ErrorCoarse taps 9 9 N/A N/A
4Read latency 10 11 10 10
ErrorCoarse taps 6 9 6 13
Debug
To determine the status of DQS Gate Calibration, click the DQS_GATE_CAL stage under theStatus window and view the results within the Memory IP Properties window. The messagedisplayed in the Memory IP Properties identifies how the stage failed, or notes if it passedsuccessfully.
Appendix B: Debugging
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Figure 56: Memory IP XSDB Debug GUI Example – DQS Gate
CAL_ERROR Decode for DQS Preamble Detection Calibration
The status of DQS Gate can also be determined by decoding the CAL_ERROR result according totable below. Execute the Tcl commands noted in the Manually Analyzing the XSDB Outputsection to generate the XSDB output containing the signal results.
Table 101: CAL_ERROR Decode for DQS Preamble Detection Calibration
Error Code Description Recommended Debug Step
6 DQS gating timeout waiting for XPHY gatetraining done.
Check power and pinout on the PCB/Design.This is the error found when the DRAM does notrespond to the Read command. Probe if theread DQS is generated when a read command issent out.
7 DQS gating reached maximum read latencylimit.
Check DQS and CK trace lengths. Ensure themaximum trace length is not violated. For debugpurposes, try a lower frequency where moresearch range is available and check if the stageis successful.
8 DQS gating reached maximum read latencylimit.
Check DQS and CK trace lengths for all theranks. Ensure the maximum trace length is notviolated. For debug purposes, try a lowerfrequency.
Appendix B: Debugging
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XSDB Registers of Interest during DQS Preamble Detection Calibration
The following table shows the XSDB registers and values adjusted or used during the DQSPreamble Detection stage of calibration. The values can be analyzed in both successful andfailing calibrations to determine the resultant values and the consistency in results across resets.These values can be found within the Memory IP core properties in the Hardware Manager or byexecuting the Tcl commands noted in the Manually Analyzing the XSDB Output section.
Table 102: XSDB Registers of Interest during DQS Preamble Detection Calibration
XSDB Reg Usage Signal Description
BRAM_DQSGATE_STG1_OVERFLOW_* One value per rank andDQS group
Coarse tap overflow statusduring XPHY based DQSgate calibration.
BRAM_DQSGATE_STG1_READ_LAT_RANK*_BYTE* One value per rank andDQS group
Read Latency value aftercentering the internalclock to the noise region ofthird edge of DQS strobe.
BRAM_DQSGATE_STG1_RLDLYRNK_CRSE_RANK*_BYTE* One value per rank andDQS group
Coarse tap value aftercentering the internalclock to the noise region ofthird edge of DQS strobe.
BRAM_DQSGATE_STG1_RLDLYRNK_FINE_RANK*_BYTE* One value per rank andDQS group
Fine tap value aftercentering the internalclock to the noise region ofthird edge of DQS strobe.
BRAM_DQSGATE_STG2_READ_LAT_RANK*_BYTE* One value per rank andDQS group
Read Latency value afteradjusting coarse tap valuein range of 6 to 9.
BRAM_DQSGATE_STG2_RLDLYRNK_CRSE_RANK*_BYTE* One value per rank andDQS group
Coarse tap value afteradjusting coarse tap valuein range of 6 to 9.
BRAM_DQSGATE_MAX_READ_LAT Only one valueMaximum Read Latencyacross all rank just beforethe start of multi-rankadjustment.
BRAM_DQSGATE_READ_LAT_FINAL_BYTE* One value per DQS group
Read Latency final valueafter multi-rankadjustment. The ReadLatency field is limited toCAS latency -3 to CASlatency + 7. If the DQS istoggling yet was not foundcheck the latency of theDQS signal coming back inrelation to the chip select.
BRAM_DQSGATE_RLDLYRNK_CRSE_FINAL_RANK*_BYTE* One value per rank andDQS group
Coarse tap final value aftermulti-rank adjustment.
BISC_ALIGN_PQTR_NIBBLE* One per nibbleInitial 0° offset valueprovided by BISC at power-up.
Appendix B: Debugging
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Table 102: XSDB Registers of Interest during DQS Preamble Detection Calibration(cont'd)
XSDB Reg Usage Signal Description
BISC_ALIGN_NQTR_NIBBLE* One per nibbleInitial 0° offset valueprovided by BISC at power-up.
BISC_PQTR_NIBBLE* One per nibble
Initial 90° offset valueprovided by BISC at power-up. Compute 90° value intaps by taking (BISC_PQTR– BISC_ALIGN_PQTR). Toestimate tap resolutiontake (¼ of the memoryclock period)/ (BISC_PQTR– BISC_ALIGN_PQTR).
BISC_NQTR_NIBBLE* One per nibble
Initial 90° offset valueprovided by BISC at power-up. Compute 90° value intaps by taking (BISC_PQTR– BISC_ALIGN_PQTR). Toestimate tap resolutiontake (¼ of the memoryclock period)/ (BISC_PQTR– BISC_ALIGN_PQTR).
This is a sample of the results for the DQS Preamble Detection XSDB debug signals:
BRAM_DQSGATE_STG1_OVERFLOW_00 int true 0BRAM_DQSGATE_STG1_OVERFLOW_01 int true 0BRAM_DQSGATE_STG1_OVERFLOW_02 int true 0BRAM_DQSGATE_STG1_OVERFLOW_03 int true 0BRAM_DQSGATE_STG1_OVERFLOW_04 int true 0BRAM_DQSGATE_STG1_OVERFLOW_05 int true 0BRAM_DQSGATE_STG1_OVERFLOW_06 int true 0BRAM_DQSGATE_STG1_OVERFLOW_07 int true 0BRAM_DQSGATE_STG1_OVERFLOW_08 int true 0BRAM_DQSGATE_STG1_OVERFLOW_09 int true 0BRAM_DQSGATE_STG1_OVERFLOW_10 int true 0BRAM_DQSGATE_STG1_OVERFLOW_11 int true 0BRAM_DQSGATE_STG1_OVERFLOW_12 int true 0BRAM_DQSGATE_STG1_OVERFLOW_13 int true 0BRAM_DQSGATE_STG1_OVERFLOW_14 int true 0BRAM_DQSGATE_STG1_OVERFLOW_15 int true 0BRAM_DQSGATE_STG1_OVERFLOW_16 int true 0BRAM_DQSGATE_STG1_OVERFLOW_17 int true 0BRAM_DQSGATE_STG1_OVERFLOW_18 int true 0BRAM_DQSGATE_STG1_OVERFLOW_19 int true 0BRAM_DQSGATE_STG1_OVERFLOW_20 int true 0BRAM_DQSGATE_STG1_OVERFLOW_21 int true 0BRAM_DQSGATE_STG1_OVERFLOW_22 int true 0BRAM_DQSGATE_STG1_OVERFLOW_23 int true 0BRAM_DQSGATE_STG1_OVERFLOW_24 int true 0BRAM_DQSGATE_STG1_OVERFLOW_25 int true 0BRAM_DQSGATE_STG1_OVERFLOW_26 int true 0BRAM_DQSGATE_STG1_OVERFLOW_27 int true 0BRAM_DQSGATE_STG1_OVERFLOW_28 int true 0BRAM_DQSGATE_STG1_OVERFLOW_29 int true 0BRAM_DQSGATE_STG1_OVERFLOW_30 int true 0BRAM_DQSGATE_STG1_OVERFLOW_31 int true 0
Appendix B: Debugging
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BRAM_DQSGATE_STG1_OVERFLOW_32 int true 0BRAM_DQSGATE_STG1_OVERFLOW_33 int true 0BRAM_DQSGATE_STG1_OVERFLOW_34 int true 0BRAM_DQSGATE_STG1_OVERFLOW_35 int true 0BRAM_DQSGATE_STG1_OVERFLOW_36 int true 0BRAM_DQSGATE_STG1_OVERFLOW_37 int true 0BRAM_DQSGATE_STG1_OVERFLOW_38 int true 0BRAM_DQSGATE_STG1_OVERFLOW_39 int true 0BRAM_DQSGATE_STG1_OVERFLOW_40 int true 0BRAM_DQSGATE_STG1_OVERFLOW_41 int true 0BRAM_DQSGATE_STG1_OVERFLOW_42 int true 0BRAM_DQSGATE_STG1_OVERFLOW_43 int true 0BRAM_DQSGATE_STG1_OVERFLOW_44 int true 0BRAM_DQSGATE_STG1_OVERFLOW_45 int true 0BRAM_DQSGATE_STG1_OVERFLOW_46 int true 0BRAM_DQSGATE_STG1_OVERFLOW_47 int true 0BRAM_DQSGATE_STG1_OVERFLOW_48 int true 0BRAM_DQSGATE_STG1_OVERFLOW_49 int true 0BRAM_DQSGATE_STG1_OVERFLOW_50 int true 0BRAM_DQSGATE_STG1_OVERFLOW_51 int true 0BRAM_DQSGATE_STG1_OVERFLOW_52 int true 0BRAM_DQSGATE_STG1_OVERFLOW_53 int true 0BRAM_DQSGATE_STG1_OVERFLOW_54 int true 0BRAM_DQSGATE_STG1_OVERFLOW_55 int true 0BRAM_DQSGATE_STG1_OVERFLOW_56 int true 0BRAM_DQSGATE_STG1_OVERFLOW_57 int true 0BRAM_DQSGATE_STG1_OVERFLOW_58 int true 0BRAM_DQSGATE_STG1_OVERFLOW_59 int true 0BRAM_DQSGATE_STG1_OVERFLOW_60 int true 0BRAM_DQSGATE_STG1_OVERFLOW_61 int true 0BRAM_DQSGATE_STG1_OVERFLOW_62 int true 0BRAM_DQSGATE_STG1_OVERFLOW_63 int true 0BRAM_DQSGATE_STG1_OVERFLOW_64 int true 0BRAM_DQSGATE_STG1_OVERFLOW_65 int true 0BRAM_DQSGATE_STG1_OVERFLOW_66 int true 0BRAM_DQSGATE_STG1_OVERFLOW_67 int true 0BRAM_DQSGATE_STG1_OVERFLOW_68 int true 0BRAM_DQSGATE_STG1_OVERFLOW_69 int true 0BRAM_DQSGATE_STG1_OVERFLOW_70 int true 0BRAM_DQSGATE_STG1_OVERFLOW_71 int true 0BRAM_DQSGATE_STG1_OVERFLOW_72 int true 0BRAM_DQSGATE_STG1_OVERFLOW_73 int true 0BRAM_DQSGATE_STG1_OVERFLOW_74 int true 0BRAM_DQSGATE_STG1_OVERFLOW_75 int true 0BRAM_DQSGATE_STG1_OVERFLOW_76 int true 0BRAM_DQSGATE_STG1_OVERFLOW_77 int true 0BRAM_DQSGATE_STG1_OVERFLOW_78 int true 0BRAM_DQSGATE_STG1_OVERFLOW_79 int true 0BRAM_DQSGATE_STG1_OVERFLOW_80 int true 0BRAM_DQSGATE_STG1_OVERFLOW_81 int true 0BRAM_DQSGATE_STG1_OVERFLOW_82 int true 0BRAM_DQSGATE_STG1_OVERFLOW_83 int true 0BRAM_DQSGATE_STG1_OVERFLOW_84 int true 0BRAM_DQSGATE_STG1_OVERFLOW_85 int true 0BRAM_DQSGATE_STG1_OVERFLOW_86 int true 0BRAM_DQSGATE_STG1_OVERFLOW_87 int true 0BRAM_DQSGATE_STG1_OVERFLOW_88 int true 0BRAM_DQSGATE_STG1_OVERFLOW_89 int true 0BRAM_DQSGATE_STG1_OVERFLOW_90 int true 0BRAM_DQSGATE_STG1_OVERFLOW_91 int true 0BRAM_DQSGATE_STG1_OVERFLOW_92 int true 0BRAM_DQSGATE_STG1_OVERFLOW_93 int true 0BRAM_DQSGATE_STG1_OVERFLOW_94 int true 0
Appendix B: Debugging
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BRAM_DQSGATE_STG1_OVERFLOW_95 int true 0BRAM_DQSGATE_STG1_READ_LAT_RANK0_BYTE0 int true 24BRAM_DQSGATE_STG1_READ_LAT_RANK0_BYTE1 int true 24BRAM_DQSGATE_STG1_READ_LAT_RANK0_BYTE2 int true 24BRAM_DQSGATE_STG1_READ_LAT_RANK0_BYTE3 int true 24BRAM_DQSGATE_STG1_READ_LAT_RANK0_BYTE4 int true 24BRAM_DQSGATE_STG1_READ_LAT_RANK0_BYTE5 int true 24BRAM_DQSGATE_STG1_READ_LAT_RANK0_BYTE6 int true 27BRAM_DQSGATE_STG1_READ_LAT_RANK0_BYTE7 int true 27BRAM_DQSGATE_STG1_RLDLYRNK_CRSE_RANK0_BYTE0 int true 11BRAM_DQSGATE_STG1_RLDLYRNK_CRSE_RANK0_BYTE1 int true 12BRAM_DQSGATE_STG1_RLDLYRNK_CRSE_RANK0_BYTE2 int true 13BRAM_DQSGATE_STG1_RLDLYRNK_CRSE_RANK0_BYTE3 int true 14BRAM_DQSGATE_STG1_RLDLYRNK_CRSE_RANK0_BYTE4 int true 15BRAM_DQSGATE_STG1_RLDLYRNK_CRSE_RANK0_BYTE5 int true 15BRAM_DQSGATE_STG1_RLDLYRNK_CRSE_RANK0_BYTE6 int true 4BRAM_DQSGATE_STG1_RLDLYRNK_CRSE_RANK0_BYTE7 int true 5BRAM_DQSGATE_STG1_RLDLYRNK_FINE_RANK0_BYTE0 int true 71BRAM_DQSGATE_STG1_RLDLYRNK_FINE_RANK0_BYTE1 int true 68BRAM_DQSGATE_STG1_RLDLYRNK_FINE_RANK0_BYTE2 int true 25BRAM_DQSGATE_STG1_RLDLYRNK_FINE_RANK0_BYTE3 int true 68BRAM_DQSGATE_STG1_RLDLYRNK_FINE_RANK0_BYTE4 int true 0BRAM_DQSGATE_STG1_RLDLYRNK_FINE_RANK0_BYTE5 int true 13BRAM_DQSGATE_STG1_RLDLYRNK_FINE_RANK0_BYTE6 int true 41BRAM_DQSGATE_STG1_RLDLYRNK_FINE_RANK0_BYTE7 int true 20BRAM_DQSGATE_STG2_READ_LAT_RANK0_BYTE0 int true 25BRAM_DQSGATE_STG2_READ_LAT_RANK0_BYTE1 int true 25BRAM_DQSGATE_STG2_READ_LAT_RANK0_BYTE2 int true 25BRAM_DQSGATE_STG2_READ_LAT_RANK0_BYTE3 int true 26BRAM_DQSGATE_STG2_READ_LAT_RANK0_BYTE4 int true 26BRAM_DQSGATE_STG2_READ_LAT_RANK0_BYTE5 int true 26BRAM_DQSGATE_STG2_READ_LAT_RANK0_BYTE6 int true 26BRAM_DQSGATE_STG2_READ_LAT_RANK0_BYTE7 int true 26BRAM_DQSGATE_STG2_RLDLYRNK_CRSE_RANK0_BYTE0 int true 7BRAM_DQSGATE_STG2_RLDLYRNK_CRSE_RANK0_BYTE1 int true 8BRAM_DQSGATE_STG2_RLDLYRNK_CRSE_RANK0_BYTE2 int true 9BRAM_DQSGATE_STG2_RLDLYRNK_CRSE_RANK0_BYTE3 int true 6BRAM_DQSGATE_STG2_RLDLYRNK_CRSE_RANK0_BYTE4 int true 7BRAM_DQSGATE_STG2_RLDLYRNK_CRSE_RANK0_BYTE5 int true 7BRAM_DQSGATE_STG2_RLDLYRNK_CRSE_RANK0_BYTE6 int true 8BRAM_DQSGATE_STG2_RLDLYRNK_CRSE_RANK0_BYTE7 int true 9BRAM_DQSGATE_MAX_READ_LAT int true 26BRAM_DQSGATE_READ_LAT_FINAL_BYTE0 int true 25BRAM_DQSGATE_READ_LAT_FINAL_BYTE1 int true 25BRAM_DQSGATE_READ_LAT_FINAL_BYTE2 int true 25BRAM_DQSGATE_READ_LAT_FINAL_BYTE3 int true 26BRAM_DQSGATE_READ_LAT_FINAL_BYTE4 int true 26BRAM_DQSGATE_READ_LAT_FINAL_BYTE5 int true 26BRAM_DQSGATE_READ_LAT_FINAL_BYTE6 int true 26BRAM_DQSGATE_READ_LAT_FINAL_BYTE7 int true 26BRAM_DQSGATE_RLDLYRNK_CRSE_FINAL_RANK0_BYTE0 int true 7BRAM_DQSGATE_RLDLYRNK_CRSE_FINAL_RANK0_BYTE1 int true 8BRAM_DQSGATE_RLDLYRNK_CRSE_FINAL_RANK0_BYTE2 int true 9BRAM_DQSGATE_RLDLYRNK_CRSE_FINAL_RANK0_BYTE3 int true 6BRAM_DQSGATE_RLDLYRNK_CRSE_FINAL_RANK0_BYTE4 int true 7BRAM_DQSGATE_RLDLYRNK_CRSE_FINAL_RANK0_BYTE5 int true 7BRAM_DQSGATE_RLDLYRNK_CRSE_FINAL_RANK0_BYTE6 int true 8BRAM_DQSGATE_RLDLYRNK_CRSE_FINAL_RANK0_BYTE7 int true 9BRAM_BISC_PQTR_ALIGN_NIBBLE0 int true 1BRAM_BISC_PQTR_ALIGN_NIBBLE1 int true 0BRAM_BISC_PQTR_ALIGN_NIBBLE2 int true 1BRAM_BISC_PQTR_ALIGN_NIBBLE3 int true 0BRAM_BISC_PQTR_ALIGN_NIBBLE4 int true 0
Appendix B: Debugging
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BRAM_BISC_PQTR_ALIGN_NIBBLE5 int true 2BRAM_BISC_PQTR_ALIGN_NIBBLE6 int true 0BRAM_BISC_PQTR_ALIGN_NIBBLE7 int true 0BRAM_BISC_PQTR_ALIGN_NIBBLE8 int true 1BRAM_BISC_PQTR_ALIGN_NIBBLE9 int true 1BRAM_BISC_PQTR_ALIGN_NIBBLE10 int true 0BRAM_BISC_PQTR_ALIGN_NIBBLE11 int true 33BRAM_BISC_PQTR_ALIGN_NIBBLE12 int true 0BRAM_BISC_PQTR_ALIGN_NIBBLE13 int true 1BRAM_BISC_PQTR_ALIGN_NIBBLE14 int true 1BRAM_BISC_PQTR_ALIGN_NIBBLE15 int true 2BRAM_BISC_NQTR_ALIGN_NIBBLE0 int true 0BRAM_BISC_NQTR_ALIGN_NIBBLE1 int true 1BRAM_BISC_NQTR_ALIGN_NIBBLE2 int true 0BRAM_BISC_NQTR_ALIGN_NIBBLE3 int true 1BRAM_BISC_NQTR_ALIGN_NIBBLE4 int true 0BRAM_BISC_NQTR_ALIGN_NIBBLE5 int true 0BRAM_BISC_NQTR_ALIGN_NIBBLE6 int true 2BRAM_BISC_NQTR_ALIGN_NIBBLE7 int true 0BRAM_BISC_NQTR_ALIGN_NIBBLE8 int true 0BRAM_BISC_NQTR_ALIGN_NIBBLE9 int true 0BRAM_BISC_NQTR_ALIGN_NIBBLE10 int true 1BRAM_BISC_NQTR_ALIGN_NIBBLE11 int true 0BRAM_BISC_NQTR_ALIGN_NIBBLE12 int true 1BRAM_BISC_NQTR_ALIGN_NIBBLE13 int true 0BRAM_BISC_NQTR_ALIGN_NIBBLE14 int true 0BRAM_BISC_NQTR_ALIGN_NIBBLE15 int true 0BRAM_BISC_PQTR_NIBBLE0 int true 89BRAM_BISC_PQTR_NIBBLE1 int true 88BRAM_BISC_PQTR_NIBBLE2 int true 89BRAM_BISC_PQTR_NIBBLE3 int true 87BRAM_BISC_PQTR_NIBBLE4 int true 88BRAM_BISC_PQTR_NIBBLE5 int true 88BRAM_BISC_PQTR_NIBBLE6 int true 89BRAM_BISC_PQTR_NIBBLE7 int true 88BRAM_BISC_PQTR_NIBBLE8 int true 88BRAM_BISC_PQTR_NIBBLE9 int true 91BRAM_BISC_PQTR_NIBBLE10 int true 90BRAM_BISC_PQTR_NIBBLE11 int true 92BRAM_BISC_PQTR_NIBBLE12 int true 89BRAM_BISC_PQTR_NIBBLE13 int true 90BRAM_BISC_PQTR_NIBBLE14 int true 90BRAM_BISC_PQTR_NIBBLE15 int true 90BRAM_BISC_NQTR_NIBBLE0 int true 87BRAM_BISC_NQTR_NIBBLE1 int true 90BRAM_BISC_NQTR_NIBBLE2 int true 90BRAM_BISC_NQTR_NIBBLE3 int true 89BRAM_BISC_NQTR_NIBBLE4 int true 87BRAM_BISC_NQTR_NIBBLE5 int true 89BRAM_BISC_NQTR_NIBBLE6 int true 91BRAM_BISC_NQTR_NIBBLE7 int true 91BRAM_BISC_NQTR_NIBBLE8 int true 87BRAM_BISC_NQTR_NIBBLE9 int true 91BRAM_BISC_NQTR_NIBBLE10 int true 90BRAM_BISC_NQTR_NIBBLE11 int true 91BRAM_BISC_NQTR_NIBBLE12 int true 90BRAM_BISC_NQTR_NIBBLE13 int true 90BRAM_BISC_NQTR_NIBBLE14 int true 88BRAM_BISC_NQTR_NIBBLE15 int true 89
Appendix B: Debugging
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The following table provides expected results for coarse and read latency parameters during DQSPreamble Detection. These values can be compared to the results found in hardware testing.
Table 103: Expected Results for DQS Preamble Detection Coarse Tap and RL
XSDB Reg DescriptionBRAM_DQSGATE_STG2_RLDLYRNK_CRSE_RANK*_BYTE* Coarse tap values adjusted in range of 6 to 9
BRAM_DQSGATE_READ_LAT_FINAL_BYTE*Read Latency value last used during DQS PreambleDetection. Expected value is dependent on the PCB tracelength but should be in the range CL-2 to CL+4.
BRAM_DQSGATE_RLDLYRNK_CRSE_FINAL_RANK*_BYTE* Final coarse tap value. Expected values 6-13 only.
Hardware Measurements
This is the first stage of calibration. Therefore, any general setup issue can result in a failureduring DQS Preamble Detection Calibration. The first items to verify are proper clocking andreset setup as well as usage of unmodified Memory IP RTL that is generated specifically for theSDRAM(s) in hardware. The General Checks section (see related information) should be verifiedwhen a failure occurs during DQS Preamble Detection.
After the General Checks have been verified, hardware measurements on DQS, and specificallythe DQS byte that fails during DQS Preamble Detection, should be captured and analyzed. DQSmust be toggling during DQS Preamble Detection. While probing DQS, validate the following:
1. Continuous DQS pulses exist with gaps between each BL8 read.
2. The signal integrity of DQS:
• Ensure VIL and VIH are met for the specific I/O Standard in use. For more information, seethe Versal Prime Series Data Sheet: DC and AC Switching Characteristics (DS956) and theVersal AI Core Series Data Sheet: DC and AC Switching Characteristics (DS957).
• Look for 50% duty cycle periods.
• Ensure that the signals have low jitter/noise that can result from any power supply orboard noise.
If DQS pulses are not present and the General Checks have been verified, probe the readcommands at the SDRAM and verify:
2. The signal integrity of each command signal is valid.
• Ensure VIL and VIH are met. For more information, see the JESD79-4, DDR4 SDRAMStandard, JEDEC® Solid State Technology Association.
3. CK to command timing.
4. RESET# voltage level.
5. Memory initialization routine.
Related Information
General Checks
Debugging Write Leveling Calibration Failures
Calibration Overview
The DDR4 SDRAM memory modules use a fly-by topology on clocks, address, commands, andcontrol signals to improve signal integrity. This topology causes a skew between DQS and CK ateach memory device on the module. Write leveling is a feature in DDR4 SDRAMs that allows thecontroller to adjust each write DQS phase independently with respect to the clock (CK)forwarded to the DDR4 device to compensate for this skew and meet the tDQSS specification.
During write leveling, DQS is driven by the FPGA memory interface and DQ is driven by theDDR4 SDRAM device to provide feedback. To start write leveling, an MRS command is sent tothe DRAM to enable the feedback feature, while another MRS command is sent to disable writeleveling at the end. The figures shows the block diagram for the write leveling implementation.
Appendix B: Debugging
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The XPHY is set up for write leveling by setting various attributes in the RIU. WL_TRAIN is set todecouple the DQS and DQ when driving out the DQS. This allows the XPHY to capture thereturning DQ from the DRAM. Because the DQ is returned without the returning DQS strobe forcapture, the RX_GATE is set to 0 in the XPHY to disable DQS gate operation.
DQS is delayed with ODELAY and coarse delay (WL_DLY_CRSE [12:9] applies to all bits in anibble) provided in the RIU WL_DLY_RNKx register. The WL_DLY_FINE [8:0] location in the RIUis used to store the ODELAY value for write leveling for a given nibble (used by the XPHY whenswitching ranks).
A DQS train of pulses is output by the FPGA to the DRAM to detect the relationship of CK andDQS at the DDR4 memory device. DQS is delayed using the coarse taps in unit tap incrementsuntil a 0 to 1 transition is detected on the feedback DQ input. Pattern 0X1 is searched after eachcoarse tap increment for detecting the rising edge of CK.
If the algorithm never sees the pattern 0X1 using the coarse taps, the ODELAY of the DQS is setto an offset value (first set at 45°, BRAM_WRLVL_OFFSET_RANK*_BYTE*) and the coarse tapsare checked again from 0 (the algorithm might need to perform this if the noise region is close to90° or there is a large amount of DCD). If the transition is still not found, the offset is halved, andthe algorithm tries again. If even after using all the ODELAY and coarse tap it does not see thepattern 0X1 then write leveling calibration error is issued.
The number of ODELAY taps used is determined by the initial alignment of the DQS and CK andthe size of this noise region as shown in the figure.
Appendix B: Debugging
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Figure 59: Worst Case ODELAY Taps (Maximum and Minimum)
DQS/DQS#
CK/CK#
Coarse Tap
1*Coarse
2*Coarse
3*Coarse
Required ODELAY(max)
DQS/DQS#
CK/CK#
Coarse Tap
Required ODELAY (min)
X24738-101420
After finding the rising edge of the CK, coarse tap is reverted back to the last stable 0 seen justbefore the rising edge and coarse tap value is saved asBRAM_WRLVL_CRSE_STG1_RANK*_BYTE*.
Stable 0 Confirmation Before Rising Edge of CK
Confirmation of stable 0 before the rising edge of CK is required before starting the noisewindow detection phase. Confirmation of the stable 0 tells that fine tap increment will start fromleft most edge of the noise.
For confirming the stable 0 few fine taps are incremented and if it still sees stable 0 for all thefine taps then it means it is in the stable 0 region before the noise of 0 to 1 transaction. If it doesnot find the stable 0 this way then one coarse tap is decremented, and stable 0 is confirmedagain. If it does not find stable 0 even after decrementing coarse tap, it indicates error.
Noise Window Detection and Centering
The fine taps are incremented until a non-zero value is returned. This is recorded as the left edgeof the unstable region (BRAM_WRLVL_FINE_LEFT_RANK*_BYTE*). The fine taps areincremented again until all samples taken return a 1. This is recorded as the right edge of theuncertain region (BRAM_WRLVL_FINE_RIGHT_RANK*_BYTE*). Various write leveling regions areshown in the figure.
Appendix B: Debugging
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After finding both the edges of the noise region, DQS is centered in the noise region. The finalfine tap is computed as the midpoint of the uncertain region, odelay – MIN_VALID_CNT –((right_edge_taps – left_edge_taps) / 2).
After the final ODELAY setting is found, the value of ODELAY is loaded in the RIU in theWL_DLY_RNKx[8:0] register and BRAM_WRLVL_FINE_FINAL_RANK*_BYTE*. This value is alsoloaded in the ODELAY register for the DQ and the DM to match the DQS.
After write leveling, the MPR command is sent to the DRAM to disable the write leveling feature,the WL_TRAIN is set back to the default OFF setting, and the DQS gate is turned back on toallow for capture of the DQ with the returning strobe DQS.
Debug
To determine the status of Write Leveling Calibration, click the WRITE_LEVELING_CAL stageunder the Status window and view the results within the Memory IP Properties window. Themessage displayed in the Memory IP Properties identifies how the stage failed, or notes if itpassed successfully.
Appendix B: Debugging
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Figure 61: Memory IP XSDB Debug GUI Example – Write Leveling
CAL_ERROR Decode for Write Leveling Calibration
The status of Write Leveling can also be determined by decoding the CAL_ERROR resultaccording to the table below. Execute the Tcl commands noted in the Manually Analyzing theXSDB Output section to generate the XSDB output containing the signal results.
Table 104: CAL_ERROR Decode for Write Leveling Calibration
Error Code Description Recommended Debug Step
9 Write leveling failed to find rising edge usingcoarse and fine offset.
For failures on the second rank of a multi-rankDIMM, check if the DIMM uses mirroring andmake sure the design generated matches whatthe DIMM expects. Check the pinout andconnections of the address/control bus,specifically A7 which is used to set the writeleveling mode in the DRAM.
10 Write leveling failed in stable 0 confirmationstage.
Check the BISC values in XSDB (for the nibblesassociated with the DQS) to determine the 90°offset value in taps.
11 Write leveling reached maximum taps to findnoise width by incrementing DQS ODELAY.
Check the BISC values in XSDB (for the nibblesassociated with the DQS) to determine the 90°offset value in taps.
Appendix B: Debugging
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XSDB Registers of Interest Write Leveling Calibration
The following table shows the XSDB registers and values adjusted or used during the WriteLeveling stage of calibration. The values can be analyzed in both successful and failingcalibrations to determine the resultant values and the consistency in results across resets. Thesevalues can be found within the Memory IP core properties in the Hardware Manager or byexecuting the Tcl commands noted in the Manually Analyzing the XSDB Output section.
Table 105: XSDB Registers of Interest Write Leveling Calibration
XSDB Reg Usage Signal Description
BRAM_WRLVL_CRSE_STG1 _RANK*_BYTE* One value per rank perbyte
WRLVL course tap setting to the laststable 0 seen just before the risingedge of CK.
BRAM_WRLVL_OFFSET_RANK*_BYTE* One value per rank perbyte
ODELAY Offset used during rising edgedetection of CK.
BRAM_WRLVL_CRSE_FINAL_RANK*_BYTE* One value per rank perbyte
WRLVL course tap setting afterconfirming stable 0 just before therising edge of CK.
BRAM_WRLVL_NOISE_FCRSE_RANK*_BYTE* One value per rank perbyte
WL_DLY_FINE tap value when left edgeof noise is detected using step size of10 taps.
BRAM_WRLVL_FINE_LEFT_RANK*_BYTE* One value per rank perbyte
WL_DLY_FINE tap value when left edgeof noise is detected.
BRAM_WRLVL_FINE_RIGHT_RANK*_BYTE* One value per rank perbyte
WL_DLY_FINE tap value when rightedge of noise is detected.
BRAM_WRLVL_FINE_FINAL_RANK*_BYTE* One value per rank perbyte
Final WL_DLY_FINE tap value. This isadjusted during alignment of DQS toCK.
BISC_ALIGN_PQTR_NIBBLE* One per nibble Initial 0° offset value provided by BISCat power-up.
BISC_ALIGN_NQTR_NIBBLE* One per nibble Initial 0° offset value provided by BISCat power-up.
BISC_PQTR_NIBBLE* One per nibble
Initial 90° offset value provided by BISCat power-up. Compute 90° value in tapsby taking (BISC_PQTR –BISC_ALIGN_PQTR). To estimate tapresolution take (¼ of the memory clockperiod)/ (BISC_PQTR –BISC_ALIGN_PQTR).
BISC_NQTR_NIBBLE* One per nibble
Initial 90° offset value provided by BISCat power-up. Compute 90° value in tapsby taking (BISC_PQTR –BISC_ALIGN_PQTR). To estimate tapresolution take (¼ of the memory clockperiod)/ (BISC_PQTR –BISC_ALIGN_PQTR).
Appendix B: Debugging
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This is a sample of the results for the Write Leveling XSDB debug signals:
BRAM_WRLVL_CRSE_STG1_RANK0_BYTE0 int true 3BRAM_WRLVL_CRSE_STG1_RANK0_BYTE1 int true 3BRAM_WRLVL_CRSE_STG1_RANK0_BYTE2 int true 0BRAM_WRLVL_CRSE_STG1_RANK0_BYTE3 int true 3BRAM_WRLVL_CRSE_STG1_RANK0_BYTE4 int true 0BRAM_WRLVL_CRSE_STG1_RANK0_BYTE5 int true 1BRAM_WRLVL_CRSE_STG1_RANK0_BYTE6 int true 1BRAM_WRLVL_CRSE_STG1_RANK0_BYTE7 int true 1BRAM_WRLVL_OFFSET_RANK0_BYTE0 int true 0BRAM_WRLVL_OFFSET_RANK0_BYTE1 int true 0BRAM_WRLVL_OFFSET_RANK0_BYTE2 int true 0BRAM_WRLVL_OFFSET_RANK0_BYTE3 int true 0BRAM_WRLVL_OFFSET_RANK0_BYTE4 int true 0BRAM_WRLVL_OFFSET_RANK0_BYTE5 int true 0BRAM_WRLVL_OFFSET_RANK0_BYTE6 int true 0BRAM_WRLVL_OFFSET_RANK0_BYTE7 int true 0BRAM_WRLVL_CRSE_FINAL_RANK0_BYTE0 int true 3BRAM_WRLVL_CRSE_FINAL_RANK0_BYTE1 int true 3BRAM_WRLVL_CRSE_FINAL_RANK0_BYTE2 int true 3BRAM_WRLVL_CRSE_FINAL_RANK0_BYTE3 int true 2BRAM_WRLVL_CRSE_FINAL_RANK0_BYTE4 int true 0BRAM_WRLVL_CRSE_FINAL_RANK0_BYTE5 int true 1BRAM_WRLVL_CRSE_FINAL_RANK0_BYTE6 int true 1BRAM_WRLVL_CRSE_FINAL_RANK0_BYTE7 int true 1BRAM_WRLVL_NOISE_FCRSE_RANK0_BYTE0 int true 0BRAM_WRLVL_NOISE_FCRSE_RANK0_BYTE1 int true 0BRAM_WRLVL_NOISE_FCRSE_RANK0_BYTE2 int true 0BRAM_WRLVL_NOISE_FCRSE_RANK0_BYTE3 int true 0BRAM_WRLVL_NOISE_FCRSE_RANK0_BYTE4 int true 0BRAM_WRLVL_NOISE_FCRSE_RANK0_BYTE5 int true 0BRAM_WRLVL_NOISE_FCRSE_RANK0_BYTE6 int true 0BRAM_WRLVL_NOISE_FCRSE_RANK0_BYTE7 int true 0BRAM_WRLVL_FINE_LEFT_RANK0_BYTE0 int true 7BRAM_WRLVL_FINE_LEFT_RANK0_BYTE1 int true 9BRAM_WRLVL_FINE_LEFT_RANK0_BYTE2 int true 0BRAM_WRLVL_FINE_LEFT_RANK0_BYTE3 int true 4BRAM_WRLVL_FINE_LEFT_RANK0_BYTE4 int true 4BRAM_WRLVL_FINE_LEFT_RANK0_BYTE5 int true 4BRAM_WRLVL_FINE_LEFT_RANK0_BYTE6 int true 1BRAM_WRLVL_FINE_LEFT_RANK0_BYTE7 int true 5BRAM_WRLVL_FINE_RIGHT_RANK0_BYTE0 int true 22BRAM_WRLVL_FINE_RIGHT_RANK0_BYTE1 int true 24BRAM_WRLVL_FINE_RIGHT_RANK0_BYTE2 int true 17BRAM_WRLVL_FINE_RIGHT_RANK0_BYTE3 int true 9BRAM_WRLVL_FINE_RIGHT_RANK0_BYTE4 int true 21BRAM_WRLVL_FINE_RIGHT_RANK0_BYTE5 int true 19BRAM_WRLVL_FINE_RIGHT_RANK0_BYTE6 int true 17BRAM_WRLVL_FINE_RIGHT_RANK0_BYTE7 int true 21BRAM_WRLVL_FINE_FINAL_RANK0_BYTE0 int true 31BRAM_WRLVL_FINE_FINAL_RANK0_BYTE1 int true 63BRAM_WRLVL_FINE_FINAL_RANK0_BYTE2 int true 105BRAM_WRLVL_FINE_FINAL_RANK0_BYTE3 int true 93BRAM_WRLVL_FINE_FINAL_RANK0_BYTE4 int true 59BRAM_WRLVL_FINE_FINAL_RANK0_BYTE5 int true 28BRAM_WRLVL_FINE_FINAL_RANK0_BYTE6 int true 55BRAM_WRLVL_FINE_FINAL_RANK0_BYTE7 int true 99BRAM_BISC_PQTR_ALIGN_NIBBLE0 int true 1BRAM_BISC_PQTR_ALIGN_NIBBLE1 int true 0BRAM_BISC_PQTR_ALIGN_NIBBLE2 int true 1BRAM_BISC_PQTR_ALIGN_NIBBLE3 int true 0BRAM_BISC_PQTR_ALIGN_NIBBLE4 int true 0
Appendix B: Debugging
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BRAM_BISC_PQTR_ALIGN_NIBBLE5 int true 2BRAM_BISC_PQTR_ALIGN_NIBBLE6 int true 0BRAM_BISC_PQTR_ALIGN_NIBBLE7 int true 0BRAM_BISC_PQTR_ALIGN_NIBBLE8 int true 1BRAM_BISC_PQTR_ALIGN_NIBBLE9 int true 1BRAM_BISC_PQTR_ALIGN_NIBBLE10 int true 0BRAM_BISC_PQTR_ALIGN_NIBBLE11 int true 33BRAM_BISC_PQTR_ALIGN_NIBBLE12 int true 0BRAM_BISC_PQTR_ALIGN_NIBBLE13 int true 1BRAM_BISC_PQTR_ALIGN_NIBBLE14 int true 1BRAM_BISC_PQTR_ALIGN_NIBBLE15 int true 2BRAM_BISC_NQTR_ALIGN_NIBBLE0 int true 0BRAM_BISC_NQTR_ALIGN_NIBBLE1 int true 1BRAM_BISC_NQTR_ALIGN_NIBBLE2 int true 0BRAM_BISC_NQTR_ALIGN_NIBBLE3 int true 1BRAM_BISC_NQTR_ALIGN_NIBBLE4 int true 0BRAM_BISC_NQTR_ALIGN_NIBBLE5 int true 0BRAM_BISC_NQTR_ALIGN_NIBBLE6 int true 2BRAM_BISC_NQTR_ALIGN_NIBBLE7 int true 0BRAM_BISC_NQTR_ALIGN_NIBBLE8 int true 0BRAM_BISC_NQTR_ALIGN_NIBBLE9 int true 0BRAM_BISC_NQTR_ALIGN_NIBBLE10 int true 1BRAM_BISC_NQTR_ALIGN_NIBBLE11 int true 0BRAM_BISC_NQTR_ALIGN_NIBBLE12 int true 1BRAM_BISC_NQTR_ALIGN_NIBBLE13 int true 0BRAM_BISC_NQTR_ALIGN_NIBBLE14 int true 0BRAM_BISC_NQTR_ALIGN_NIBBLE15 int true 0BRAM_BISC_PQTR_NIBBLE0 int true 89BRAM_BISC_PQTR_NIBBLE1 int true 88BRAM_BISC_PQTR_NIBBLE2 int true 89BRAM_BISC_PQTR_NIBBLE3 int true 87BRAM_BISC_PQTR_NIBBLE4 int true 88BRAM_BISC_PQTR_NIBBLE5 int true 88BRAM_BISC_PQTR_NIBBLE6 int true 89BRAM_BISC_PQTR_NIBBLE7 int true 88BRAM_BISC_PQTR_NIBBLE8 int true 88BRAM_BISC_PQTR_NIBBLE9 int true 91BRAM_BISC_PQTR_NIBBLE10 int true 90BRAM_BISC_PQTR_NIBBLE11 int true 92BRAM_BISC_PQTR_NIBBLE12 int true 89BRAM_BISC_PQTR_NIBBLE13 int true 90BRAM_BISC_PQTR_NIBBLE14 int true 90BRAM_BISC_PQTR_NIBBLE15 int true 90BRAM_BISC_NQTR_NIBBLE0 int true 87BRAM_BISC_NQTR_NIBBLE1 int true 90BRAM_BISC_NQTR_NIBBLE2 int true 90BRAM_BISC_NQTR_NIBBLE3 int true 89BRAM_BISC_NQTR_NIBBLE4 int true 87BRAM_BISC_NQTR_NIBBLE5 int true 89BRAM_BISC_NQTR_NIBBLE6 int true 91BRAM_BISC_NQTR_NIBBLE7 int true 91BRAM_BISC_NQTR_NIBBLE8 int true 87BRAM_BISC_NQTR_NIBBLE9 int true 91BRAM_BISC_NQTR_NIBBLE10 int true 90BRAM_BISC_NQTR_NIBBLE11 int true 91BRAM_BISC_NQTR_NIBBLE12 int true 90BRAM_BISC_NQTR_NIBBLE13 int true 90BRAM_BISC_NQTR_NIBBLE14 int true 88BRAM_BISC_NQTR_NIBBLE15 int true 89
Appendix B: Debugging
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The tap variance across DQS byte groups vary greatly due to the difference in trace lengths withfly-by-routing. The table provides expected results for the coarse and fine parameters duringWrite Leveling.
Table 106: Expected Write Leveling Results
XSDB Reg Description
BRAM_WRLVL_CRSE_FINAL_RANK*_BYTE* WRLVL Coarse tap setting after calibration. Expected values0 to 4.
BRAM_WRLVL_FINE_RIGHT_RANK*_BYTE*WRLVL ODELAY tap setting to find Stable 1. Expected values0 to 90° setting of ODELAY taps (depending on the tapresolution).
Hardware Measurements
The following measurements can be made by triggering on the status bit that indicates the startof WRLVL (dbg_cal_seq[1] = 1’b1).
1. Verify DQS and CK are toggling on the board. The FPGA sends DQS and CK during WriteLeveling. If they are not toggling, something is wrong with the setup and the General Checkssection should be thoroughly reviewed.
2. Verify fly-by-routing is implemented correctly on the board.
3. Verify CK to DQS trace matching. The required matching is documented with the Versal ACAPPCB Design User Guide (UG863). Failure to adhere to this spec can result in Write Levelingfailures.
4. Trigger on the start of Write Leveling by bringing dbg_cal_seq[1] to an I/O and using therising edge (1’b1) as the scope trigger. Monitor the following:
• MRS command at the memory to enable Write Leveling Mode. The Mode registers mustbe properly set up to enable Write Leveling. Specifically, address bit A7 must be correct. Ifthe part chosen in the Memory IP is not accurate or there is an issue with the connectionof the address bits on the board, this could be an issue. If the Mode registers are not setup to enable Write Leveling, the 0-to-1 transition is not seen.
Note: For dual-rank design when address mirroring is used, address bit A7 is not the same betweenthe two ranks.
• Verify the ODT pin is connected and being asserted properly during the DQS toggling.
• Check the signal levels of all the DQ bits being returned. Any stuck-at-bits (Low/High) orfloating bits that are not being driven to a given rail can cause issues.
Appendix B: Debugging
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• Verify the DQS to CK relationship changes as the algorithm makes adjustments to theDQS. Check the DQ value being returned as this relationship changes.
• For DDR4 check the VREF settings are correct in the design.
5. Using the Vivado Hardware Manager and while running the Memory IP Example Design withDebug Signals enabled, set the trigger to dbg_cal_seq = 0R0 (R signifies rising edge). Thefollowing simulation example shows how the debug signals should behave during successfulWrite Leveling.
Figure 62: RTL Debug Signals during Write Leveling
Related Information
General Checks
Read Leveling Calibration Overview
After the gate has been trained and Write Leveling has completed, the next step is to ensurereliable capture of the read data with the DQS. This stage of Read Leveling is divided into twophases, Per-Bit DQ Deskew and Read DQS Centering. Read Leveling uses the DDR4 MultiPurpose Register (MPR). The MPR contains a pattern that can be used to train the read DQS andDQ for read capture.
To perform per-bit deskew, a repeating pattern available through DDR4 MPR is read back toback. When per-bit deskew is complete, the same simple repeating pattern available throughDDR4 MPR is used to center the DQS in the DQ read eye.
Appendix B: Debugging
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The DQS strobe passes through gate logic before the start of DQ data sampling. The gate logicdrives PDQS and NDQS out of the input DQS strobe on per-nibble basis (four DQ bits perPDQS/NDQS). The XPHY provides separate delay elements PQTR/NQTR (2 to 3 ps per tap, 512total) for the PDQS /NDQS to clock the rising and falling edge DQ data (PDQS for rising edge,NDQS for falling edge). This allows the algorithm to center the rising and falling edge DQS strobeindependently to ensure more margin when dealing with DCD. The data captured in the PDQSclock domain is transferred to the NDQS clock domain before being sent to the read FIFO and tothe general interconnect clock domain.
Due to this transfer of clock domains, the PDQS and NDQS clocks must be roughly 180° out ofphase. This relationship between the PDQS/NDQS clock paths is set up as part of the BISC start-up routine, and thus calibration needs to maintain this relationship as part of the training(BRAM_BISC_ALIGN_PQTR, BRAM_BISC_ALIGN_NQTR, BRAM_BISC_PQTR,BRAM_BISC_NQTR).
Debugging Read Per-Bit DQ Deskew Failures
Calibration Overview
Because Write Centering calibration has not yet been performed, write operation cannot becarried out properly. Data pattern 10101010 stored in mode register (MPR0) of DRAM is readback to back for performing per bit deskew. The figure shows the pattern read from MPR0 ofDRAM.
Figure 63: Repeating Pattern Read from MPR0
DQS/DQS#
0 1 0 1 0 1 0 1
DQ/DQ#
X24737-101420
At the start of deskew, PDQS and NDQS of all the nibbles are delayed together until the PDQSof each nibble finds valid stable region for each bit of its nibble once. Only the rising edge data ischecked for correctness. The falling edge comparison is thrown away to allow for extra delay onthe PDQS/NDQS relative to the DQ. The final delay tap applied for delaying PDQS and NDQStogether is stored as BRAM_RDDQ_QTR_DESKEW_NIBBLE*.
The figure shows the initial alignment of PDQS/NDQS with DQ bits of the nibble.
Appendix B: Debugging
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Figure 64: Per-Bit Deskew – Initial Relationship Example
D0
PDQS
NDQS
10 0
D1 10 0
X24735-101420
The figure shows the alignment of PDQS/NDQS with DQ bits of the nibble after detecting validstable region for all DQ bits in the nibble once.
Figure 65: Per-Bit Deskew – Detecting Valid Stable Region
D0
PDQS
NDQS
10 0
D1 10 0
Delay PDQS/NDQS
X24733-101420
After detecting valid stable region for all DQ bits in the nibble once. All DQ bits in the nibble aredelayed in parallel until valid stable region to noise region crossing is detected on their PDQSsampling. The final DQ IDELAY value from deskew is stored atBRAM_RDDQ_IDELAY_FINAL_BIT*. The figure shows the alignment of PDQS/NDQS with DQbits in the nibble after detecting transition from valid stable region to noise region.
Appendix B: Debugging
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Figure 66: Per-Bit Deskew – Detecting Valid Stable Region to Noise Region Crossing
D0
PDQS
NDQS
10 0
D1 10 0
X24734-101420
Debug
To determine the status of Read Per-Bit DQ Deskew Calibration, click the READ_DQ_CAL stageunder the Status window and view the results within the Memory IP Properties window. Themessage displayed in the Memory IP Properties identifies how the stage failed, or notes if itpassed successfully. Check CAL_ERROR for confirming whether the calibration failure is in ReadPer-Bit DQ Deskew or Read DQ Centering stage.
Appendix B: Debugging
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Figure 67: Memory IP XSDB Debug GUI Example – Read Leveling (Read Per-Bit DQDeskew)
CAL_ERROR Decode for Read Per-Bit DQ Deskew Calibration
The status of Read Per-Bit DQ Deskew can also be determined by decoding the CAL_ERRORresult according to the table below. Execute the Tcl commands noted in the Manually Analyzingthe XSDB Output section to generate the XSDB output containing the signal results.
Table 107: CAL_ERROR Decode for Read Per-Bit DQ Deskew Calibration
Error Code Description Recommended Debug Step
12No valid data found for a given bit in the nibbleby incrementing PQTR/NQTR IDELAY togetherusing step size of 1 tap.
Check the dbg_rd_data, dbg_rd_data_cmp, anddbg_expected_data signals in the ILA. Check thepinout and look for any STUCK-AT-BITs, checkvrp resistor, VREF resistor. CheckBRAM_BISC_PQTR, BRAM_BISC_NQTR forstarting offset between rising/falling clocks.
13No valid data found for a given bit in the nibbleby incrementing DQ IDELAY using step size of 1tap.
Check the dbg_rd_data, dbg_rd_data_cmp, anddbg_expected_data signals in the ILA. Check thepinout and look for any STUCK-AT-BITs, checkvrp resistor, VREF resistor. CheckBRAM_BISC_PQTR, BRAM_BISC_NQTR forstarting offset between rising/falling clocks.
Appendix B: Debugging
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14Noise region not found for a given bit in thenibble by incrementing DQ IDELAY using stepsize of 10 taps.
Check for a mapping issue. This usually implies adelay is not moving when it should. Check theconnections going to the XPHY and ensure thecorrect RIU is selected based on the byte beingadjusted.
15Noise region not found for a given bit in thenibble by incrementing DQ IDELAY using stepsize of 1 tap.
Check for a mapping issue. This usually implies adelay is not moving when it should. Check theconnections going to the XPHY and ensure thecorrect RIU is selected based on the byte beingadjusted.
Related Information
Manually Analyzing the XSDB Output
XSDB Registers of Interest during Read Per-Bit DQ Deskew Calibration
The following table shows the XSDB registers and values adjusted or used during the Read Per-Bit DQ Deskew stage of calibration. The values can be analyzed in both successful and failingcalibrations to determine the resultant values and the consistency in results across resets. Thesevalues can be found within the Memory IP core properties in the Hardware Manager or byexecuting the Tcl commands noted in the Manually Analyzing the XSDB Output section.
Table 108: XSDB Registers of Interest during Read Per-Bit DQ Deskew Calibration
XSDB Reg Usage Signal Description
BRAM_RDDQ_QTR_DESKEW_NIBBLE* One per nibble
Read leveling QTR IDELAY (PDQS andNDQS delayed together) delay valuewhen valid stable region is detected forall DQ bits in a nibble during per bitread DQ deskew.
BRAM_RDDQ_IDELAY_FINAL_BIT* One per bit Read leveling IDELAY delay value foundduring per bit read DQ deskew.
This is a sample of the results for the Read Per-Bit DQ Deskew XSDB debug signals:
BRAM_RDDQ_QTR_DESKEW_NIBBLE0 int true 16BRAM_RDDQ_QTR_DESKEW_NIBBLE1 int true 16BRAM_RDDQ_QTR_DESKEW_NIBBLE2 int true 16BRAM_RDDQ_QTR_DESKEW_NIBBLE3 int true 16BRAM_RDDQ_QTR_DESKEW_NIBBLE4 int true 16BRAM_RDDQ_QTR_DESKEW_NIBBLE5 int true 16BRAM_RDDQ_QTR_DESKEW_NIBBLE6 int true 16BRAM_RDDQ_QTR_DESKEW_NIBBLE7 int true 16BRAM_RDDQ_QTR_DESKEW_NIBBLE8 int true 0BRAM_RDDQ_QTR_DESKEW_NIBBLE9 int true 0BRAM_RDDQ_QTR_DESKEW_NIBBLE10 int true 0BRAM_RDDQ_QTR_DESKEW_NIBBLE11 int true 0BRAM_RDDQ_QTR_DESKEW_NIBBLE12 int true 0BRAM_RDDQ_QTR_DESKEW_NIBBLE13 int true 0BRAM_RDDQ_QTR_DESKEW_NIBBLE14 int true 0BRAM_RDDQ_QTR_DESKEW_NIBBLE15 int true 0
Appendix B: Debugging
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BRAM_RDDQ_IDELAY_FINAL_BIT00 int true 59BRAM_RDDQ_IDELAY_FINAL_BIT01 int true 70BRAM_RDDQ_IDELAY_FINAL_BIT02 int true 58BRAM_RDDQ_IDELAY_FINAL_BIT03 int true 61BRAM_RDDQ_IDELAY_FINAL_BIT04 int true 69BRAM_RDDQ_IDELAY_FINAL_BIT05 int true 78BRAM_RDDQ_IDELAY_FINAL_BIT06 int true 73BRAM_RDDQ_IDELAY_FINAL_BIT07 int true 73BRAM_RDDQ_IDELAY_FINAL_BIT08 int true 63BRAM_RDDQ_IDELAY_FINAL_BIT09 int true 70BRAM_RDDQ_IDELAY_FINAL_BIT10 int true 55BRAM_RDDQ_IDELAY_FINAL_BIT11 int true 63BRAM_RDDQ_IDELAY_FINAL_BIT12 int true 76BRAM_RDDQ_IDELAY_FINAL_BIT13 int true 68BRAM_RDDQ_IDELAY_FINAL_BIT14 int true 68BRAM_RDDQ_IDELAY_FINAL_BIT15 int true 60BRAM_RDDQ_IDELAY_FINAL_BIT16 int true 71BRAM_RDDQ_IDELAY_FINAL_BIT17 int true 70BRAM_RDDQ_IDELAY_FINAL_BIT18 int true 69BRAM_RDDQ_IDELAY_FINAL_BIT19 int true 73BRAM_RDDQ_IDELAY_FINAL_BIT20 int true 61BRAM_RDDQ_IDELAY_FINAL_BIT21 int true 75BRAM_RDDQ_IDELAY_FINAL_BIT22 int true 71BRAM_RDDQ_IDELAY_FINAL_BIT23 int true 77BRAM_RDDQ_IDELAY_FINAL_BIT24 int true 63BRAM_RDDQ_IDELAY_FINAL_BIT25 int true 69BRAM_RDDQ_IDELAY_FINAL_BIT26 int true 60BRAM_RDDQ_IDELAY_FINAL_BIT27 int true 62BRAM_RDDQ_IDELAY_FINAL_BIT28 int true 68BRAM_RDDQ_IDELAY_FINAL_BIT29 int true 70BRAM_RDDQ_IDELAY_FINAL_BIT30 int true 67BRAM_RDDQ_IDELAY_FINAL_BIT31 int true 71BRAM_RDDQ_IDELAY_FINAL_BIT32 int true 64BRAM_RDDQ_IDELAY_FINAL_BIT33 int true 66BRAM_RDDQ_IDELAY_FINAL_BIT34 int true 55BRAM_RDDQ_IDELAY_FINAL_BIT35 int true 61BRAM_RDDQ_IDELAY_FINAL_BIT36 int true 63BRAM_RDDQ_IDELAY_FINAL_BIT37 int true 69BRAM_RDDQ_IDELAY_FINAL_BIT38 int true 69BRAM_RDDQ_IDELAY_FINAL_BIT39 int true 69BRAM_RDDQ_IDELAY_FINAL_BIT40 int true 66BRAM_RDDQ_IDELAY_FINAL_BIT41 int true 63BRAM_RDDQ_IDELAY_FINAL_BIT42 int true 61BRAM_RDDQ_IDELAY_FINAL_BIT43 int true 62BRAM_RDDQ_IDELAY_FINAL_BIT44 int true 67BRAM_RDDQ_IDELAY_FINAL_BIT45 int true 67BRAM_RDDQ_IDELAY_FINAL_BIT46 int true 69BRAM_RDDQ_IDELAY_FINAL_BIT47 int true 69BRAM_RDDQ_IDELAY_FINAL_BIT48 int true 73BRAM_RDDQ_IDELAY_FINAL_BIT49 int true 75BRAM_RDDQ_IDELAY_FINAL_BIT50 int true 68BRAM_RDDQ_IDELAY_FINAL_BIT51 int true 65BRAM_RDDQ_IDELAY_FINAL_BIT52 int true 67BRAM_RDDQ_IDELAY_FINAL_BIT53 int true 77BRAM_RDDQ_IDELAY_FINAL_BIT54 int true 77BRAM_RDDQ_IDELAY_FINAL_BIT55 int true 73BRAM_RDDQ_IDELAY_FINAL_BIT56 int true 61BRAM_RDDQ_IDELAY_FINAL_BIT57 int true 75BRAM_RDDQ_IDELAY_FINAL_BIT58 int true 68
Appendix B: Debugging
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BRAM_RDDQ_IDELAY_FINAL_BIT59 int true 67BRAM_RDDQ_IDELAY_FINAL_BIT60 int true 68BRAM_RDDQ_IDELAY_FINAL_BIT61 int true 77BRAM_RDDQ_IDELAY_FINAL_BIT62 int true 73BRAM_RDDQ_IDELAY_FINAL_BIT63 int true 74
Related Information
Manually Analyzing the XSDB Output
Expected Results
• Look at the individual IDELAY taps for each bit. The IDELAY taps should only vary by 0 to 20taps, and is dependent on PCB trace delays. For Deskew, the IDELAY taps are typically in the50 to 70 tap range, while PQTR and NQTR are usually in the 0 to 20 tap range.
• Determine if any bytes completed successfully. The per-bit algorithm steps in parallel througheach DQS byte.
2. Probe a data pin to check for data being returned from the DRAM.
3. Probe the read burst and check if the expected data pattern is being returned.
4. Check for floating address pins if the expected data is not returned.
5. Check for any stuck-at level issues on DQ pins whose signal level does not change. Ifpossible, probe at the receiver to check termination and signal integrity.
6. Check the DBG port signals and the full read data and comparison result to check the data ingeneral interconnect. Check if the dbg_rd_valid aligns with the data pattern or is off(which can indicate an issue with DQS gate calibration). Set up a trigger when the error getsasserted to capture signals in the hardware debugger for analysis.
7. Re-check results from DQS gate or other previous calibration stages. Compare passing bytelanes against failing byte lanes for previous stages of calibration. If a failure occurs duringsimple pattern calibration, check the values found during deskew for example.
8. All of the data comparison for read deskew occurs in the general interconnect, so it can beuseful to pull in the debug data in the hardware debugger and take a look at what the datalooks like coming back as taps are adjusted, see the figure below. The screen capture is fromsimulation with a small burst of five reads. Look at dbg_rd_data, dbg_rd_data_cmp, anddbg_rd_valid.
9. Use the Vivado Hardware Manager while running the Memory IP Example Design withDebug Signals enabled, set the Read Deskew trigger to cal_r*_status[22] = R (risingedge). To view each byte, add an additional trigger on dbg_cmp_byte and set to the byte ofinterest. The following simulation example shows how the debug signals should behaveduring successful Read Deskew.
Appendix B: Debugging
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After the data is deskewed, the PQTR/NQTR delays need to be adjusted to center in theaggregate data valid window for a given nibble. The DRAM MPR register is used to provide thedata pattern for centering. Therefore, the pattern changes each bit time and does not rely onbeing written into the DRAM first, eliminating some uncertainty. Gaps in the reads to the DRAMare used to stress the initial centering to incorporate the effects of ISI on the first DQS pulse asshown in the figure.
Figure 69: Gap between MPR Read
DQS/DQS#
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1DQ/DQ#
X24724-101420
Given that the PHY has two capture strobes PDQS/NDQS that need to be centeredindependently yet moved together, calibration needs to take special care to ensure the clocksstay in a certain phase relationship with one another.
Appendix B: Debugging
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The data and PDQS/NDQS strobe delays start with the value found during DQ per bit deskew.Data is first delayed with IDELAY such that both the PDQS and NDQS clocks start out just to theleft of the data valid window for all bits in a given nibble, so the entire read window can bescanned with each clock (see figure below, BRAM_DQ_IDELAY_FINAL_BIT*). Scanning thewindow with the same delay element and computing the center with that delay element helps tominimize uncertainty in tap resolution that might arise from using different delay lines to find theedges of the read window.
Figure 70: Delay DQ Thus PDQS and NDQS in Failing Region
0Original DQ
PDQS
NDQS
F 0 F
0DQ F 0 F
Delay the data using IDELAYX24716-101420
At the start of training, the PDQS/NDQS and data are roughly edge aligned. During deskew theaggregate edge for both PDQS/NDQS is found while you want to find a separate edge for eachclock.
After making sure both PDQS/NDQS start outside the data valid region, the clocks areincremented to look for the passing region (see figure below). Rising edge data is checked forPDQS while falling edge data is checked for NDQS, with a separate check to indicate where thepassing region/falling region is for each clock.
Appendix B: Debugging
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Figure 71: PDQS and NDQS Delayed to Find Passing Region (Left Edge)
0DQ
PDQS
NDQS
F 0 F
X24732-101420
When searching for the edge, a minimum window size of 15 is used to guarantee the noiseregion has been cleared and the true edge is found. The PQDS/NDQS delays are increased pastthe initial passing point until the minimum window size is found before the left edge is declaredas found. If the minimum window is not located across the entire tap range for either clock, anerror is asserted.
After the left edge is found (BRAM_RDDQ_PQTR_LEFT_NIBBLE*,BRAM_RDDQ_PQTR_LEFT_NIBBLE*), the right edge of the data valid window can be searchedstarting from the left edge + minimum window size. Again, the PQTR/NQTR delays areincremented together using step size of 10 taps and checked for error independently to keeptrack of the right edge of the window. Because the data from the PDQS domain is transferredinto the NDQS clock domain in the XPHY, the edge for NDQS is checked first, keeping track ofthe results for PDQS along the way (see figure below).
When the NDQS edge is located, a flag is checked to see if the PDQS edge is found as well. If thePDQS edge was not found, the PQTR delay continues to search for the edge, while the NQTRdelay stays at its right edge (BRAM_RDDQ_PQTR_RIGHT_FCRSE_NIBBLE*,BRAM_RDDQ_NQTR_RIGHT_FCRSE_NIBBLE*).
The PQTR/NQTR delays are decremented together using step size of 1 tap to ensure a minimumwindow size of 15 is detected to guarantee the noise region has been cleared and the true rightedge is found (BRAM_RDDQ_PQTR_RIGHT_NIBBLE*, BRAM_RDDQ_NQTR_RIGHT_NIBBLE*).
Appendix B: Debugging
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Figure 72: PDQS and NDQS Delayed to Find Failing Region (Right Edge)
0DQ
PDQS
NDQS
F 0 F
Left Edge Minimum Window Size
PDQS Right
NDQS Right
X24731-101420
After both rising and falling edge windows are found, the final center point is calculated based onthe left and right edges for each clock. The final delay for each clock(BRAM_RDDQ_PQTR_FINAL_NIBBLE*, BRAM_RDDQ_NQTR_FINAL_NIBBLE*) is computed by:left + ((right – left) / 2).
Debug
To determine the status of Read DQS Centering Calibration, click the READ_DQ_CAL stageunder the Status window and view the results within the Memory IP Properties window. Themessage displayed in the Memory IP Properties identifies how the stage failed, or notes if itpassed successfully. Check CAL_ERROR for confirming whether the calibration failure is in ReadPer-Bit DQ Deskew or Read DQ Centering stage.
Appendix B: Debugging
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Figure 73: Memory IP XSDB Debug GUI Example – Read Leveling (Read DQ Centering)
CAL_ERROR Decode for Read DQS Centering Calibration
The status of Read DQS Centering can also be determined by decoding the CAL_ERROR resultaccording to the table below. Execute the Tcl commands noted in the Manually Analyzing theXSDB Output section to generate the XSDB output containing the signal results.
Table 109: CAL_ERROR Decode for Read DQS Centering Calibration
Error Code Description Recommended Debug Step
16 Noise region not found for a given bit in thenibble by incrementing DQ IDELAY
Check for a mapping issue. This usually implies adelay is not moving when it should. Check theconnections going to the XPHY and ensure thecorrect RIU is selected based on the byte beingadjusted.
17 Could not find the left edge of valid data windowby incrementing PQTR/NQTR IDELAY together.
Check for a mapping issue. This usually implies adelay is not moving when it should. Check theconnections going to the XPHY and ensure thecorrect RIU is selected based on the byte beingadjusted.
18Could not find the right edge of valid datawindow by decrementing PQTR/NQTR IDELAYtogether.
Check for a mapping issue. This usually implies adelay is not moving when it should. Check theconnections going to the XPHY and ensure thecorrect RIU is selected based on the byte beingadjusted.
Appendix B: Debugging
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Table 109: CAL_ERROR Decode for Read DQS Centering Calibration (cont'd)
Error Code Description Recommended Debug Step
19 Negative sanity check failed.
Check CAL_ERROR_BIT_*_*,CAL_ERROR_DATA_NIBBLE_*_*,CAL_ERROR_PHY_NIBBLE_*_* XSDB registers todetermine which nibbles/bits failed. Checkmargin found during previous stages ofcalibration for the given byte that failed.
20 Positive sanity check failed.
Check CAL_ERROR_BIT_*_*,CAL_ERROR_DATA_NIBBLE_*_*,CAL_ERROR_PHY_NIBBLE_*_* XSDB registers todetermine which nibbles/bits failed. Checkmargin found during previous stages ofcalibration for the given byte that failed.
Related Information
Manually Analyzing the XSDB Output
XSDB Registers of Interest during Read DQS Centering Calibration
The table shows the XSDB registers and values adjusted or used during the Read DQS Centeringstage of calibration. The values can be analyzed in both successful and failing calibrations todetermine the resultant values and the consistency in results across resets. These values can befound within the Memory IP core properties in the Hardware Manager or by executing the Tclcommands noted in the Manually Analyzing the XSDB Output section.
Table 110: XSDB Registers of Interest during Read DQS Centering Calibration
XSDB Reg Usage Signal Description
BRAM_RDDQ_IDELAY_FINAL_BIT* One per bit Read leveling IDELAY delay value foundduring Read DQS Centering.
BRAM_RDDQ_PQTR_LEFT_NIBBLE* One per nibbleRead leveling PQTR tap position whenleft edge of read data valid window isdetected (Simple).
BRAM_RDDQ_NQTR_LEFT_NIBBLE* One per nibbleRead leveling NQTR tap position whenleft edge of read data valid window isdetected (Simple).
BRAM_RDDQ_PQTR_RIGHT_FCRSE_NIBBLE* One per nibble
Read leveling PQTR tap position whenright edge of read data valid window isdetected by incrementing PQTR/NQTRIDELAY using step size of 10 taps(Simple).
BRAM_RDDQ_NQTR_RIGHT_FCRSE_NIBBLE* One per nibble
Read leveling NQTR tap position whenright edge of read data valid window isdetected by incrementing PQTR/NQTRIDELAY using step size of 10 taps(Simple).
BRAM_RDDQ_PQTR_RIGHT_NIBBLE* One per nibbleRead leveling PQTR tap position whenright edge of read data valid window isdetected (Simple).
Appendix B: Debugging
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Table 110: XSDB Registers of Interest during Read DQS Centering Calibration (cont'd)
XSDB Reg Usage Signal Description
BRAM_RDDQ_NQTR_RIGHT_NIBBLE* One per nibbleRead leveling NQTR tap position whenright edge of read data valid window isdetected (Simple).
BRAM_RDDQ_PQTR_FINAL_NIBBLE* One per nibbleRead leveling PQTR center tap positionfound at the end of read DQS centering(Simple).
BRAM_RDDQ_NQTR_FINAL_NIBBLE* One per nibbleRead leveling NQTR center tap positionfound at the end of read DQS centering(Simple).
BISC_ALIGN_PQTR_NIBBLE* One per nibble Initial 0° offset value provided by BISCat power-up.
BISC_ALIGN_NQTR_NIBBLE* One per nibble Initial 0° offset value provided by BISCat power-up.
BISC_PQTR_NIBBLE* One per nibble
Initial 90° offset value provided by BISCat power-up. Compute 90° value in tapsby taking (BISC_PQTR –BISC_ALIGN_PQTR). To estimate tapresolution take (¼ of the memory clockperiod)/ (BISC_PQTR –BISC_ALIGN_PQTR).
BISC_NQTR_NIBBLE* One per nibble
Initial 90° offset value provided by BISCat power-up. Compute 90° value in tapsby taking (BISC_PQTR –BISC_ALIGN_PQTR). To estimate tapresolution take (¼ of the memory clockperiod)/ (BISC_PQTR –BISC_ALIGN_PQTR).
This is a sample of results for Read MPR DQS Centering using the Memory IP Debug GUI withinthe Hardware Manager.
Note: Either the “Table” or “Chart” view can be used to look at the window.
Appendix B: Debugging
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Figure 74: Example Read Calibration Margin from Memory IP Debug GUI
This is a sample of results for the Read Per-Bit Deskew XSDB debug signals:
BRAM_RDDQ_IDELAY_FINAL_BIT00 int true 59BRAM_RDDQ_IDELAY_FINAL_BIT01 int true 70BRAM_RDDQ_IDELAY_FINAL_BIT02 int true 58BRAM_RDDQ_IDELAY_FINAL_BIT03 int true 61BRAM_RDDQ_IDELAY_FINAL_BIT04 int true 69BRAM_RDDQ_IDELAY_FINAL_BIT05 int true 78BRAM_RDDQ_IDELAY_FINAL_BIT06 int true 73BRAM_RDDQ_IDELAY_FINAL_BIT07 int true 73BRAM_RDDQ_IDELAY_FINAL_BIT08 int true 63
Appendix B: Debugging
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BRAM_RDDQ_IDELAY_FINAL_BIT09 int true 70BRAM_RDDQ_IDELAY_FINAL_BIT10 int true 55BRAM_RDDQ_IDELAY_FINAL_BIT11 int true 63BRAM_RDDQ_IDELAY_FINAL_BIT12 int true 76BRAM_RDDQ_IDELAY_FINAL_BIT13 int true 68BRAM_RDDQ_IDELAY_FINAL_BIT14 int true 68BRAM_RDDQ_IDELAY_FINAL_BIT15 int true 60BRAM_RDDQ_IDELAY_FINAL_BIT16 int true 71BRAM_RDDQ_IDELAY_FINAL_BIT17 int true 70BRAM_RDDQ_IDELAY_FINAL_BIT18 int true 69BRAM_RDDQ_IDELAY_FINAL_BIT19 int true 73BRAM_RDDQ_IDELAY_FINAL_BIT20 int true 61BRAM_RDDQ_IDELAY_FINAL_BIT21 int true 75BRAM_RDDQ_IDELAY_FINAL_BIT22 int true 71BRAM_RDDQ_IDELAY_FINAL_BIT23 int true 77BRAM_RDDQ_IDELAY_FINAL_BIT24 int true 63BRAM_RDDQ_IDELAY_FINAL_BIT25 int true 69BRAM_RDDQ_IDELAY_FINAL_BIT26 int true 60BRAM_RDDQ_IDELAY_FINAL_BIT27 int true 62BRAM_RDDQ_IDELAY_FINAL_BIT28 int true 68BRAM_RDDQ_IDELAY_FINAL_BIT29 int true 70BRAM_RDDQ_IDELAY_FINAL_BIT30 int true 67BRAM_RDDQ_IDELAY_FINAL_BIT31 int true 71BRAM_RDDQ_IDELAY_FINAL_BIT32 int true 64BRAM_RDDQ_IDELAY_FINAL_BIT33 int true 66BRAM_RDDQ_IDELAY_FINAL_BIT34 int true 55BRAM_RDDQ_IDELAY_FINAL_BIT35 int true 61BRAM_RDDQ_IDELAY_FINAL_BIT36 int true 63BRAM_RDDQ_IDELAY_FINAL_BIT37 int true 69BRAM_RDDQ_IDELAY_FINAL_BIT38 int true 69BRAM_RDDQ_IDELAY_FINAL_BIT39 int true 69BRAM_RDDQ_IDELAY_FINAL_BIT40 int true 66BRAM_RDDQ_IDELAY_FINAL_BIT41 int true 63BRAM_RDDQ_IDELAY_FINAL_BIT42 int true 61BRAM_RDDQ_IDELAY_FINAL_BIT43 int true 62BRAM_RDDQ_IDELAY_FINAL_BIT44 int true 67BRAM_RDDQ_IDELAY_FINAL_BIT45 int true 67BRAM_RDDQ_IDELAY_FINAL_BIT46 int true 69BRAM_RDDQ_IDELAY_FINAL_BIT47 int true 69BRAM_RDDQ_IDELAY_FINAL_BIT48 int true 73BRAM_RDDQ_IDELAY_FINAL_BIT49 int true 75BRAM_RDDQ_IDELAY_FINAL_BIT50 int true 68BRAM_RDDQ_IDELAY_FINAL_BIT51 int true 65BRAM_RDDQ_IDELAY_FINAL_BIT52 int true 67BRAM_RDDQ_IDELAY_FINAL_BIT53 int true 77BRAM_RDDQ_IDELAY_FINAL_BIT54 int true 77BRAM_RDDQ_IDELAY_FINAL_BIT55 int true 73BRAM_RDDQ_IDELAY_FINAL_BIT56 int true 61BRAM_RDDQ_IDELAY_FINAL_BIT57 int true 75BRAM_RDDQ_IDELAY_FINAL_BIT58 int true 68BRAM_RDDQ_IDELAY_FINAL_BIT59 int true 67BRAM_RDDQ_IDELAY_FINAL_BIT60 int true 68BRAM_RDDQ_IDELAY_FINAL_BIT61 int true 77BRAM_RDDQ_IDELAY_FINAL_BIT62 int true 73BRAM_RDDQ_IDELAY_FINAL_BIT63 int true 74BRAM_RDDQ_PQTR_LEFT_NIBBLE0 int true 22BRAM_RDDQ_PQTR_LEFT_NIBBLE1 int true 22BRAM_RDDQ_PQTR_LEFT_NIBBLE2 int true 22BRAM_RDDQ_PQTR_LEFT_NIBBLE3 int true 22BRAM_RDDQ_PQTR_LEFT_NIBBLE4 int true 22BRAM_RDDQ_PQTR_LEFT_NIBBLE5 int true 22BRAM_RDDQ_PQTR_LEFT_NIBBLE6 int true 22BRAM_RDDQ_PQTR_LEFT_NIBBLE7 int true 22
Appendix B: Debugging
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BRAM_RDDQ_PQTR_LEFT_NIBBLE8 int true 22BRAM_RDDQ_PQTR_LEFT_NIBBLE9 int true 22BRAM_RDDQ_PQTR_LEFT_NIBBLE10 int true 22BRAM_RDDQ_PQTR_LEFT_NIBBLE11 int true 22BRAM_RDDQ_PQTR_LEFT_NIBBLE12 int true 22BRAM_RDDQ_PQTR_LEFT_NIBBLE13 int true 22BRAM_RDDQ_PQTR_LEFT_NIBBLE14 int true 22BRAM_RDDQ_PQTR_LEFT_NIBBLE15 int true 22BRAM_RDDQ_NQTR_LEFT_NIBBLE0 int true 33BRAM_RDDQ_NQTR_LEFT_NIBBLE1 int true 42BRAM_RDDQ_NQTR_LEFT_NIBBLE2 int true 37BRAM_RDDQ_NQTR_LEFT_NIBBLE3 int true 60BRAM_RDDQ_NQTR_LEFT_NIBBLE4 int true 42BRAM_RDDQ_NQTR_LEFT_NIBBLE5 int true 39BRAM_RDDQ_NQTR_LEFT_NIBBLE6 int true 43BRAM_RDDQ_NQTR_LEFT_NIBBLE7 int true 42BRAM_RDDQ_NQTR_LEFT_NIBBLE8 int true 37BRAM_RDDQ_NQTR_LEFT_NIBBLE9 int true 42BRAM_RDDQ_NQTR_LEFT_NIBBLE10 int true 40BRAM_RDDQ_NQTR_LEFT_NIBBLE11 int true 43BRAM_RDDQ_NQTR_LEFT_NIBBLE12 int true 42BRAM_RDDQ_NQTR_LEFT_NIBBLE13 int true 39BRAM_RDDQ_NQTR_LEFT_NIBBLE14 int true 36BRAM_RDDQ_NQTR_LEFT_NIBBLE15 int true 39BRAM_RDDQ_PQTR_RIGHT_FCRSE_NIBBLE0 int true 192BRAM_RDDQ_PQTR_RIGHT_FCRSE_NIBBLE1 int true 192BRAM_RDDQ_PQTR_RIGHT_FCRSE_NIBBLE2 int true 192BRAM_RDDQ_PQTR_RIGHT_FCRSE_NIBBLE3 int true 192BRAM_RDDQ_PQTR_RIGHT_FCRSE_NIBBLE4 int true 192BRAM_RDDQ_PQTR_RIGHT_FCRSE_NIBBLE5 int true 202BRAM_RDDQ_PQTR_RIGHT_FCRSE_NIBBLE6 int true 192BRAM_RDDQ_PQTR_RIGHT_FCRSE_NIBBLE7 int true 192BRAM_RDDQ_PQTR_RIGHT_FCRSE_NIBBLE8 int true 0BRAM_RDDQ_PQTR_RIGHT_FCRSE_NIBBLE9 int true 0BRAM_RDDQ_PQTR_RIGHT_FCRSE_NIBBLE10 int true 0BRAM_RDDQ_PQTR_RIGHT_FCRSE_NIBBLE11 int true 0BRAM_RDDQ_PQTR_RIGHT_FCRSE_NIBBLE12 int true 0BRAM_RDDQ_PQTR_RIGHT_FCRSE_NIBBLE13 int true 0BRAM_RDDQ_PQTR_RIGHT_FCRSE_NIBBLE14 int true 0BRAM_RDDQ_PQTR_RIGHT_FCRSE_NIBBLE15 int true 0BRAM_RDDQ_NQTR_RIGHT_FCRSE_NIBBLE0 int true 183BRAM_RDDQ_NQTR_RIGHT_FCRSE_NIBBLE1 int true 192BRAM_RDDQ_NQTR_RIGHT_FCRSE_NIBBLE2 int true 187BRAM_RDDQ_NQTR_RIGHT_FCRSE_NIBBLE3 int true 200BRAM_RDDQ_NQTR_RIGHT_FCRSE_NIBBLE4 int true 182BRAM_RDDQ_NQTR_RIGHT_FCRSE_NIBBLE5 int true 189BRAM_RDDQ_NQTR_RIGHT_FCRSE_NIBBLE6 int true 193BRAM_RDDQ_NQTR_RIGHT_FCRSE_NIBBLE7 int true 192BRAM_RDDQ_NQTR_RIGHT_FCRSE_NIBBLE8 int true 0BRAM_RDDQ_NQTR_RIGHT_FCRSE_NIBBLE9 int true 0BRAM_RDDQ_NQTR_RIGHT_FCRSE_NIBBLE10 int true 0BRAM_RDDQ_NQTR_RIGHT_FCRSE_NIBBLE11 int true 0BRAM_RDDQ_NQTR_RIGHT_FCRSE_NIBBLE12 int true 0BRAM_RDDQ_NQTR_RIGHT_FCRSE_NIBBLE13 int true 0BRAM_RDDQ_NQTR_RIGHT_FCRSE_NIBBLE14 int true 0BRAM_RDDQ_NQTR_RIGHT_FCRSE_NIBBLE15 int true 0BRAM_RDDQ_PQTR_RIGHT_NIBBLE0 int true 172BRAM_RDDQ_PQTR_RIGHT_NIBBLE1 int true 175BRAM_RDDQ_PQTR_RIGHT_NIBBLE2 int true 172BRAM_RDDQ_PQTR_RIGHT_NIBBLE3 int true 172BRAM_RDDQ_PQTR_RIGHT_NIBBLE4 int true 174BRAM_RDDQ_PQTR_RIGHT_NIBBLE5 int true 179BRAM_RDDQ_PQTR_RIGHT_NIBBLE6 int true 172
Appendix B: Debugging
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BRAM_RDDQ_PQTR_RIGHT_NIBBLE7 int true 175BRAM_RDDQ_PQTR_RIGHT_NIBBLE8 int true 175BRAM_RDDQ_PQTR_RIGHT_NIBBLE9 int true 176BRAM_RDDQ_PQTR_RIGHT_NIBBLE10 int true 175BRAM_RDDQ_PQTR_RIGHT_NIBBLE11 int true 176BRAM_RDDQ_PQTR_RIGHT_NIBBLE12 int true 176BRAM_RDDQ_PQTR_RIGHT_NIBBLE13 int true 173BRAM_RDDQ_PQTR_RIGHT_NIBBLE14 int true 176BRAM_RDDQ_PQTR_RIGHT_NIBBLE15 int true 176BRAM_RDDQ_NQTR_RIGHT_NIBBLE0 int true 167BRAM_RDDQ_NQTR_RIGHT_NIBBLE1 int true 172BRAM_RDDQ_NQTR_RIGHT_NIBBLE2 int true 170BRAM_RDDQ_NQTR_RIGHT_NIBBLE3 int true 175BRAM_RDDQ_NQTR_RIGHT_NIBBLE4 int true 165BRAM_RDDQ_NQTR_RIGHT_NIBBLE5 int true 168BRAM_RDDQ_NQTR_RIGHT_NIBBLE6 int true 172BRAM_RDDQ_NQTR_RIGHT_NIBBLE7 int true 171BRAM_RDDQ_NQTR_RIGHT_NIBBLE8 int true 164BRAM_RDDQ_NQTR_RIGHT_NIBBLE9 int true 166BRAM_RDDQ_NQTR_RIGHT_NIBBLE10 int true 171BRAM_RDDQ_NQTR_RIGHT_NIBBLE11 int true 170BRAM_RDDQ_NQTR_RIGHT_NIBBLE12 int true 166BRAM_RDDQ_NQTR_RIGHT_NIBBLE13 int true 166BRAM_RDDQ_NQTR_RIGHT_NIBBLE14 int true 166BRAM_RDDQ_NQTR_RIGHT_NIBBLE15 int true 168BRAM_RDDQ_PQTR_FINAL_NIBBLE0 int true 97BRAM_RDDQ_PQTR_FINAL_NIBBLE1 int true 98BRAM_RDDQ_PQTR_FINAL_NIBBLE2 int true 97BRAM_RDDQ_PQTR_FINAL_NIBBLE3 int true 97BRAM_RDDQ_PQTR_FINAL_NIBBLE4 int true 98BRAM_RDDQ_PQTR_FINAL_NIBBLE5 int true 100BRAM_RDDQ_PQTR_FINAL_NIBBLE6 int true 97BRAM_RDDQ_PQTR_FINAL_NIBBLE7 int true 98BRAM_RDDQ_PQTR_FINAL_NIBBLE8 int true 98BRAM_RDDQ_PQTR_FINAL_NIBBLE9 int true 99BRAM_RDDQ_PQTR_FINAL_NIBBLE10 int true 98BRAM_RDDQ_PQTR_FINAL_NIBBLE11 int true 99BRAM_RDDQ_PQTR_FINAL_NIBBLE12 int true 99BRAM_RDDQ_PQTR_FINAL_NIBBLE13 int true 97BRAM_RDDQ_PQTR_FINAL_NIBBLE14 int true 99BRAM_RDDQ_PQTR_FINAL_NIBBLE15 int true 99BRAM_RDDQ_NQTR_FINAL_NIBBLE0 int true 100BRAM_RDDQ_NQTR_FINAL_NIBBLE1 int true 107BRAM_RDDQ_NQTR_FINAL_NIBBLE2 int true 103BRAM_RDDQ_NQTR_FINAL_NIBBLE3 int true 117BRAM_RDDQ_NQTR_FINAL_NIBBLE4 int true 103BRAM_RDDQ_NQTR_FINAL_NIBBLE5 int true 103BRAM_RDDQ_NQTR_FINAL_NIBBLE6 int true 107BRAM_RDDQ_NQTR_FINAL_NIBBLE7 int true 106BRAM_RDDQ_NQTR_FINAL_NIBBLE8 int true 100BRAM_RDDQ_NQTR_FINAL_NIBBLE9 int true 104BRAM_RDDQ_NQTR_FINAL_NIBBLE10 int true 105BRAM_RDDQ_NQTR_FINAL_NIBBLE11 int true 106BRAM_RDDQ_NQTR_FINAL_NIBBLE12 int true 104BRAM_RDDQ_NQTR_FINAL_NIBBLE13 int true 102BRAM_RDDQ_NQTR_FINAL_NIBBLE14 int true 101BRAM_RDDQ_NQTR_FINAL_NIBBLE15 int true 103BRAM_BISC_PQTR_ALIGN_NIBBLE0 int true 1BRAM_BISC_PQTR_ALIGN_NIBBLE1 int true 0BRAM_BISC_PQTR_ALIGN_NIBBLE2 int true 1BRAM_BISC_PQTR_ALIGN_NIBBLE3 int true 0BRAM_BISC_PQTR_ALIGN_NIBBLE4 int true 0BRAM_BISC_PQTR_ALIGN_NIBBLE5 int true 2
Appendix B: Debugging
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BRAM_BISC_PQTR_ALIGN_NIBBLE6 int true 0BRAM_BISC_PQTR_ALIGN_NIBBLE7 int true 0BRAM_BISC_PQTR_ALIGN_NIBBLE8 int true 1BRAM_BISC_PQTR_ALIGN_NIBBLE9 int true 1BRAM_BISC_PQTR_ALIGN_NIBBLE10 int true 0BRAM_BISC_PQTR_ALIGN_NIBBLE11 int true 33BRAM_BISC_PQTR_ALIGN_NIBBLE12 int true 0BRAM_BISC_PQTR_ALIGN_NIBBLE13 int true 1BRAM_BISC_PQTR_ALIGN_NIBBLE14 int true 1BRAM_BISC_PQTR_ALIGN_NIBBLE15 int true 2BRAM_BISC_NQTR_ALIGN_NIBBLE0 int true 0BRAM_BISC_NQTR_ALIGN_NIBBLE1 int true 1BRAM_BISC_NQTR_ALIGN_NIBBLE2 int true 0BRAM_BISC_NQTR_ALIGN_NIBBLE3 int true 1BRAM_BISC_NQTR_ALIGN_NIBBLE4 int true 0BRAM_BISC_NQTR_ALIGN_NIBBLE5 int true 0BRAM_BISC_NQTR_ALIGN_NIBBLE6 int true 2BRAM_BISC_NQTR_ALIGN_NIBBLE7 int true 0BRAM_BISC_NQTR_ALIGN_NIBBLE8 int true 0BRAM_BISC_NQTR_ALIGN_NIBBLE9 int true 0BRAM_BISC_NQTR_ALIGN_NIBBLE10 int true 1BRAM_BISC_NQTR_ALIGN_NIBBLE11 int true 0BRAM_BISC_NQTR_ALIGN_NIBBLE12 int true 1BRAM_BISC_NQTR_ALIGN_NIBBLE13 int true 0BRAM_BISC_NQTR_ALIGN_NIBBLE14 int true 0BRAM_BISC_NQTR_ALIGN_NIBBLE15 int true 0BRAM_BISC_PQTR_NIBBLE0 int true 89BRAM_BISC_PQTR_NIBBLE1 int true 88BRAM_BISC_PQTR_NIBBLE2 int true 89BRAM_BISC_PQTR_NIBBLE3 int true 87BRAM_BISC_PQTR_NIBBLE4 int true 88BRAM_BISC_PQTR_NIBBLE5 int true 88BRAM_BISC_PQTR_NIBBLE6 int true 89BRAM_BISC_PQTR_NIBBLE7 int true 88BRAM_BISC_PQTR_NIBBLE8 int true 88BRAM_BISC_PQTR_NIBBLE9 int true 91BRAM_BISC_PQTR_NIBBLE10 int true 90BRAM_BISC_PQTR_NIBBLE11 int true 92BRAM_BISC_PQTR_NIBBLE12 int true 89BRAM_BISC_PQTR_NIBBLE13 int true 90BRAM_BISC_PQTR_NIBBLE14 int true 90BRAM_BISC_PQTR_NIBBLE15 int true 90BRAM_BISC_NQTR_NIBBLE0 int true 87BRAM_BISC_NQTR_NIBBLE1 int true 90BRAM_BISC_NQTR_NIBBLE2 int true 90BRAM_BISC_NQTR_NIBBLE3 int true 89BRAM_BISC_NQTR_NIBBLE4 int true 87BRAM_BISC_NQTR_NIBBLE5 int true 89BRAM_BISC_NQTR_NIBBLE6 int true 91BRAM_BISC_NQTR_NIBBLE7 int true 91BRAM_BISC_NQTR_NIBBLE8 int true 87BRAM_BISC_NQTR_NIBBLE9 int true 91BRAM_BISC_NQTR_NIBBLE10 int true 90BRAM_BISC_NQTR_NIBBLE11 int true 91BRAM_BISC_NQTR_NIBBLE12 int true 90BRAM_BISC_NQTR_NIBBLE13 int true 90BRAM_BISC_NQTR_NIBBLE14 int true 88BRAM_BISC_NQTR_NIBBLE15 int true 89
Related Information
Manually Analyzing the XSDB Output
Appendix B: Debugging
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• Look at the individual PQTR/NQTR tap settings for each nibble. The taps should only vary by0 to 20 taps. Use the BISC values to compute the estimated bit time in taps
• Determine if any bytes completed successfully. The read DQS Centering algorithm stepsthrough each DQS byte group detecting the capture edges.
• To analyze the window size in ps, see the Determining Window Size in ps section. In somecases, simple pattern calibration might show a better than ideal rise or fall window. Because asimple pattern (clock pattern) is used, it is possible for the rising edge clock to always find thesame value (for example, 1) and the falling edge to always find the opposite (for example, 0).This can occur due to a non-ideal starting VREF value which causes duty cycle distortionmaking the rise or fall larger than the other. If the rise and fall window sizes are addedtogether and compared against the expected clock cycle time, the result should be morereasonable. As a general rule of thumb, the window size for a healthy system should be ≥ 30%of the expected UI size.
Related Information
Determining Window Size in ps
Hardware Measurements
1. Using high quality probes and scope, probe the address/command to ensure the load registercommand to the DRAM that enables MPR was correct. To enable the MPR, a Mode registerset (MRS) command is issued to the MR3 register with bit A2 = 1. To make this measurement,bring a scope trigger to an I/O based on the following conditions:
• To view each byte, add an additional trigger on dbg_cmp_byte and set to the byte ofinterest. Within this capture, A2 (must be 1) and we_n (must be 0)
3. Probe a data pin to check for data being returned from the DRAM.
4. Probe the read burst and check if the expected data pattern is being returned.
5. Check for floating address pins if the expected data is not returned.
6. Check for any stuck-at level issues on DQ pins whose signal level does not change. If at allpossible probe at the receiver to check termination and signal integrity.
7. Check the DBG port signals and the full read data and comparison result to check the data ingeneral interconnect. The calibration algorithm has RTL logic issue the commands and checkthe data. Check if the dbg_rd_valid aligns with the data pattern or is OFF (which canindicate an issue with DQS gate calibration). Set up a trigger when the error gets asserted tocapture signals in the hardware debugger for analysis.
Appendix B: Debugging
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8. Re-check results from DQS gate or other previous calibration stages. Compare passing bytelanes against failing byte lanes for previous stages of calibration. If a failure occurs duringsimple pattern calibration, check the values found during deskew for example.
9. All the data comparison for read DQS centering occurs in the general interconnect, so it canbe useful to pull in the debug data in the hardware debugger and take a look at what the datalooks like coming back as taps are adjusted, see the figure below. The screen capture shownis from simulation with a small burst of five reads. Look at dbg_rd_data,dbg_rd_data_cmp, and dbg_rd_valid.
10. Using the Vivado Hardware Manager and while running the Memory IP Example Design withDebug Signals enabled, set the Read Centering trigger to (cal_r*_status[22] = R(rising edge) && dbg_rd_valid = 1’b0 && cal_seq_cnt[2:0] = 3’b0). To vieweach byte, add an additional trigger on dbg_cmp_byte and set to the byte of interest. Thefollowing simulation example shows how the debug signals should behave during successfulRead DQS Centering.
Figure 75: RTL Debug Signals during Read DQS Centering (No Error)
Write Calibration OverviewNote: The calibration step is only enabled for the first rank in a multi-rank system.
The DRAM requires the write DQS to be center-aligned with the DQ to ensure maximum writemargin. The DQS and DQ ODELAY are used to fine tune the 90° phase alignment to ensuremaximum margin at the DRAM.
Appendix B: Debugging
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A simple clock pattern of 10101010 is used initially because the write latency has not yet beendetermined. Due to fly-by routing on the PCB/DIMM module, the command to data timing isunknown until the next stage of calibration. When issuing a write to the DRAM, the DQS andDQ toggles for four clock cycles before and four clock cycles after the expected write latency.This is used to ensure the data is written into the DRAM even if the command-to-write datarelationship is still unknown. Write calibration is divided into three phases.
1. Write DQ Per-Bit Deskew
2. Write DBI bit Deskew
3. Write DQS to DQ/DBI Centering
Debugging Write Per-Bit DQ Deskew Failures
Calibration Overview
Initially all the DQ bits associated with a DQS strobe have the same ODELAY setting based onthe write leveling results, but the ODELAY for each bit might need to be adjusted to account forskew between bits. The figure below shows an example of the initial timing relationship betweena write DQS and DQ.
Figure 76: Initial Write DQS and DQ with Skew between Bits
Write DQS
DQ0
DQ1
DQn
X24730-101420
1. Turn off DBI/DM on the write path and DBI on the read path (MRS setting in the DRAM andfabric switch).
2. Write pattern 10101010 into the DRAM memory and read back. Here, MSB is the last bit ofa burst and LSB is the first bit of a burst. The data read back on some DQ bits are 10101010while other DQ bits might be 01010101 due to skew between the DQ bits.
3. Increment DQS ODELAY one fine tap at a time (maximum shift limited to 90⁰) for findingcommon valid window (15 taps wide) for all DQ bits. This step is carried out in parallel for allDQS. Once valid window is detected for a DQ bit, increment ODELAY for that DQ bit alongwith DQS until common valid window is detected for the remaining DQ bits (see figurebelow). At the end of this step, common valid window detection status of write DQS is savedas BRAM_WRDQDBI_STG1_BYTE_STATUS* and DQ bits for which valid window is detectedis saved as BRAM_WRDQDBI_STG1_BIT_STATUS*.
Appendix B: Debugging
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Figure 77: Increment Write DQS ODELAY until All Bits Captured with Correct Pattern
Write DQS
DQ0
DQ1
DQn
ODELAY shift for DQSX24727-101420
4. If a DQS is unable to detect common valid window before reaching maximum shift of 90⁰ (seefigure below), ODELAY for DQS and DQ (bits for which valid window is detected) arereverted back to point where last valid window is detected for a DQ bit. At the end of thisstep, DQS ODELAY value is saved as BRAM_WRDQDBI_STG2_DQS_ODLY_BYTE* and DQbits ODELAY value is saved as BRAM_WRDQDBI_STG2_DQ_ODLY_BIT*.
Figure 78: Write DQS ODELAY Reached 90⁰ Limit While Searching for Correct Patternfor All DQ Bits
Write DQS
DQ0
DQ1
DQn
ODELAY shift for DQS reached 90º Unable to detect
valid windowX24740-101420
5. ODELAY value of DQS for which common valid window is detected for at least one of theDQ bits is reverted back by minimum window width of 15 taps. Increment DQ ODELAY onetap at a time (maximum shift limited to 180⁰) for detecting common valid window onremaining DQ bits (see figure below). At the end of this step, DQS ODELAY value is saved asBRAM_WRDQDBI_STG1_DQS_DELAY_BYTE* and DQ bits ODELAY value is saved asBRAM_WRDQDBI_STG3_DQ_ODLY_BIT*.
Appendix B: Debugging
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Figure 79: Increment DQ ODELAY until All Bits Captured with Correct Pattern
Write DQS
DQ0
DQ1
DQn
ODELAY shift for DQ
X24726-101420
6. Increment each DQ ODELAY using step size of 10 taps until each bit fails to return theexpected data pattern. Once completed, decrement each DQ ODELAY using step size of 10taps. At the end of this step, DQ ODELAY value is saved asBRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT*.
7. Increment each DQ ODELAY by one fine tap at a time until each bit fails to return theexpected data pattern (the data is edge aligned with the write DQS, see figure below). At theend of this step, DQ ODELAY value is saved asBRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT*.
Figure 80: DQ Per-Bit Write Deskew
Write DQS
DQ0
DQ1
DQn
ODELAY shift for DQ
ODELAY shift for DQ
X24717-101420
Debug
To determine the status of Write Per-Bit DQ Deskew Calibration, click the WRITE_DQ_DBI_CALstage under the Status window and view the results within the Memory IP Properties window.The message displayed in the Memory IP Properties identifies how the stage failed, or notes if itpassed successfully. Check CAL_ERROR for confirming whether the calibration failure is in WritePer-Bit DQ Deskew or Write Per-Bit DBI Deskew or Write DQS to DQ/DBI Centering stage.
Appendix B: Debugging
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Figure 81: Memory IP XSDB Debug GUI Example – Write DQ Per-Bit DQ Deskew
CAL_ERROR Decode for Write Per-Bit DQ Deskew Calibration
The status of Write Per-Bit DQ Deskew can also be determined by decoding the CAL_ERRORresult according to the table below. Execute the Tcl commands noted in the Manually Analyzingthe XSDB Output section to generate the XSDB output containing the signal results.
Table 111: CAL_ERROR Decode for Write Per-Bit DQ Deskew Calibration
Error Code Description Recommended Debug Step
21No valid data found for a given bit in the byte byincrementing DQS ODELAY first and then DQODELAY.
Check the alignment of DQS to DQ during awrite burst with a scope on the PCB. Check theDQS-to-CK alignment. Check the WRLVL fields inXSDB for a given byte.
22Noise region not found for a given bit in the byteby incrementing DQ ODELAY using step size of10 taps.
Check for a mapping issue. This usually implies adelay is not moving when it should. Check theconnections going to the XPHY and ensure thecorrect RIU is selected based on the byte beingadjusted.
23Noise region not found for a given bit in the byteby incrementing DQ ODELAY using step size of 1tap.
Check for a mapping issue. This usually implies adelay is not moving when it should. Check theconnections going to the XPHY and ensure thecorrect RIU is selected based on the byte beingadjusted.
Appendix B: Debugging
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XSDB Registers of Interest during DQ Per-Bit DQ Deskew Calibration
The table shows the XSDB registers and values adjusted or used during the Write Per-Bit DQDeskew stage of calibration. The values can be analyzed in both successful and failingcalibrations to determine the resultant values and the consistency in results across resets. Thesevalues can be found within the Memory IP core properties in the Hardware Manager or byexecuting the Tcl commands noted in the Manually Analyzing the XSDB Output section.
Table 112: XSDB Registers of Interest during DQ Per-Bit DQ Deskew Calibration
XSDB Reg Usage Signal Description
BRAM_WRDQDBI_STG1_DQS_DELAY_BYTE* One per byteDQS ODELAY value required to placeDQS into the byte write data validwindow during write DQ per-bitdeskew.
BRAM_WRDQDBI_STG1_BYTE_STATUS* – Write valid window detection status atbyte level.
BRAM_WRDQDBI_STG1_BIT_STATUS_BYTE* One per byte Write valid window detection status atbit level.
BRAM_WRDQDBI_STG2_DQS_ODLY_BYTE* One per byteDQS ODELAY value after reverting DQSto the location where last write validwindow is detected for a DQ bit in abyte.
BRAM_WRDQDBI_STG2_DQ_ODLY_BIT* One per bitDQ ODELAY value after reverting DQbits to the point where last write validwindow is detected for a DQ bit in abyte.
BRAM_WRDQDBI_STG3_DQ_ODLY_BIT* One per bitDQ ODELAY value after detecting writevalid window by incrementing DQODELAY.
BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT* One per bitDQ ODELAY value when invalid writedata is detected by incrementingODELAY using step size of 10 taps.
BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT* One per bitDQ ODELAY value when invalid writedata is detected by incrementingODELAY using step size of 1 tap.
This is a sample of the results for the Write Per-Bit DQ Deskew XSDB debug signals:
BRAM_WRDQDBI_STG1_DQS_DELAY_BYTE0 int true 31BRAM_WRDQDBI_STG1_DQS_DELAY_BYTE1 int true 63BRAM_WRDQDBI_STG1_DQS_DELAY_BYTE2 int true 105BRAM_WRDQDBI_STG1_DQS_DELAY_BYTE3 int true 93BRAM_WRDQDBI_STG1_DQS_DELAY_BYTE4 int true 59BRAM_WRDQDBI_STG1_DQS_DELAY_BYTE5 int true 28BRAM_WRDQDBI_STG1_DQS_DELAY_BYTE6 int true 55BRAM_WRDQDBI_STG1_DQS_DELAY_BYTE7 int true 99BRAM_WRDQDBI_STG1_BYTE_STATUS_00 int true 255BRAM_WRDQDBI_STG1_BYTE_STATUS_01 int true 255BRAM_WRDQDBI_STG1_BIT_STATUS_BYTE0 int true 255BRAM_WRDQDBI_STG1_BIT_STATUS_BYTE1 int true 255
Appendix B: Debugging
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BRAM_WRDQDBI_STG1_BIT_STATUS_BYTE2 int true 255BRAM_WRDQDBI_STG1_BIT_STATUS_BYTE3 int true 255BRAM_WRDQDBI_STG1_BIT_STATUS_BYTE4 int true 0BRAM_WRDQDBI_STG1_BIT_STATUS_BYTE5 int true 0BRAM_WRDQDBI_STG1_BIT_STATUS_BYTE6 int true 0BRAM_WRDQDBI_STG1_BIT_STATUS_BYTE7 int true 0BRAM_WRDQDBI_STG2_DQS_ODLY_BYTE0 int true 45BRAM_WRDQDBI_STG2_DQS_ODLY_BYTE1 int true 77BRAM_WRDQDBI_STG2_DQS_ODLY_BYTE2 int true 119BRAM_WRDQDBI_STG2_DQS_ODLY_BYTE3 int true 107BRAM_WRDQDBI_STG2_DQS_ODLY_BYTE4 int true 73BRAM_WRDQDBI_STG2_DQS_ODLY_BYTE5 int true 42BRAM_WRDQDBI_STG2_DQS_ODLY_BYTE6 int true 69BRAM_WRDQDBI_STG2_DQS_ODLY_BYTE7 int true 113BRAM_WRDQDBI_STG2_DQ_ODLY_BIT00 int true 31BRAM_WRDQDBI_STG2_DQ_ODLY_BIT01 int true 31BRAM_WRDQDBI_STG2_DQ_ODLY_BIT02 int true 31BRAM_WRDQDBI_STG2_DQ_ODLY_BIT03 int true 31BRAM_WRDQDBI_STG2_DQ_ODLY_BIT04 int true 31BRAM_WRDQDBI_STG2_DQ_ODLY_BIT05 int true 31BRAM_WRDQDBI_STG2_DQ_ODLY_BIT06 int true 31BRAM_WRDQDBI_STG2_DQ_ODLY_BIT07 int true 31BRAM_WRDQDBI_STG2_DQ_ODLY_BIT08 int true 63BRAM_WRDQDBI_STG2_DQ_ODLY_BIT09 int true 63BRAM_WRDQDBI_STG2_DQ_ODLY_BIT10 int true 63BRAM_WRDQDBI_STG2_DQ_ODLY_BIT11 int true 63BRAM_WRDQDBI_STG2_DQ_ODLY_BIT12 int true 63BRAM_WRDQDBI_STG2_DQ_ODLY_BIT13 int true 63BRAM_WRDQDBI_STG2_DQ_ODLY_BIT14 int true 63BRAM_WRDQDBI_STG2_DQ_ODLY_BIT15 int true 63BRAM_WRDQDBI_STG2_DQ_ODLY_BIT16 int true 105BRAM_WRDQDBI_STG2_DQ_ODLY_BIT17 int true 105BRAM_WRDQDBI_STG2_DQ_ODLY_BIT18 int true 105BRAM_WRDQDBI_STG2_DQ_ODLY_BIT19 int true 105BRAM_WRDQDBI_STG2_DQ_ODLY_BIT20 int true 105BRAM_WRDQDBI_STG2_DQ_ODLY_BIT21 int true 105BRAM_WRDQDBI_STG2_DQ_ODLY_BIT22 int true 105BRAM_WRDQDBI_STG2_DQ_ODLY_BIT23 int true 105BRAM_WRDQDBI_STG2_DQ_ODLY_BIT24 int true 93BRAM_WRDQDBI_STG2_DQ_ODLY_BIT25 int true 93BRAM_WRDQDBI_STG2_DQ_ODLY_BIT26 int true 93BRAM_WRDQDBI_STG2_DQ_ODLY_BIT27 int true 93BRAM_WRDQDBI_STG2_DQ_ODLY_BIT28 int true 93BRAM_WRDQDBI_STG2_DQ_ODLY_BIT29 int true 93BRAM_WRDQDBI_STG2_DQ_ODLY_BIT30 int true 93BRAM_WRDQDBI_STG2_DQ_ODLY_BIT31 int true 93BRAM_WRDQDBI_STG2_DQ_ODLY_BIT32 int true 59BRAM_WRDQDBI_STG2_DQ_ODLY_BIT33 int true 59BRAM_WRDQDBI_STG2_DQ_ODLY_BIT34 int true 59BRAM_WRDQDBI_STG2_DQ_ODLY_BIT35 int true 59BRAM_WRDQDBI_STG2_DQ_ODLY_BIT36 int true 59BRAM_WRDQDBI_STG2_DQ_ODLY_BIT37 int true 59BRAM_WRDQDBI_STG2_DQ_ODLY_BIT38 int true 59BRAM_WRDQDBI_STG2_DQ_ODLY_BIT39 int true 59BRAM_WRDQDBI_STG2_DQ_ODLY_BIT40 int true 28BRAM_WRDQDBI_STG2_DQ_ODLY_BIT41 int true 28BRAM_WRDQDBI_STG2_DQ_ODLY_BIT42 int true 28BRAM_WRDQDBI_STG2_DQ_ODLY_BIT43 int true 28BRAM_WRDQDBI_STG2_DQ_ODLY_BIT44 int true 28BRAM_WRDQDBI_STG2_DQ_ODLY_BIT45 int true 28BRAM_WRDQDBI_STG2_DQ_ODLY_BIT46 int true 28BRAM_WRDQDBI_STG2_DQ_ODLY_BIT47 int true 28BRAM_WRDQDBI_STG2_DQ_ODLY_BIT48 int true 55
Appendix B: Debugging
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BRAM_WRDQDBI_STG2_DQ_ODLY_BIT49 int true 55BRAM_WRDQDBI_STG2_DQ_ODLY_BIT50 int true 55BRAM_WRDQDBI_STG2_DQ_ODLY_BIT51 int true 55BRAM_WRDQDBI_STG2_DQ_ODLY_BIT52 int true 55BRAM_WRDQDBI_STG2_DQ_ODLY_BIT53 int true 55BRAM_WRDQDBI_STG2_DQ_ODLY_BIT54 int true 55BRAM_WRDQDBI_STG2_DQ_ODLY_BIT55 int true 55BRAM_WRDQDBI_STG2_DQ_ODLY_BIT56 int true 99BRAM_WRDQDBI_STG2_DQ_ODLY_BIT57 int true 99BRAM_WRDQDBI_STG2_DQ_ODLY_BIT58 int true 99BRAM_WRDQDBI_STG2_DQ_ODLY_BIT59 int true 99BRAM_WRDQDBI_STG2_DQ_ODLY_BIT60 int true 99BRAM_WRDQDBI_STG2_DQ_ODLY_BIT61 int true 99BRAM_WRDQDBI_STG2_DQ_ODLY_BIT62 int true 99BRAM_WRDQDBI_STG2_DQ_ODLY_BIT63 int true 99BRAM_WRDQDBI_STG3_DQ_ODLY_BIT00 int true 31BRAM_WRDQDBI_STG3_DQ_ODLY_BIT01 int true 31BRAM_WRDQDBI_STG3_DQ_ODLY_BIT02 int true 31BRAM_WRDQDBI_STG3_DQ_ODLY_BIT03 int true 31BRAM_WRDQDBI_STG3_DQ_ODLY_BIT04 int true 31BRAM_WRDQDBI_STG3_DQ_ODLY_BIT05 int true 31BRAM_WRDQDBI_STG3_DQ_ODLY_BIT06 int true 31BRAM_WRDQDBI_STG3_DQ_ODLY_BIT07 int true 31BRAM_WRDQDBI_STG3_DQ_ODLY_BIT08 int true 63BRAM_WRDQDBI_STG3_DQ_ODLY_BIT09 int true 63BRAM_WRDQDBI_STG3_DQ_ODLY_BIT10 int true 63BRAM_WRDQDBI_STG3_DQ_ODLY_BIT11 int true 63BRAM_WRDQDBI_STG3_DQ_ODLY_BIT12 int true 63BRAM_WRDQDBI_STG3_DQ_ODLY_BIT13 int true 63BRAM_WRDQDBI_STG3_DQ_ODLY_BIT14 int true 63BRAM_WRDQDBI_STG3_DQ_ODLY_BIT15 int true 63BRAM_WRDQDBI_STG3_DQ_ODLY_BIT16 int true 105BRAM_WRDQDBI_STG3_DQ_ODLY_BIT17 int true 105BRAM_WRDQDBI_STG3_DQ_ODLY_BIT18 int true 105BRAM_WRDQDBI_STG3_DQ_ODLY_BIT19 int true 105BRAM_WRDQDBI_STG3_DQ_ODLY_BIT20 int true 105BRAM_WRDQDBI_STG3_DQ_ODLY_BIT21 int true 105BRAM_WRDQDBI_STG3_DQ_ODLY_BIT22 int true 105BRAM_WRDQDBI_STG3_DQ_ODLY_BIT23 int true 105BRAM_WRDQDBI_STG3_DQ_ODLY_BIT24 int true 93BRAM_WRDQDBI_STG3_DQ_ODLY_BIT25 int true 93BRAM_WRDQDBI_STG3_DQ_ODLY_BIT26 int true 93BRAM_WRDQDBI_STG3_DQ_ODLY_BIT27 int true 93BRAM_WRDQDBI_STG3_DQ_ODLY_BIT28 int true 93BRAM_WRDQDBI_STG3_DQ_ODLY_BIT29 int true 93BRAM_WRDQDBI_STG3_DQ_ODLY_BIT30 int true 93BRAM_WRDQDBI_STG3_DQ_ODLY_BIT31 int true 93BRAM_WRDQDBI_STG3_DQ_ODLY_BIT32 int true 59BRAM_WRDQDBI_STG3_DQ_ODLY_BIT33 int true 59BRAM_WRDQDBI_STG3_DQ_ODLY_BIT34 int true 59BRAM_WRDQDBI_STG3_DQ_ODLY_BIT35 int true 59BRAM_WRDQDBI_STG3_DQ_ODLY_BIT36 int true 59BRAM_WRDQDBI_STG3_DQ_ODLY_BIT37 int true 59BRAM_WRDQDBI_STG3_DQ_ODLY_BIT38 int true 59BRAM_WRDQDBI_STG3_DQ_ODLY_BIT39 int true 59BRAM_WRDQDBI_STG3_DQ_ODLY_BIT40 int true 28BRAM_WRDQDBI_STG3_DQ_ODLY_BIT41 int true 28BRAM_WRDQDBI_STG3_DQ_ODLY_BIT42 int true 28BRAM_WRDQDBI_STG3_DQ_ODLY_BIT43 int true 28BRAM_WRDQDBI_STG3_DQ_ODLY_BIT44 int true 28BRAM_WRDQDBI_STG3_DQ_ODLY_BIT45 int true 28BRAM_WRDQDBI_STG3_DQ_ODLY_BIT46 int true 28BRAM_WRDQDBI_STG3_DQ_ODLY_BIT47 int true 28
Appendix B: Debugging
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BRAM_WRDQDBI_STG3_DQ_ODLY_BIT48 int true 55BRAM_WRDQDBI_STG3_DQ_ODLY_BIT49 int true 55BRAM_WRDQDBI_STG3_DQ_ODLY_BIT50 int true 55BRAM_WRDQDBI_STG3_DQ_ODLY_BIT51 int true 55BRAM_WRDQDBI_STG3_DQ_ODLY_BIT52 int true 55BRAM_WRDQDBI_STG3_DQ_ODLY_BIT53 int true 55BRAM_WRDQDBI_STG3_DQ_ODLY_BIT54 int true 55BRAM_WRDQDBI_STG3_DQ_ODLY_BIT55 int true 55BRAM_WRDQDBI_STG3_DQ_ODLY_BIT56 int true 99BRAM_WRDQDBI_STG3_DQ_ODLY_BIT57 int true 99BRAM_WRDQDBI_STG3_DQ_ODLY_BIT58 int true 99BRAM_WRDQDBI_STG3_DQ_ODLY_BIT59 int true 99BRAM_WRDQDBI_STG3_DQ_ODLY_BIT60 int true 99BRAM_WRDQDBI_STG3_DQ_ODLY_BIT61 int true 99BRAM_WRDQDBI_STG3_DQ_ODLY_BIT62 int true 99BRAM_WRDQDBI_STG3_DQ_ODLY_BIT63 int true 99BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT00 int true 91BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT01 int true 101BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT02 int true 91BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT03 int true 101BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT04 int true 101BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT05 int true 111BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT06 int true 101BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT07 int true 101BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT08 int true 123BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT09 int true 123BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT10 int true 123BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT11 int true 133BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT12 int true 123BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT13 int true 133BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT14 int true 123BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT15 int true 123BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT16 int true 175BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT17 int true 175BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT18 int true 175BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT19 int true 185BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT20 int true 165BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT21 int true 175BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT22 int true 175BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT23 int true 185BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT24 int true 163BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT25 int true 163BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT26 int true 163BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT27 int true 173BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT28 int true 163BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT29 int true 163BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT30 int true 173BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT31 int true 173BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT32 int true 129BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT33 int true 129BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT34 int true 129BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT35 int true 129BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT36 int true 129BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT37 int true 139BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT38 int true 139BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT39 int true 139BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT40 int true 88BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT41 int true 88BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT42 int true 88BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT43 int true 98BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT44 int true 88BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT45 int true 98BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT46 int true 98
Appendix B: Debugging
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BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT47 int true 98BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT48 int true 135BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT49 int true 125BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT50 int true 125BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT51 int true 125BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT52 int true 125BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT53 int true 135BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT54 int true 135BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT55 int true 135BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT56 int true 159BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT57 int true 169BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT58 int true 169BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT59 int true 179BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT60 int true 169BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT61 int true 179BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT62 int true 169BRAM_WRDQDBI_DESKEW_DQ_ODLY_FCRSE_BIT63 int true 179BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT00 int true 97BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT01 int true 105BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT02 int true 99BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT03 int true 109BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT04 int true 108BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT05 int true 114BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT06 int true 108BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT07 int true 108BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT08 int true 130BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT09 int true 130BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT10 int true 131BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT11 int true 136BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT12 int true 131BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT13 int true 139BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT14 int true 131BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT15 int true 124BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT16 int true 179BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT17 int true 180BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT18 int true 179BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT19 int true 189BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT20 int true 171BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT21 int true 184BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT22 int true 182BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT23 int true 187BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT24 int true 170BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT25 int true 171BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT26 int true 166BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT27 int true 176BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT28 int true 170BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT29 int true 169BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT30 int true 174BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT31 int true 176BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT32 int true 132BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT33 int true 131BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT34 int true 129BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT35 int true 133BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT36 int true 129BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT37 int true 145BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT38 int true 138BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT39 int true 138BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT40 int true 94BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT41 int true 93BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT42 int true 93BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT43 int true 104BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT44 int true 91BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT45 int true 102
Appendix B: Debugging
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BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT46 int true 98BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT47 int true 101BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT48 int true 136BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT49 int true 134BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT50 int true 130BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT51 int true 134BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT52 int true 132BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT53 int true 138BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT54 int true 138BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT55 int true 141BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT56 int true 163BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT57 int true 178BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT58 int true 178BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT59 int true 181BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT60 int true 177BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT61 int true 182BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT62 int true 178BRAM_WRDQDBI_DESKEW_DQ_ODLY_BIT63 int true 182
Related Information
Manually Analyzing the XSDB Output
Expected Results
Hardware measurements should show the write DQ bits are deskewed at the end of thesecalibration stages.
• Determine if any bytes completed successfully. The write calibration algorithm steps througheach DQS byte group detecting the capture edges.
• If the incorrect data pattern is detected, determine if the error is due to the write access orthe read access.
Hardware Measurements
1. Probe the DQ bit alignment at the memory during writes. Trigger at the start(cal_r*_status[26] = R for Rising Edge) and again at the end of per bit deskew(cal_r*_status[27] = R for Rising Edge) to view the starting and ending alignments. Tolook at each byte, add a trigger on the byte using dbg_cmp_byte.
2. Using the Vivado Hardware Manager and while running the Memory IP Example Design withDebug Signals enabled, set the trigger (cal_r*_status[26] = R for Rising Edge). Thefollowing simulation examples show how the debug signals should behave during successfulWrite Per-Bit Deskew:
Appendix B: Debugging
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Calibration OverviewNote: The calibration step is only enabled for the first rank in a multi-rank system.
Initially DBI and DQS strobe have the same ODELAY setting based on the write leveling results,but ODELAY values of DQS are modified during write DQ per-deskew. A similar mechanism asthe write DQ per-bit deskew is run but DBI pin is deskewed instead in relation to DQS. Thefigure below shows an example of the initial timing relationship between a write DQS and DBI.
1. Turn on DBI on the write path, turn off DM on the write path, and DBI on the read path (MRSsetting in the DRAM and fabric switch).
2. Write pattern 10101010 into the DRAM memory (extending the data pattern before/afterthe burst because write latency calibration has not yet been performed) and read back thedata. The data read back on some DQ bytes might be different from the expected patternFF00FF00_FF00FF00 due to skew between DBI and DQS.
Appendix B: Debugging
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Figure 85: Initial Write DQS and DBI with Skew between Them
DBI_n
Write DQS
FFDQ byte
FFData written in memory array 00 FF 00 FF 00 FF 00
X24729-101420
3. Increment DQS ODELAY by one fine tap at a time (maximum shift limited to 90⁰) for findingvalid window (15 taps wide) for the data read on DQ byte (see figure below). This step iscarried out in parallel for all DQS. At the end of this step, valid window detection status issaved as BRAM_WRDQDBI_STG4_BYTE_STATUS*.
4. If a DQS is unable to detect valid window before reaching maximum shift of 90⁰ (see figurebelow), ODELAY for that DQS is reverted to initial value. At the end of this step, DQSODELAY value is saved as BRAM_WRDQDBI_STG5_DQS_ODLY_BYTE*.
Figure 87: Write DQS ODELAY Reached 90⁰ Limit While Searching for Correct Patternfor DQ Byte
DBI_n
Write DQS
FFDQ byte
FFData written in memory array 00 FF 00 FF 00 FF FF
ODELAY shift for DQS reached 90°
X24741-101420
5. ODELAY value of DQS for which valid window is detected is reverted back by minimumwindow width of 15 taps. Increment DBI ODELAY by one fine tap at a time (maximum shiftlimited to 180⁰) for detecting valid window of remaining DQS strobe (see figure below). Atthe end of this step, DQS ODELAY value is saved asBRAM_WRDQDBI_STG4_DQS_DELAY_BYTE* and DBI ODELAY value is saved asBRAM_WRDQDBI_STG6_DBI_ODLY_BYTE*.
Appendix B: Debugging
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00Data written in memory array FF 00 FF 00 FF 00 FF
ODELAY shift for DBIX24725-101420
6. Increment each DBI ODELAY using step size of 10 taps until DQ byte fails to return theexpected data pattern. Once completed, decrement each DBI ODELAY by step size of 10taps. At the end of this stage, DBI ODELAY values are saved asBRAM_WRDQDBI_DESKEW_DBI_ODLY_FCRSE_BYTE*.
7. Increment each DBI ODELAY by one fine tap at a time until DQ byte fails to return theexpected data pattern (DBI is edge aligned with write DQS, see figure below). At the end ofthis step, DBI ODELAY values are stored as BRAM_WRDQDBI_DESKEW_DBI_ODLY_BYTE*.
Appendix B: Debugging
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XXData written in memory array XX XX XX XX XX XX XX
ODELAY shift for DBI
X24739-101420
Debug
To determine the status of Write Per-Bit DBI Deskew Calibration, click the WRITE_DQ_DBI_CALstage under the Status window and view the results within the Memory IP Properties window.The message displayed in the Memory IP Properties identifies how the stage failed, or notes if itpassed successfully. Check CAL_ERROR for confirming whether the calibration failure is in WritePer-Bit DQ Deskew, Write Per-Bit DBI Deskew, or Write DQS to DQ/DBI Centering stage.
Appendix B: Debugging
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Figure 90: Memory IP XSDB Debug GUI Example – Write Per-Bit DBI Deskew
CAL_ERROR Decode for Write Per-Bit DBI Deskew Calibration
The status of Write Per-Bit DBI Deskew can also be determined by decoding the CAL_ERRORresult according to the table below. Execute the Tcl commands noted in the Manually Analyzingthe XSDB Output section to generate the XSDB output containing the signal results.
Table 113: CAL_ERROR Decode for Write Per-Bit DBI Deskew Calibration
Error Code Description Recommended Debug Step
24No valid data found for a given bit in the byte byincrementing DQS ODELAY first and then DBIODELAY.
Check the alignment of DQS to DBI during awrite burst with a scope on the PCB. Check theDQS-to-CK alignment. Check the WRLVL fields inXSDB for a given byte.
25Noise region not found for a given bit in the byteby incrementing DBI ODELAY using step size of10 taps.
Check for a mapping issue. This usually implies adelay is not moving when it should. Check theconnections going to the XPHY and ensure thecorrect RIU is selected based on the byte beingadjusted.
26
Noise region not found for a given bit in the byteby incrementing DBI ODELAY using step size of 1tap.
Check for a mapping issue. This usually implies adelay is not moving when it should. Check theconnections going to the XPHY and ensure thecorrect RIU is selected based on the byte beingadjusted.
Appendix B: Debugging
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XSDB Registers of Interest during Write Per-Bit DBI Deskew Calibration
The following table shows the XSDB registers and values adjusted or used during the Write Per-Bit DBI Deskew stage of calibration. The values can be analyzed in both successful and failingcalibrations to determine the resultant values and the consistency in results across resets. Thesevalues can be found within the Memory IP core properties in the Hardware Manager or byexecuting the Tcl commands noted in the Manually Analyzing the XSDB Output section.
Table 114: XSDB Registers of Interest during Write Per-Bit DBI Deskew Calibration
BRAM_WRDQDBI_STG4_DQS_DELAY_BYTE* One per byteDQS ODELAY value required to placeDQS into the byte write data validwindow during write DBI bit deskew.
BRAM_WRDQDBI_STG5_DQS_ODLY_BYTE* One per byteDQS ODELAY value after reverting DQSto initial value if byte write valid data isnot detected.
BRAM_WRDQDBI_STG6_DBI_ODLY_BYTE* One per byteDBI ODELAY value after detecting writevalid window by incrementing DBIODELAY.
BRAM_WRDQDBI_DESKEW_DBI_ODLY_FCRSE_BYTE* One per byteDBI ODELAY value when invalid writedata is detected by incrementingODELAY using step size of 10 taps.
BRAM_WRDQDBI_DESKEW_DBI_ODLY_BYTE* One per byteDBI ODELAY value when invalid writedata is detected by incrementingODELAY using step size of 1 tap.
This is a sample of the results for the Write Per-Bit DBI Deskew XSDB debug signals:
BRAM_WRDQDBI_STG4_BYTE_STATUS_00 int true 255BRAM_WRDQDBI_STG4_BYTE_STATUS_01 int true 255BRAM_WRDQDBI_STG4_DQS_DELAY_BYTE0 int true 31BRAM_WRDQDBI_STG4_DQS_DELAY_BYTE1 int true 63BRAM_WRDQDBI_STG4_DQS_DELAY_BYTE2 int true 105BRAM_WRDQDBI_STG4_DQS_DELAY_BYTE3 int true 93BRAM_WRDQDBI_STG4_DQS_DELAY_BYTE4 int true 59BRAM_WRDQDBI_STG4_DQS_DELAY_BYTE5 int true 28BRAM_WRDQDBI_STG4_DQS_DELAY_BYTE6 int true 55BRAM_WRDQDBI_STG4_DQS_DELAY_BYTE7 int true 99BRAM_WRDQDBI_STG5_DQS_ODLY_BYTE0 int true 45BRAM_WRDQDBI_STG5_DQS_ODLY_BYTE1 int true 77BRAM_WRDQDBI_STG5_DQS_ODLY_BYTE2 int true 119BRAM_WRDQDBI_STG5_DQS_ODLY_BYTE3 int true 107BRAM_WRDQDBI_STG5_DQS_ODLY_BYTE4 int true 73BRAM_WRDQDBI_STG5_DQS_ODLY_BYTE5 int true 42BRAM_WRDQDBI_STG5_DQS_ODLY_BYTE6 int true 69BRAM_WRDQDBI_STG5_DQS_ODLY_BYTE7 int true 113BRAM_WRDQDBI_STG6_DBI_ODLY_BYTE0 int true 31BRAM_WRDQDBI_STG6_DBI_ODLY_BYTE1 int true 63BRAM_WRDQDBI_STG6_DBI_ODLY_BYTE2 int true 105
Appendix B: Debugging
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BRAM_WRDQDBI_STG6_DBI_ODLY_BYTE3 int true 93BRAM_WRDQDBI_STG6_DBI_ODLY_BYTE4 int true 59BRAM_WRDQDBI_STG6_DBI_ODLY_BYTE5 int true 28BRAM_WRDQDBI_STG6_DBI_ODLY_BYTE6 int true 55BRAM_WRDQDBI_STG6_DBI_ODLY_BYTE7 int true 99BRAM_WRDQDBI_DESKEW_DBI_ODLY_FCRSE_BYTE0 int true 101BRAM_WRDQDBI_DESKEW_DBI_ODLY_FCRSE_BYTE1 int true 133BRAM_WRDQDBI_DESKEW_DBI_ODLY_FCRSE_BYTE2 int true 185BRAM_WRDQDBI_DESKEW_DBI_ODLY_FCRSE_BYTE3 int true 173BRAM_WRDQDBI_DESKEW_DBI_ODLY_FCRSE_BYTE4 int true 129BRAM_WRDQDBI_DESKEW_DBI_ODLY_FCRSE_BYTE5 int true 98BRAM_WRDQDBI_DESKEW_DBI_ODLY_FCRSE_BYTE6 int true 135BRAM_WRDQDBI_DESKEW_DBI_ODLY_FCRSE_BYTE7 int true 169BRAM_WRDQDBI_DESKEW_DBI_ODLY_BYTE0 int true 105BRAM_WRDQDBI_DESKEW_DBI_ODLY_BYTE1 int true 137BRAM_WRDQDBI_DESKEW_DBI_ODLY_BYTE2 int true 185BRAM_WRDQDBI_DESKEW_DBI_ODLY_BYTE3 int true 175BRAM_WRDQDBI_DESKEW_DBI_ODLY_BYTE4 int true 137BRAM_WRDQDBI_DESKEW_DBI_ODLY_BYTE5 int true 101BRAM_WRDQDBI_DESKEW_DBI_ODLY_BYTE6 int true 141BRAM_WRDQDBI_DESKEW_DBI_ODLY_BYTE7 int true 171
Related Information
Manually Analyzing the XSDB Output
Expected Results
Hardware measurements should show the write DBI bits are deskewed at the end of thesecalibration stages.
• Determine if any bytes completed successfully. The write calibration algorithm steps througheach DQS byte group detecting the capture edges.
• If the incorrect data pattern is detected, determine if the error is due to the write access orthe read access.
Hardware Measurements
1. Probe the DBI bit alignment at the memory during writes. Trigger at the start(cal_r*_status[26] = R for Rising Edge) and again at the end of per bit deskew(cal_r*_status[27] = R for Rising Edge) to view the starting and ending alignments. Tolook at each byte, add a trigger on the byte using dbg_cmp_byte.
2. Using the Vivado Hardware Manager and while running the Memory IP Example Design withDebug Signals enabled, set the trigger (cal_r*_status[26] = R for Rising Edge). Thefollowing simulation examples show how the debug signals should behave during successfulWrite Per-Bit DBI Deskew:
Appendix B: Debugging
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After write DQ per-bit and DBI bit deskew, the next step is to determine the relative center ofthe DQS in the write data eye.
1. Left margin of write data for a DQS is calculated as the largest value among DQ bits delayand DBI delay calculated during deskew. ODELAY of DQ bits and DBI is decremented bystep size equal to the left margin. At the end of this step, DQ ODELAY value is saved asBRAM_WRDQDBI_LEFT_EDGE_DQ_BIT* and final ODELAY values for DBI are saved asBRAM_WRDQDBI_LEFT_EDGE_DBI_BYTE*.
2. Issue a set of write and read bursts with the data pattern 10101010 and check the read data.Just as in write DQ per-bit deskew when issuing a write to the DRAM, the DQS and DQtoggles for eight clock cycles before and after the expected write latency. This is used toensure the data is written into the DRAM even if the command-to-write data relationship isstill unknown.
3. Find the right edge of the write data window by incrementing DQS ODELAY by step size of10 taps until the data changes from the expected data pattern 10101010. Once completed,decrement each DQS ODELAY by step size of 10 taps. At the end of this stage, right marginvalues are saved as BRAM_WRDQDBI_RIGHT_MARGIN_FCRSE_BYTE*.
4. Increment each DQS ODELAY by one fine tap at a time until the data changes from theexpected data pattern 10101010 (see figure below). At the end of this step, right marginvalues are saved as BRAM_WRDQDBI_RIGHT_MARGIN_BYTE*.
Figure 93: Write DQS to DQ/DBI Centering – Right Margin
0DQ[n] F 0 F
Write DQS
Write DQS Delayed
X24742-101420
Appendix B: Debugging
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The final ODELAY tap settings for DQS, DQ, and DBI are indicated byBRAM_WRDQDBI_ODLY_DQS_FINAL_BYTE*, BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT*,and BRAM_WRDQDBI_ODLY_DBI_FINAL_BYTE*, respectively.
Debug
To determine the status of Write DQS to DQ/DBI Centering Calibration, click theWRITE_DQ_DBI_CAL stage under the Status window and view the results within the Memory IPProperties window. The message displayed in the Memory IP Properties identifies how the stagefailed, or notes if it passed successfully. Check CAL_ERROR for confirming whether thecalibration failure is in Write DQ Per-Bit Deskew, Write DBI Bit Deskew, or Write DQS toDQ/DBI Centering stage.
Appendix B: Debugging
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Figure 94: Memory IP XSDB Debug GUI Example – Write DQS to DQ/DBI Centering
CAL_ERROR Decode for Write DQS to DQ/DBI Centering Calibration
The status of Write DQS to DQ/DBI Centering can also be determined by decoding theCAL_ERROR result according to the table below. Execute the Tcl commands noted in theManually Analyzing the XSDB Output section to generate the XSDB output containing the signalresults
Table 115: CAL_ERROR Decode for Write DQS to DQ/DBI Centering Calibration
Error Code Description Recommended Debug Step
27Right edge of write data not found byincrementing DQS ODELAY using step size of 10taps.
Check for a mapping issue. This usually implies adelay is not moving when it should. Check theconnections going to the XPHY and ensure thecorrect RIU is selected based on the byte beingadjusted.
28Right edge of write data not found byincrementing DQS ODELAY using step size of 1tap.
Check for a mapping issue. This usually implies adelay is not moving when it should. Check theconnections going to the XPHY and ensure thecorrect RIU is selected based on the byte beingadjusted.
29 Positive sanity check failed.
Check CAL_ERROR_BIT_*_*,CAL_ERROR_DATA_NIBBLE_*_*,CAL_ERROR_PHY_NIBBLE_*_* XSDB registers todetermine which nibbles/bits failed. Checkmargin found during previous stages ofcalibration for the given byte that failed.
Appendix B: Debugging
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XSDB Registers of Interest during Write DQS to DQ/DBI Centering Calibration
The following table shows the XSDB registers and values adjusted or used during the Write DQSto DQ/DBI Centering stage of calibration. The values can be analyzed in both successful andfailing calibrations to determine the resultant values and the consistency in results across resets.These values can be found within the Memory IP core properties in the Hardware Manager or byexecuting the Tcl commands noted in the Manually Analyzing the XSDB Output section.
Table 116: XSDB Registers of Interest during Write DQS to DQ/DBI CenteringCalibration
XSDB Reg Usage Signal DescriptionBRAM_WRDQDBI_LEFT_MARGIN_BYTE* One per byte Write data left margin.
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT* One per byte DQ ODELAY value at the left edge ofwrite data window.
BRAM_WRDQDBI_LEFT_EDGE_DBI_BYTE* One per byte DBI ODELAY value at the left edge ofwrite data window.
BRAM_WRDQDBI_RIGHT_MARGIN_FCRSE_BYTE* One per byteDQS ODELAY value when right edge ofwrite data valid window is detected byincrementing DQS ODELAY using stepsize of 10 taps (Simple).
BRAM_WRDQDBI_RIGHT_MARGIN_BYTE* One per byteDQS ODELAY value when right edge ofwrite data valid window is detected byincrementing DQS ODELAY using stepsize of 1 tap (Simple).
BRAM_WRDQDBI_RIGHT_EDGE_DQS_BYTE* One per byte
BRAM_WRDQDBI_ODLY_DQS_FINAL_BYTE* One per byte Final DQS ODELAY value after WriteDQS-to-DQ/DBI Centering (Simple).
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT* One per byte Final DQ ODELAY value after WriteDQS-to-DQ/DBI Centering (Simple).
BRAM_WRDQDBI_ODLY_DBI_FINAL_BYTE* One per byte Final DBI ODELAY value after WriteDQS-to-DQ/DBI Centering (Simple).
This is a sample of the results for the Write DQ Per-Bit Deskew XSDB debug signals:
BRAM_WRDQDBI_LEFT_MARGIN_BYTE0 int true 66BRAM_WRDQDBI_LEFT_MARGIN_BYTE1 int true 61BRAM_WRDQDBI_LEFT_MARGIN_BYTE2 int true 66BRAM_WRDQDBI_LEFT_MARGIN_BYTE3 int true 73BRAM_WRDQDBI_LEFT_MARGIN_BYTE4 int true 70BRAM_WRDQDBI_LEFT_MARGIN_BYTE5 int true 63BRAM_WRDQDBI_LEFT_MARGIN_BYTE6 int true 75BRAM_WRDQDBI_LEFT_MARGIN_BYTE7 int true 64BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT00 int true 31BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT01 int true 39BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT02 int true 33BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT03 int true 43BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT04 int true 42BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT05 int true 48
Appendix B: Debugging
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BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT06 int true 42BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT07 int true 42BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT08 int true 69BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT09 int true 69BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT10 int true 70BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT11 int true 75BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT12 int true 70BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT13 int true 78BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT14 int true 70BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT15 int true 63BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT16 int true 113BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT17 int true 114BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT18 int true 113BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT19 int true 123BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT20 int true 105BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT21 int true 118BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT22 int true 116BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT23 int true 121BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT24 int true 97BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT25 int true 98BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT26 int true 93BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT27 int true 103BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT28 int true 97BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT29 int true 96BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT30 int true 101BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT31 int true 103BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT32 int true 62BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT33 int true 61BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT34 int true 59BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT35 int true 63BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT36 int true 59BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT37 int true 75BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT38 int true 68BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT39 int true 68BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT40 int true 31BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT41 int true 30BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT42 int true 30BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT43 int true 41BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT44 int true 28BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT45 int true 39BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT46 int true 35BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT47 int true 38BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT48 int true 61BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT49 int true 59BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT50 int true 55BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT51 int true 59BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT52 int true 57BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT53 int true 63BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT54 int true 63BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT55 int true 66BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT56 int true 99BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT57 int true 114BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT58 int true 114BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT59 int true 117BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT60 int true 113BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT61 int true 118BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT62 int true 114BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT63 int true 118BRAM_WRDQDBI_LEFT_EDGE_DBI_BYTE0 int true 39BRAM_WRDQDBI_LEFT_EDGE_DBI_BYTE1 int true 76BRAM_WRDQDBI_LEFT_EDGE_DBI_BYTE2 int true 119BRAM_WRDQDBI_LEFT_EDGE_DBI_BYTE3 int true 102BRAM_WRDQDBI_LEFT_EDGE_DBI_BYTE4 int true 67
Appendix B: Debugging
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BRAM_WRDQDBI_LEFT_EDGE_DBI_BYTE5 int true 38BRAM_WRDQDBI_LEFT_EDGE_DBI_BYTE6 int true 66BRAM_WRDQDBI_LEFT_EDGE_DBI_BYTE7 int true 107BRAM_WRDQDBI_RIGHT_EDGE_DQS_BYTE0 int true 0BRAM_WRDQDBI_RIGHT_EDGE_DQS_BYTE1 int true 0BRAM_WRDQDBI_RIGHT_EDGE_DQS_BYTE2 int true 0BRAM_WRDQDBI_RIGHT_EDGE_DQS_BYTE3 int true 0BRAM_WRDQDBI_RIGHT_EDGE_DQS_BYTE4 int true 0BRAM_WRDQDBI_RIGHT_EDGE_DQS_BYTE5 int true 0BRAM_WRDQDBI_RIGHT_EDGE_DQS_BYTE6 int true 0BRAM_WRDQDBI_RIGHT_EDGE_DQS_BYTE7 int true 0BRAM_WRDQDBI_RIGHT_MARGIN_FCRSE_BYTE0 int true 100BRAM_WRDQDBI_RIGHT_MARGIN_FCRSE_BYTE1 int true 100BRAM_WRDQDBI_RIGHT_MARGIN_FCRSE_BYTE2 int true 100BRAM_WRDQDBI_RIGHT_MARGIN_FCRSE_BYTE3 int true 90BRAM_WRDQDBI_RIGHT_MARGIN_FCRSE_BYTE4 int true 100BRAM_WRDQDBI_RIGHT_MARGIN_FCRSE_BYTE5 int true 90BRAM_WRDQDBI_RIGHT_MARGIN_FCRSE_BYTE6 int true 90BRAM_WRDQDBI_RIGHT_MARGIN_FCRSE_BYTE7 int true 90BRAM_WRDQDBI_RIGHT_MARGIN_BYTE0 int true 99BRAM_WRDQDBI_RIGHT_MARGIN_BYTE1 int true 106BRAM_WRDQDBI_RIGHT_MARGIN_BYTE2 int true 103BRAM_WRDQDBI_RIGHT_MARGIN_BYTE3 int true 91BRAM_WRDQDBI_RIGHT_MARGIN_BYTE4 int true 103BRAM_WRDQDBI_RIGHT_MARGIN_BYTE7 int true 97BRAM_WRDQDBI_RIGHT_MARGIN_BYTE5 int true 97BRAM_WRDQDBI_RIGHT_MARGIN_BYTE6 int true 90BRAM_WRDQDBI_ODLY_DQS_FINAL_BYTE0 int true 48BRAM_WRDQDBI_ODLY_DQS_FINAL_BYTE1 int true 86BRAM_WRDQDBI_ODLY_DQS_FINAL_BYTE2 int true 124BRAM_WRDQDBI_ODLY_DQS_FINAL_BYTE3 int true 102BRAM_WRDQDBI_ODLY_DQS_FINAL_BYTE4 int true 76BRAM_WRDQDBI_ODLY_DQS_FINAL_BYTE5 int true 45BRAM_WRDQDBI_ODLY_DQS_FINAL_BYTE6 int true 63BRAM_WRDQDBI_ODLY_DQS_FINAL_BYTE7 int true 116BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT00 int true 31BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT01 int true 39BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT02 int true 33BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT03 int true 43BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT04 int true 42BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT05 int true 48BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT06 int true 42BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT07 int true 42BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT08 int true 69BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT09 int true 69BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT10 int true 70BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT11 int true 75BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT12 int true 70BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT13 int true 78BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT14 int true 70BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT15 int true 63BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT16 int true 113BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT17 int true 114BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT18 int true 113BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT19 int true 123BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT20 int true 105BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT21 int true 118BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT22 int true 116BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT23 int true 121BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT24 int true 97BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT25 int true 98BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT26 int true 93BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT27 int true 103
Appendix B: Debugging
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BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT28 int true 97BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT29 int true 96BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT30 int true 101BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT31 int true 103BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT32 int true 62BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT33 int true 61BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT34 int true 59BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT35 int true 63BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT36 int true 59BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT37 int true 75BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT38 int true 68BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT39 int true 68BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT40 int true 31BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT41 int true 30BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT42 int true 30BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT43 int true 41BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT44 int true 28BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT45 int true 39BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT46 int true 35BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT47 int true 38BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT48 int true 61BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT49 int true 59BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT50 int true 55BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT51 int true 59BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT52 int true 57BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT53 int true 63BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT54 int true 63BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT55 int true 66BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT56 int true 99BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT57 int true 114BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT58 int true 114BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT59 int true 117BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT60 int true 113BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT61 int true 118BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT62 int true 114BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT63 int true 118BRAM_WRDQDBI_ODLY_DBI_FINAL_BYTE0 int true 39BRAM_WRDQDBI_ODLY_DBI_FINAL_BYTE1 int true 76BRAM_WRDQDBI_ODLY_DBI_FINAL_BYTE2 int true 119BRAM_WRDQDBI_ODLY_DBI_FINAL_BYTE3 int true 102BRAM_WRDQDBI_ODLY_DBI_FINAL_BYTE4 int true 67BRAM_WRDQDBI_ODLY_DBI_FINAL_BYTE5 int true 38BRAM_WRDQDBI_ODLY_DBI_FINAL_BYTE6 int true 66BRAM_WRDQDBI_ODLY_DBI_FINAL_BYTE7 int true 107
Related Information
Manually Analyzing the XSDB Output
Expected Results
Hardware measurements should show that the write DQ bits are deskewed and that the writeDQS are centered in the write DQ window at the end of these calibration stages:
• Look at the individual BRAM_WRDQDBI_ODLY_DQS_FINAL_BYTE* andBRAM_WRDQDBI_ODLY_DQ_FINAL_BYTE* tap settings for each nibble. The taps shouldonly vary by 0 to 20 taps. See Determining Window Size in ps section to calculate the writewindow.
Appendix B: Debugging
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• Determine if any bytes completed successfully. The write calibration algorithm steps througheach DQS byte group detecting the capture edges.
• If the incorrect data pattern is detected, determine if the error is due to the write access orthe read access.
• Both edges need to be found. This is possible at all frequencies because the algorithm uses90° of ODELAY taps to find the edges.
• To analyze the window size in ps, see Determining Window Size in ps section. As a generalrule of thumb, the window size for a healthy system should be ≥ 30% of the expected UI size.
Related Information
Determining Window Size in ps
Hardware Measurements
1. Probe the DQS to DQ write phase relationship at the memory. DQS should be center-alignedto DQ at the end of this stage of calibration. Trigger at the start (cal_r*_status[26] = Rfor Rising Edge) and again at the end (cal_r*_status[27] = R for Rising Edge) of WriteDQS to DQ/DBI Centering to view the starting and ending alignments.
2. Using the Vivado Hardware Manager and while running the Memory IP Example Design withDebug Signals enabled, set the trigger (cal_r*_status[26] = R for Rising Edge). Thesimulation examples shown in the Debugging Write Per-Bit DQ Deskew Failures section canbe used to additionally monitor the expected behavior for Write DQS Centering.
Related Information
Debugging Write Per-Bit DQ Deskew Failures
Debugging Write Latency Calibration Failures
Calibration Overview
Write latency calibration is required to align the write DQS to the correct CK edge. During writeleveling, the write DQS is aligned to the nearest rising edge of CK. However, this might not bethe edge that captures the write command. Depending on the interface type (UDIMM, RDIMM,LRDIMM, or component), the DQS could be up to three CK cycles earlier or aligned to the CKedge that captures the write command.
Write latency calibration makes use of the coarse tap in the WL_RNK_REG of the XPHY foradjusting the write latency on a per byte basis. Write leveling uses up a maximum of three coarsetaps of the XPHY delay ensuring each write DQS is aligned to the nearest clock edge. MemoryController provides the write data 1 tCK early to the PHY, which is then delayed by write levelingup to one memory clock cycle. This means for the zero PCB delay case of a typical simulation thedata would be aligned at the DRAM without additional delay added from write calibration.
Appendix B: Debugging
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Write latency calibration can only account for early data, because in the case where the dataarrives late at the DRAM there is no push back on the controller to provide the data earlier. With16 XPHY coarse taps available (each tap is 90°), four memory clock cycles of shift are available inthe XPHY with one memory clock used by write leveling. This leaves three memory clocks ofdelay available for write latency calibration.
The figure shows the calibration flow to determine the setting required for each byte.
Appendix B: Debugging
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Send one write command with Pre and post data bursts
Send one read command to the same address
Byte_Count != 0
Byte_Count = Total DQS
Read Received data for the byte indexed by Byte_Count
Compare the Read data
Add 0 coarse
taps
If coarse taps < 4 ?
Add -4 coarse
taps
ErrorWrite latency Correction End
Do sanity check by sending one write and one read for the same address
Sanity Pass ?
Yes
No
DEC Byte_Count
Write latency correctionNone -1 3 2 1 0
Add 4 coarse
taps
Add 8 coarse
taps
Add 12 coarse
taps
X24744-101420
The write DQS for the write command is extended for longer than required to ensure the DQS istoggling when the DRAM expects it to clock in the write data. A specific data pattern is used tocheck when the correct data pattern gets written into the DRAM, as shown in the figure below.
Appendix B: Debugging
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Figure 96: Write Latency Calibration Alignment Example
DQS/DQS#
DQ 0x00 0xFFFF 00 AA 55 55 AA 99 66
CK/CK#
Target cWL
DQS/DQS#
DQ 0x00 0xFFFF 00 AA 55 55 AA 99 66
Data Read Back: 55AA9966FFFFFFFF
Coarse: 3
Coarse: 7Data Read Back:
AA5555AA9966FFFFDQS/DQS#
DQ 0x00 0xFFFF 00 AA 55 55 AA 99 66Coarse: 11
Data Read Back: FF00AA5555AA9966
X24743-101420
In the example at the start of write latency calibration for the given byte. the target write latencyfalls in the middle of the data pattern. The returned data would be 55AA9966FFFFFFFF ratherthan the expected FF00AA5555AA9966. The write DQS and data are delayed using the XPHYcoarse delay and the operation is repeated, until the correct data pattern is found or there are nomore coarse taps available. After the pattern is found, the amount of coarse delay required isindicated by BRAM_WRLAT_WLDLYRNK_CRSE_FINAL_RANK*_BYTE*.
If the data pattern is not found for a given byte, the data pattern found is checked to see if thedata at the maximum delay available still arrives too early (indicating not enough adjustment wasavailable in the XPHY to align to the correct location) or if the first burst with no extra delayapplied is already late (indicating at the start the data would need to be pulled back). Thefollowing data pattern is checked:
• Expected pattern on a per-nibble basis: F0A55A96
• Late Data Comparison: 00F0AA55A
• Early Data Comparison: A55A96FF, 5A96FFFF, 96FFFFF
Debug
To determine the status of Write Latency Calibration, click the WRITE_LATENCY_CAL stageunder the Status window and view the results within the Memory IP Properties window. Themessage displayed in the Memory IP Properties identifies how the stage failed, or notes if itpassed successfully.
Appendix B: Debugging
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Figure 97: Memory IP XSDB Debug GUI Example – Write Latency Calibration
CAL_ERROR Decode for Write Latency Calibration
The status of Write Latency Calibration can also be determined by decoding the CAL_ERRORresult according to the table below. Execute the Tcl commands noted in the Manually Analyzingthe XSDB Output section to generate the XSDB output containing the signal results.
Table 117: CAL_ERROR Decode for Write Latency Calibration
Error Code Description Recommended Debug Step
37 Could not find the data pattern given theamount of movement available.
38Write Latency found rank to rank skew greaterthan expected. Check margin for the byte forearlier stages of calibration. Probe the DQS/DQsignals (and DM if applicable).
Check DQS and CK trace lengths for all theranks. Ensure the maximum trace length is notviolated. For debug purposes, try a lowerfrequency.
39 Positive sanity check failed.Check read data margins from earlier stages ofcalibration. Check signal integrity during readson the DQS and DQ.
Related Information
Manually Analyzing the XSDB Output
Appendix B: Debugging
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XSDB Registers of Interest during Write Latency Calibration
The following table shows the XSDB registers and values adjusted or used during the WriteLatency stage of calibration. The values can be analyzed in both successful and failingcalibrations to determine the resultant values and the consistency in results across resets. Thesevalues can be found within the Memory IP core properties in the Hardware Manager or byexecuting the Tcl commands noted in the Manually Analyzing the XSDB Output section.
Table 118: XSDB Registers of Interest during Write Latency Calibration
XSDB Reg Usage Signal DescriptionBRAM_WRLAT_INIT_LATENCY One value Global initial write latency value.
BRAM_WRLAT_MATCH_RANK*_BYTE* One per byte Common Write Latency across allranks.
BRAM_WRLAT_MIN_LATENCY One value Minimum Write Latency across allranks.
BRAM_WRLAT_WLDLYRNK_CRSE_FINAL_RANK*_BYTE* One per rank per byte Final WR_DLY_RNK* coarse tap settingafter write leveling.
This is a sample of the results for the Write Latency XSDB debug signals:
BRAM_WRLAT_INIT_LATENCY int true 0BRAM_WRLAT_MATCH_RANK0_BYTE0 int true 0BRAM_WRLAT_MATCH_RANK0_BYTE1 int true 0BRAM_WRLAT_MATCH_RANK0_BYTE2 int true 0BRAM_WRLAT_MATCH_RANK0_BYTE3 int true 0BRAM_WRLAT_MATCH_RANK0_BYTE4 int true 0BRAM_WRLAT_MATCH_RANK0_BYTE5 int true 0BRAM_WRLAT_MATCH_RANK0_BYTE6 int true 0BRAM_WRLAT_MATCH_RANK0_BYTE7 int true 0BRAM_WRLAT_MIN_LATENCY int true 0BRAM_WRLAT_WLDLYRNK_CRSE_FINAL_RANK0_BYTE0 int true 0BRAM_WRLAT_WLDLYRNK_CRSE_FINAL_RANK0_BYTE1 int true 0BRAM_WRLAT_WLDLYRNK_CRSE_FINAL_RANK0_BYTE2 int true 0BRAM_WRLAT_WLDLYRNK_CRSE_FINAL_RANK0_BYTE3 int true 0BRAM_WRLAT_WLDLYRNK_CRSE_FINAL_RANK0_BYTE4 int true 0BRAM_WRLAT_WLDLYRNK_CRSE_FINAL_RANK0_BYTE5 int true 0BRAM_WRLAT_WLDLYRNK_CRSE_FINAL_RANK0_BYTE6 int true 6BRAM_WRLAT_WLDLYRNK_CRSE_FINAL_RANK0_BYTE7 int true 6
Related Information
Manually Analyzing the XSDB Output
Expected Results
The expected value on WRITE_LATENCY_CALIBRATION_COARSE is dependent on the startingpoint set by Write Leveling (which can be 0 to 4). The PCB trace length to the SDRAM typicallyadds up to two memory clock cycles to this starting point where each clock cycle is four coarsetaps.
Appendix B: Debugging
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If the design is stuck in the Write Latency stage, the issue could be related to either the write orthe read. Determining whether the write or read is causing the failure is critical. The followingsteps should be completed.
1. To trigger on the start of Write Latency Calibration, set the trigger to (cal_r*_status[28]= R for Rising Edge).
2. To trigger on the end of Write Latency Calibration, set the trigger to (cal_r*_status[29]= R for Rising Edge). To look at each byte, additionally add a trigger on dbg_cmp_byte andset to the byte of interest.
3. To ensure the writes are correct, observe the write DQS to write DQ relationship at thememory using high quality scope and probes. During Write Latency, a write is followed by aread so care needs to be taken to ensure the write is captured. If there is a failing bit,determining the write DQS to write DQ relationship for the specific DQ bit is critical. Thewrite ideally has the DQS center-aligned in the DQ window. Misalignment between DQS andDQ during Write Calibration points to an issue with Write DQS Centering calibration. Reviewthe Debugging Write DQS to DB/DBI Centering Failures section.
4. If the DQ-DQS alignment looks correct, next observe the we_n to DQS relationship at thememory during a write again using high quality scope and probes. The we_n to DQS delaymust equal the CAS Write Latency (CWL).
5. Using high quality scope and probes, verify the expected pattern (FF00AA5555AA9966) isbeing written to the DRAM during a write and that the expected pattern is being read backduring the first Write Calibration read. If the pattern is correct during write and read at theDRAM, verify the DQS-CK alignment. During Write Calibration, these two signals should bealigned. Write Leveling aligned these two signals which has successfully completed beforeWrite Latency.
6. Probe ODT and we_n during a write command. For ODT to be properly powered on in thememory, ODT must assert before the write command.
7. Probe DM to ensure it is held low during calibration. If a board issue exists causing DM toimproperly assert, incorrect data can be read back during calibration causing a writecalibration failure. An example of a board issue on DM is when DM is not used and tied lowat the memory with improper termination.
8. Using the Vivado Hardware Manager and while running the Memory IP Example Design withDebug Signals enabled, set the trigger.
• To trigger on the start of Write Latency Calibration, set the trigger to(cal_r*_status[28] = R for Rising Edge).
• To trigger on the end of Write Latency Calibration, set the triggerto(cal_r*_status[29] = R for Rising Edge). To look at each byte, additionally add atrigger on dbg_cmp_byte and set to the byte of interest.
The following simulation examples show how the debug signals should behave during successfulWrite Latency Calibration.
Appendix B: Debugging
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If the read DBI option is selected for DDR4, the DBI pin needs to be calibrated along with theDQ bits being captured.
The regular deskew algorithm performs a per-bit deskew on every DQ bit in a nibble against thePDQS/NDQS, pushing early DQ bits to line up with late bits. Because the DBI pin is an input toone of the nibbles, it could affect the PQTR/NQTR settings or even the other DQ pins if the DQpins need to be pushed to align with the DBI pin. A similar mechanism as the DQ per-bit deskewis ran but the DBI pin is deskewed instead in relation to the PDQS/NDQS.
DBI deskew calibration algorithm is started after the completion of read and write per bit DQdeskew calibration step. Pattern 10101010 is written in the memory and read back with DBImode enabled. Because DBI mode is enabled, instead of driving 10101010 on data lines DRAMdrives static 1 and 10101010 on the DBI line.
1. Turn on DBI on the read path (MRS setting in the DRAM and a fabric switch that inverts theread data when value read from the DBI pin is asserted).
2. If the nibble does not contain the DBI pin, skip the nibble and go to the next nibble.
3. Start from the previous PQTR/NQTR settings found during DQS to DQ centering.
4. Issue back-to-back reads to address where pattern 10101010 is written. This is repeateduntil per-bit DBI deskew is complete as shown in the figure below.
Figure 100: DBI Deskew Read Pattern
DQS/DQS#
0xFF
DQ
0xFF 0xFF 0xFF 0x000x000x000x00
0xFF
DBI_n
Data inDRAMArray
X24714-101420
5. Confirm PDQS and NDQS are sampling valid region of DBI.
• If they are not sampling the valid region, then DBI is delayed until they start sampling thevalid region with the minimum valid window confirmation.
• If they are already sampling the valid region, then only the minimum valid windowconfirmation is required.
Appendix B: Debugging
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6. After completion of step 5, DBI continues to be delayed until the PDQS and the NDQS startsampling the noise region of the DBI.
7. The delay taps used for DBI in step 6 + the minimum valid window taps is called left marginof the DBI.
8. Revert the DBI delay taps equal to the left margin.
9. Start incrementing the delay taps of the DQ lines and PDQS/NDQS until PDQS and NDQSstart sampling the noise region of the DBI.
10. The used delay taps in the step 9 is called right margin of the DBI.
11. Revert all the delay taps of the step 9.
12. Compare left margin versus the right margin.
• If the left margin is bigger than the right margin, then add delay equal to (left margin –right margin) / 2 to the DBI delay lines.
• If the right margin is bigger than the left margin, then add delay equal to (right margin –left margin) / 2 to the DQ IDELAY, PQTR, and NQTR.
13. Loop through all nibbles in the interface for the rank.
14. Turn off DBI on the read path (MRS setting in the DRAM and fabric switch).
Debug
To determine the status of Read Per-Bit DBI Deskew Calibration, click the READ_DBI_CAL stageunder the Status window and view the results within the Memory IP Properties window. Themessage displayed in the Memory IP Properties identifies how the stage failed, or notes if itpassed successfully.
Appendix B: Debugging
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2. Probe the data and DBI pins to check for data being returned from the DRAM.
3. Probe the writes checking the signal level of the write DQS and the write DQ.
4. Probe the DBI pin which should be deasserted during the write burst. The DBI pin should notbe asserted because DBI write should be off.
5. Probe the read burst after the write and check if the expected data pattern is being returned.
6. Check for floating address pins if the expected data is not returned.
7. Check for any stuck-at level issues on DQ/DBI pins whose signal level does not change. If atall possible probe at the receiver to check termination and signal integrity.
Appendix B: Debugging
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8. Check the DBG port signals and the full read data and comparison result to check the data ingeneral interconnect. The calibration algorithm has RTL logic issue the commands and checkthe data. Check if the dbg_rd_valid aligns with the data pattern or is off (which canindicate an issue with DQS gate calibration). Set up a trigger when the error gets asserted tocapture signals in the hardware debugger for analysis.
9. Re-check results from DQS gate or other previous calibration stages. Compare passing bytelanes against failing byte lanes for previous stages of calibration. If a failure occurs duringsimple pattern calibration, check the values found during deskew for example.
10. All of the data comparison for read deskew occurs in the general interconnect, so it can beuseful to pull in the debug data in the hardware debugger and take a look at what the datalooks like coming back as taps are adjusted.
11. Using the Vivado Hardware Manager and while running the Memory IP Example Design withDebug Signals enabled, set the Read DBI Deskew trigger to cal_r*_status[30] = R(rising edge). To view each byte, add an additional trigger on dbg_cmp_byte and set to thebyte of interest.
Debugging Read DQS to DQ/DBI Centering Complex Failures
Calibration OverviewNote: Only enabled for data rates above 1,600 Mb/s.
Complex data patterns are used for advanced read DQS centering for memory systems toimprove read timing margin. Long and complex data patterns on both the victim and aggressorDQ lanes impact the size and location of the data eye. The objective of the complex calibrationstep is to generate the worst case data eye on each DQ lane so that the DQS signal can bealigned, resulting in good setup/hold margin during normal operation with any workload.
There are two long data patterns stored in a block RAM, one for a victim DQ lane, and anaggressor pattern for all other DQ lanes. These patterns are used to generate write data, as wellas expected data on reads for comparison and error logging. Each pattern consists of 157 8-bitchunks or BL8 bursts.
Each DQ lane of 1-byte takes a turn at being the victim. An RTL state machine automaticallyselects each DQ lane in turn, MUXing the victim or aggressor patterns to the appropriate DQlanes, issues the read/write transactions, and records errors. The victim pattern is only walkedacross the DQ lanes of the selected byte to be calibrated, and all other DQ lanes carry theaggressor pattern, including all lanes in unselected bytes if there is more than 1-byte lane.
Similar steps to those described in Read DQS Centering are performed, with the PQTR/NQTRstarting out at the left edge of the simple window found previously. The complex pattern iswritten and read back. All bits in a nibble are checked to find the left edge of the window,incrementing the bits together as needed or the PQTR/NQTR to find the aggregate left edge.After the left and right edges are found, it steps through the entire data eye.
Appendix B: Debugging
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To determine the status of Read DQS to DQ/DBI Centering Complex Calibration, click theREAD_DQ_DBI_CAL_COMPLEX stage under the Status window and view the results within theMemory IP Properties window. The message displayed in the Memory IP Properties identifieshow the stage failed, or notes if it passed successfully.
Figure 102: Memory IP XSDB Debug GUI Example – Read DQS to DQ/DBI CenteringComplex
CAL_ERROR Decode for Read DQS to DQ/DBI Centering Complex Calibration
The status of Read DQS to DQ/DBI Centering Complex can also be determined by decoding theCAL_ERROR result according to the table below. Execute the Tcl commands noted in theManually Analyzing the XSDB Output section to generate the XSDB output containing the signalresults
Table 119: CAL_ERROR Decode for Read DQS to DQ/DBI Centering Complex Calibration
Error Code Description Recommended Debug Step
49
Noise region not found for a given bit in thenibble by incrementing DQ IDELAY
Check for a mapping issue. This usually implies adelay is not moving when it should. Check theconnections going to the XPHY and ensure thecorrect RIU is selected based on the byte beingadjusted.
Appendix B: Debugging
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Table 119: CAL_ERROR Decode for Read DQS to DQ/DBI Centering Complex Calibration(cont'd)
Error Code Description Recommended Debug Step
50Could not find the left edge of valid data windowby incrementing PQTR/NQTR IDELAY together(short complex burst)
Check for a mapping issue. This usually implies adelay is not moving when it should. Check theconnections going to the XPHY and ensure thecorrect RIU is selected based on the byte beingadjusted.
51Could not find the left edge of valid data windowby incrementing PQTR/NQTR IDELAY together(long complex burst)
Check for a mapping issue. This usually implies adelay is not moving when it should. Check theconnections going to the XPHY and ensure thecorrect RIU is selected based on the byte beingadjusted.
52Could not find the right edge of valid datawindow by decrementing PQTR/NQTR IDELAYtogether (short complex burst)
Check for a mapping issue. This usually implies adelay is not moving when it should. Check theconnections going to the XPHY and ensure thecorrect RIU is selected based on the byte beingadjusted.
53Could not find the right edge of valid datawindow by decrementing PQTR/NQTR IDELAYtogether (long complex burst)
Check for a mapping issue. This usually implies adelay is not moving when it should. Check theconnections going to the XPHY and ensure thecorrect RIU is selected based on the byte beingadjusted.
54 Positive sanity check failed
Check CAL_ERROR_BIT_*_*,CAL_ERROR_DATA_NIBBLE_*_*,CAL_ERROR_PHY_NIBBLE_*_* XSDB registers todetermine which nibbles/bits failed. Checkmargin found during previous stages ofcalibration for the given byte that failed.
Related Information
Manually Analyzing the XSDB Output
XSDB Registers of Interest during Read DQS to DQ/DBI Centering Complex Calibration
The following table shows the XSDB registers and values adjusted or used during the Read DQSto DQ/DBI Centering Complex stage of calibration. The values can be analyzed in bothsuccessful and failing calibrations to determine the resultant values and the consistency in resultsacross resets. These values can be found within the Memory IP core properties in the HardwareManager or by executing the Tcl commands noted in the Manually Analyzing the XSDB Outputsection.
Table 120: XSDB Registers of Interest during Read DQS to DQ/DBI Centering ComplexCalibration
XSDB Reg Usage Signal Description
BRAM_RDCMPLX_IDELAY_OFFSET_NIBBLE* One per nibble Read leveling IDELAY delay value foundduring Read DQS Centering (simple)
BRAM_RDCMPLX_PQTR_LEFT_SHORT_NIBBLE* One per nibbleRead leveling PQTR tap position whenleft edge of read data valid window isdetected (short complex pattern)
Appendix B: Debugging
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Table 120: XSDB Registers of Interest during Read DQS to DQ/DBI Centering ComplexCalibration (cont'd)
XSDB Reg Usage Signal Description
BRAM_RDCMPLX_NQTR_LEFT_SHORT_NIBBLE* One per nibbleRead leveling NQTR tap position whenleft edge of read data valid window isdetected (short complex pattern).
BRAM_RDCMPLX_PQTR_LEFT_NIBBLE* One per nibbleRead leveling PQTR tap position whenleft edge of read data valid window isdetected (long complex pattern).
BRAM_RDCMPLX_NQTR_LEFT_NIBBLE* One per nibbleRead leveling NQTR tap position whenleft edge of read data valid window isdetected (long complex pattern).
BRAM_RDCMPLX_PQTR_RIGHT_SHORT_FCRSE_NIBBLE* One per nibble
Read leveling PQTR tap position whenright edge of read data valid window isdetected by incrementing PQTR/NQTRIDELAY together using step size of 10taps (short complex pattern).
BRAM_RDCMPLX_NQTR_RIGHT_SHORT_FCRSE_NIBBLE* One per nibble
Read leveling PQTR tap position whenright edge of read data valid window isdetected by incrementing PQTR/NQTRIDELAY together using step size of 10taps (short complex pattern).
BRAM_RDCMPLX_PQTR_RIGHT_SHORT_NIBBLE* One per nibbleRead leveling PQTR tap position whenright edge of read data valid window isdetected (short complex pattern).
BRAM_RDCMPLX_NQTR_RIGHT_SHORT_NIBBLE* One per nibbleRead leveling NQTR tap position whenright edge of read data valid window isdetected (short complex pattern).
BRAM_RDCMPLX_PQTR_RIGHT_NIBBLE* One per nibbleRead leveling PQTR tap position whenright edge of read data valid window isdetected (long complex pattern).
BRAM_RDCMPLX_NQTR_RIGHT_NIBBLE* One per nibbleRead leveling NQTR tap position whenright edge of read data valid window isdetected (long complex pattern).
BRAM_RDCMPLX_PQTR_FINAL_NIBBLE* One per nibbleRead leveling PQTR center tap positionfound at the end of read DQS centering(complex pattern).
BRAM_RDCMPLX_NQTR_FINAL_NIBBLE* One per nibbleRead leveling NQTR center tap positionfound at the end of read DQS centering(complex pattern).
This is a sample of results for Read DQS to DQ/DBI Centering Complex using the Memory IPDebug GUI within the Hardware Manager.
Note: Either the “Table” or “Chart” view can be used to look at the window.
Appendix B: Debugging
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Figure 103: Example of Complex Read Calibration Margin
This is a sample of the results for the Read DQS to DQ/DBI Centering Complex XSDB debugsignals:
BRAM_RDCMPLX_IDELAY_OFFSET_NIBBLE00 int true 0BRAM_RDCMPLX_IDELAY_OFFSET_NIBBLE01 int true 0BRAM_RDCMPLX_IDELAY_OFFSET_NIBBLE02 int true 0BRAM_RDCMPLX_IDELAY_OFFSET_NIBBLE03 int true 0BRAM_RDCMPLX_IDELAY_OFFSET_NIBBLE04 int true 0BRAM_RDCMPLX_IDELAY_OFFSET_NIBBLE05 int true 0BRAM_RDCMPLX_IDELAY_OFFSET_NIBBLE06 int true 0
Appendix B: Debugging
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BRAM_RDCMPLX_IDELAY_OFFSET_NIBBLE07 int true 0BRAM_RDCMPLX_IDELAY_OFFSET_NIBBLE08 int true 0BRAM_RDCMPLX_IDELAY_OFFSET_NIBBLE09 int true 0BRAM_RDCMPLX_IDELAY_OFFSET_NIBBLE10 int true 0BRAM_RDCMPLX_IDELAY_OFFSET_NIBBLE11 int true 0BRAM_RDCMPLX_IDELAY_OFFSET_NIBBLE12 int true 0BRAM_RDCMPLX_IDELAY_OFFSET_NIBBLE13 int true 0BRAM_RDCMPLX_IDELAY_OFFSET_NIBBLE14 int true 0BRAM_RDCMPLX_IDELAY_OFFSET_NIBBLE15 int true 0BRAM_RDCMPLX_PQTR_LEFT_SHORT_NIBBLE00 int true 0BRAM_RDCMPLX_PQTR_LEFT_SHORT_NIBBLE01 int true 0BRAM_RDCMPLX_PQTR_LEFT_SHORT_NIBBLE02 int true 0BRAM_RDCMPLX_PQTR_LEFT_SHORT_NIBBLE03 int true 0BRAM_RDCMPLX_PQTR_LEFT_SHORT_NIBBLE04 int true 0BRAM_RDCMPLX_PQTR_LEFT_SHORT_NIBBLE05 int true 0BRAM_RDCMPLX_PQTR_LEFT_SHORT_NIBBLE06 int true 0BRAM_RDCMPLX_PQTR_LEFT_SHORT_NIBBLE07 int true 0BRAM_RDCMPLX_PQTR_LEFT_SHORT_NIBBLE08 int true 0BRAM_RDCMPLX_PQTR_LEFT_SHORT_NIBBLE09 int true 0BRAM_RDCMPLX_PQTR_LEFT_SHORT_NIBBLE10 int true 0BRAM_RDCMPLX_PQTR_LEFT_SHORT_NIBBLE11 int true 0BRAM_RDCMPLX_PQTR_LEFT_SHORT_NIBBLE12 int true 0BRAM_RDCMPLX_PQTR_LEFT_SHORT_NIBBLE13 int true 0BRAM_RDCMPLX_PQTR_LEFT_SHORT_NIBBLE14 int true 0BRAM_RDCMPLX_PQTR_LEFT_SHORT_NIBBLE15 int true 0BRAM_RDCMPLX_NQTR_LEFT_SHORT_NIBBLE00 int true 0BRAM_RDCMPLX_NQTR_LEFT_SHORT_NIBBLE01 int true 0BRAM_RDCMPLX_NQTR_LEFT_SHORT_NIBBLE02 int true 0BRAM_RDCMPLX_NQTR_LEFT_SHORT_NIBBLE03 int true 0BRAM_RDCMPLX_NQTR_LEFT_SHORT_NIBBLE04 int true 0BRAM_RDCMPLX_NQTR_LEFT_SHORT_NIBBLE05 int true 0BRAM_RDCMPLX_NQTR_LEFT_SHORT_NIBBLE06 int true 0BRAM_RDCMPLX_NQTR_LEFT_SHORT_NIBBLE07 int true 0BRAM_RDCMPLX_NQTR_LEFT_SHORT_NIBBLE08 int true 0BRAM_RDCMPLX_NQTR_LEFT_SHORT_NIBBLE09 int true 0BRAM_RDCMPLX_NQTR_LEFT_SHORT_NIBBLE10 int true 0BRAM_RDCMPLX_NQTR_LEFT_SHORT_NIBBLE11 int true 0BRAM_RDCMPLX_NQTR_LEFT_SHORT_NIBBLE12 int true 0BRAM_RDCMPLX_NQTR_LEFT_SHORT_NIBBLE13 int true 0BRAM_RDCMPLX_NQTR_LEFT_SHORT_NIBBLE14 int true 0BRAM_RDCMPLX_NQTR_LEFT_SHORT_NIBBLE15 int true 0BRAM_RDCMPLX_PQTR_LEFT_NIBBLE00 int true 65BRAM_RDCMPLX_PQTR_LEFT_NIBBLE01 int true 65BRAM_RDCMPLX_PQTR_LEFT_NIBBLE02 int true 69BRAM_RDCMPLX_PQTR_LEFT_NIBBLE03 int true 69BRAM_RDCMPLX_PQTR_LEFT_NIBBLE04 int true 71BRAM_RDCMPLX_PQTR_LEFT_NIBBLE05 int true 71BRAM_RDCMPLX_PQTR_LEFT_NIBBLE06 int true 65BRAM_RDCMPLX_PQTR_LEFT_NIBBLE07 int true 65BRAM_RDCMPLX_PQTR_LEFT_NIBBLE08 int true 69BRAM_RDCMPLX_PQTR_LEFT_NIBBLE09 int true 69BRAM_RDCMPLX_PQTR_LEFT_NIBBLE10 int true 65BRAM_RDCMPLX_PQTR_LEFT_NIBBLE11 int true 65BRAM_RDCMPLX_PQTR_LEFT_NIBBLE12 int true 65BRAM_RDCMPLX_PQTR_LEFT_NIBBLE13 int true 65BRAM_RDCMPLX_PQTR_LEFT_NIBBLE14 int true 75BRAM_RDCMPLX_PQTR_LEFT_NIBBLE15 int true 75BRAM_RDCMPLX_NQTR_LEFT_NIBBLE00 int true 67BRAM_RDCMPLX_NQTR_LEFT_NIBBLE01 int true 67BRAM_RDCMPLX_NQTR_LEFT_NIBBLE02 int true 67BRAM_RDCMPLX_NQTR_LEFT_NIBBLE03 int true 67BRAM_RDCMPLX_NQTR_LEFT_NIBBLE04 int true 69BRAM_RDCMPLX_NQTR_LEFT_NIBBLE05 int true 69
Appendix B: Debugging
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BRAM_RDCMPLX_NQTR_LEFT_NIBBLE06 int true 67BRAM_RDCMPLX_NQTR_LEFT_NIBBLE07 int true 67BRAM_RDCMPLX_NQTR_LEFT_NIBBLE08 int true 73BRAM_RDCMPLX_NQTR_LEFT_NIBBLE09 int true 73BRAM_RDCMPLX_NQTR_LEFT_NIBBLE10 int true 69BRAM_RDCMPLX_NQTR_LEFT_NIBBLE11 int true 69BRAM_RDCMPLX_NQTR_LEFT_NIBBLE12 int true 67BRAM_RDCMPLX_NQTR_LEFT_NIBBLE13 int true 67BRAM_RDCMPLX_NQTR_LEFT_NIBBLE14 int true 71BRAM_RDCMPLX_NQTR_LEFT_NIBBLE15 int true 71BRAM_RDCMPLX_PQTR_RIGHT_SHORT_FCRSE_NIBBLE00 int true 145BRAM_RDCMPLX_PQTR_RIGHT_SHORT_FCRSE_NIBBLE01 int true 165BRAM_RDCMPLX_PQTR_RIGHT_SHORT_FCRSE_NIBBLE02 int true 189BRAM_RDCMPLX_PQTR_RIGHT_SHORT_FCRSE_NIBBLE03 int true 189BRAM_RDCMPLX_PQTR_RIGHT_SHORT_FCRSE_NIBBLE04 int true 191BRAM_RDCMPLX_PQTR_RIGHT_SHORT_FCRSE_NIBBLE05 int true 191BRAM_RDCMPLX_PQTR_RIGHT_SHORT_FCRSE_NIBBLE06 int true 185BRAM_RDCMPLX_PQTR_RIGHT_SHORT_FCRSE_NIBBLE07 int true 185BRAM_RDCMPLX_PQTR_RIGHT_SHORT_FCRSE_NIBBLE08 int true 189BRAM_RDCMPLX_PQTR_RIGHT_SHORT_FCRSE_NIBBLE09 int true 189BRAM_RDCMPLX_PQTR_RIGHT_SHORT_FCRSE_NIBBLE10 int true 185BRAM_RDCMPLX_PQTR_RIGHT_SHORT_FCRSE_NIBBLE11 int true 185BRAM_RDCMPLX_PQTR_RIGHT_SHORT_FCRSE_NIBBLE12 int true 185BRAM_RDCMPLX_PQTR_RIGHT_SHORT_FCRSE_NIBBLE13 int true 185BRAM_RDCMPLX_PQTR_RIGHT_SHORT_FCRSE_NIBBLE14 int true 195BRAM_RDCMPLX_PQTR_RIGHT_SHORT_FCRSE_NIBBLE15 int true 195BRAM_RDCMPLX_NQTR_RIGHT_SHORT_FCRSE_NIBBLE00 int true 147BRAM_RDCMPLX_NQTR_RIGHT_SHORT_FCRSE_NIBBLE01 int true 167BRAM_RDCMPLX_NQTR_RIGHT_SHORT_FCRSE_NIBBLE02 int true 167BRAM_RDCMPLX_NQTR_RIGHT_SHORT_FCRSE_NIBBLE03 int true 167BRAM_RDCMPLX_NQTR_RIGHT_SHORT_FCRSE_NIBBLE04 int true 189BRAM_RDCMPLX_NQTR_RIGHT_SHORT_FCRSE_NIBBLE05 int true 189BRAM_RDCMPLX_NQTR_RIGHT_SHORT_FCRSE_NIBBLE06 int true 167BRAM_RDCMPLX_NQTR_RIGHT_SHORT_FCRSE_NIBBLE07 int true 167BRAM_RDCMPLX_NQTR_RIGHT_SHORT_FCRSE_NIBBLE08 int true 173BRAM_RDCMPLX_NQTR_RIGHT_SHORT_FCRSE_NIBBLE09 int true 173BRAM_RDCMPLX_NQTR_RIGHT_SHORT_FCRSE_NIBBLE10 int true 169BRAM_RDCMPLX_NQTR_RIGHT_SHORT_FCRSE_NIBBLE11 int true 169BRAM_RDCMPLX_NQTR_RIGHT_SHORT_FCRSE_NIBBLE12 int true 187BRAM_RDCMPLX_NQTR_RIGHT_SHORT_FCRSE_NIBBLE13 int true 187BRAM_RDCMPLX_NQTR_RIGHT_SHORT_FCRSE_NIBBLE14 int true 171BRAM_RDCMPLX_NQTR_RIGHT_SHORT_FCRSE_NIBBLE15 int true 171BRAM_RDCMPLX_PQTR_RIGHT_SHORT_NIBBLE00 int true 0BRAM_RDCMPLX_PQTR_RIGHT_SHORT_NIBBLE01 int true 0BRAM_RDCMPLX_PQTR_RIGHT_SHORT_NIBBLE02 int true 0BRAM_RDCMPLX_PQTR_RIGHT_SHORT_NIBBLE03 int true 0BRAM_RDCMPLX_PQTR_RIGHT_SHORT_NIBBLE04 int true 0BRAM_RDCMPLX_PQTR_RIGHT_SHORT_NIBBLE05 int true 0BRAM_RDCMPLX_PQTR_RIGHT_SHORT_NIBBLE06 int true 0BRAM_RDCMPLX_PQTR_RIGHT_SHORT_NIBBLE07 int true 0BRAM_RDCMPLX_PQTR_RIGHT_SHORT_NIBBLE08 int true 0BRAM_RDCMPLX_PQTR_RIGHT_SHORT_NIBBLE09 int true 0BRAM_RDCMPLX_PQTR_RIGHT_SHORT_NIBBLE10 int true 0BRAM_RDCMPLX_PQTR_RIGHT_SHORT_NIBBLE11 int true 0BRAM_RDCMPLX_PQTR_RIGHT_SHORT_NIBBLE12 int true 0BRAM_RDCMPLX_PQTR_RIGHT_SHORT_NIBBLE13 int true 0BRAM_RDCMPLX_PQTR_RIGHT_SHORT_NIBBLE14 int true 0BRAM_RDCMPLX_PQTR_RIGHT_SHORT_NIBBLE15 int true 0BRAM_RDCMPLX_NQTR_RIGHT_SHORT_NIBBLE00 int true 0BRAM_RDCMPLX_NQTR_RIGHT_SHORT_NIBBLE01 int true 0BRAM_RDCMPLX_NQTR_RIGHT_SHORT_NIBBLE02 int true 0BRAM_RDCMPLX_NQTR_RIGHT_SHORT_NIBBLE03 int true 0BRAM_RDCMPLX_NQTR_RIGHT_SHORT_NIBBLE04 int true 0
Appendix B: Debugging
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BRAM_RDCMPLX_NQTR_RIGHT_SHORT_NIBBLE05 int true 0BRAM_RDCMPLX_NQTR_RIGHT_SHORT_NIBBLE06 int true 0BRAM_RDCMPLX_NQTR_RIGHT_SHORT_NIBBLE07 int true 0BRAM_RDCMPLX_NQTR_RIGHT_SHORT_NIBBLE08 int true 0BRAM_RDCMPLX_NQTR_RIGHT_SHORT_NIBBLE09 int true 0BRAM_RDCMPLX_NQTR_RIGHT_SHORT_NIBBLE10 int true 0BRAM_RDCMPLX_NQTR_RIGHT_SHORT_NIBBLE11 int true 0BRAM_RDCMPLX_NQTR_RIGHT_SHORT_NIBBLE12 int true 0BRAM_RDCMPLX_NQTR_RIGHT_SHORT_NIBBLE13 int true 0BRAM_RDCMPLX_NQTR_RIGHT_SHORT_NIBBLE14 int true 0BRAM_RDCMPLX_NQTR_RIGHT_SHORT_NIBBLE15 int true 0BRAM_RDCMPLX_PQTR_RIGHT_NIBBLE00 int true 113BRAM_RDCMPLX_PQTR_RIGHT_NIBBLE01 int true 133BRAM_RDCMPLX_PQTR_RIGHT_NIBBLE02 int true 157BRAM_RDCMPLX_PQTR_RIGHT_NIBBLE03 int true 157BRAM_RDCMPLX_PQTR_RIGHT_NIBBLE04 int true 155BRAM_RDCMPLX_PQTR_RIGHT_NIBBLE05 int true 155BRAM_RDCMPLX_PQTR_RIGHT_NIBBLE06 int true 151BRAM_RDCMPLX_PQTR_RIGHT_NIBBLE07 int true 151BRAM_RDCMPLX_PQTR_RIGHT_NIBBLE08 int true 155BRAM_RDCMPLX_PQTR_RIGHT_NIBBLE09 int true 155BRAM_RDCMPLX_PQTR_RIGHT_NIBBLE10 int true 153BRAM_RDCMPLX_PQTR_RIGHT_NIBBLE11 int true 153BRAM_RDCMPLX_PQTR_RIGHT_NIBBLE12 int true 151BRAM_RDCMPLX_PQTR_RIGHT_NIBBLE13 int true 151BRAM_RDCMPLX_PQTR_RIGHT_NIBBLE14 int true 159BRAM_RDCMPLX_PQTR_RIGHT_NIBBLE15 int true 159BRAM_RDCMPLX_NQTR_RIGHT_NIBBLE00 int true 115BRAM_RDCMPLX_NQTR_RIGHT_NIBBLE01 int true 135BRAM_RDCMPLX_NQTR_RIGHT_NIBBLE02 int true 135BRAM_RDCMPLX_NQTR_RIGHT_NIBBLE03 int true 135BRAM_RDCMPLX_NQTR_RIGHT_NIBBLE04 int true 151BRAM_RDCMPLX_NQTR_RIGHT_NIBBLE05 int true 151BRAM_RDCMPLX_NQTR_RIGHT_NIBBLE06 int true 135BRAM_RDCMPLX_NQTR_RIGHT_NIBBLE07 int true 135BRAM_RDCMPLX_NQTR_RIGHT_NIBBLE08 int true 141BRAM_RDCMPLX_NQTR_RIGHT_NIBBLE09 int true 141BRAM_RDCMPLX_NQTR_RIGHT_NIBBLE10 int true 137BRAM_RDCMPLX_NQTR_RIGHT_NIBBLE11 int true 137BRAM_RDCMPLX_NQTR_RIGHT_NIBBLE12 int true 149BRAM_RDCMPLX_NQTR_RIGHT_NIBBLE13 int true 149BRAM_RDCMPLX_NQTR_RIGHT_NIBBLE14 int true 139BRAM_RDCMPLX_NQTR_RIGHT_NIBBLE15 int true 139BRAM_RDCMPLX_PQTR_FINAL_NIBBLE00 int true 89BRAM_RDCMPLX_PQTR_FINAL_NIBBLE01 int true 99BRAM_RDCMPLX_PQTR_FINAL_NIBBLE02 int true 113BRAM_RDCMPLX_PQTR_FINAL_NIBBLE03 int true 113BRAM_RDCMPLX_PQTR_FINAL_NIBBLE04 int true 113BRAM_RDCMPLX_PQTR_FINAL_NIBBLE05 int true 113BRAM_RDCMPLX_PQTR_FINAL_NIBBLE06 int true 108BRAM_RDCMPLX_PQTR_FINAL_NIBBLE07 int true 108BRAM_RDCMPLX_PQTR_FINAL_NIBBLE08 int true 112BRAM_RDCMPLX_PQTR_FINAL_NIBBLE09 int true 112BRAM_RDCMPLX_PQTR_FINAL_NIBBLE10 int true 109BRAM_RDCMPLX_PQTR_FINAL_NIBBLE11 int true 109BRAM_RDCMPLX_PQTR_FINAL_NIBBLE12 int true 108BRAM_RDCMPLX_PQTR_FINAL_NIBBLE13 int true 108BRAM_RDCMPLX_PQTR_FINAL_NIBBLE14 int true 117BRAM_RDCMPLX_PQTR_FINAL_NIBBLE15 int true 117BRAM_RDCMPLX_NQTR_FINAL_NIBBLE00 int true 91BRAM_RDCMPLX_NQTR_FINAL_NIBBLE01 int true 101BRAM_RDCMPLX_NQTR_FINAL_NIBBLE02 int true 101BRAM_RDCMPLX_NQTR_FINAL_NIBBLE03 int true 101
Appendix B: Debugging
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BRAM_RDCMPLX_NQTR_FINAL_NIBBLE04 int true 110BRAM_RDCMPLX_NQTR_FINAL_NIBBLE05 int true 110BRAM_RDCMPLX_NQTR_FINAL_NIBBLE06 int true 101BRAM_RDCMPLX_NQTR_FINAL_NIBBLE07 int true 101BRAM_RDCMPLX_NQTR_FINAL_NIBBLE08 int true 107BRAM_RDCMPLX_NQTR_FINAL_NIBBLE09 int true 107BRAM_RDCMPLX_NQTR_FINAL_NIBBLE10 int true 103BRAM_RDCMPLX_NQTR_FINAL_NIBBLE11 int true 103BRAM_RDCMPLX_NQTR_FINAL_NIBBLE12 int true 108BRAM_RDCMPLX_NQTR_FINAL_NIBBLE13 int true 108BRAM_RDCMPLX_NQTR_FINAL_NIBBLE14 int true 105BRAM_RDCMPLX_NQTR_FINAL_NIBBLE15 int true 105
Related Information
Manually Analyzing the XSDB Output
Expected Results
• Look at the individual PQTR/NQTR tap settings for each nibble. The taps should only vary by0 to 20 taps. Use the BISC values to compute the estimated bit time in taps.
• Look at the individual IDELAY taps for each bit. The IDELAY taps should only vary by 0 to 20taps, and is dependent on PCB trace delays. For Deskew, the IDELAY taps are typically in the50 to 70 tap range, while PQTR and NQTR are usually in the 0 to 5 tap range.
• Determine if any bytes completed successfully. The read leveling algorithm steps through eachDQS byte group detecting the capture edges.
• If the incorrect data pattern is detected, determine if the error is due to the write access orthe read access.
• To analyze the window size in ps, see Determining Window Size in ps section. As a generalrule of thumb, the window size for a healthy system should be ≥ 30% of the expected UI size.
• Compare read leveling window (read margin size) results from the simple pattern calibrationversus the complex pattern calibration. The windows should all shrink but the reduction inwindow size should shrink relatively across the data byte lanes.
• Use the Memory IP Debug GUI to quickly compare simple versus complex window sizes.
Related Information
Determining Window Size in ps
Hardware Measurements
1. Probe the write commands and read commands at the memory:
4. Probe the DM pin which should be deasserted during the write burst (or tied off on the boardwith an appropriate value resistor).
5. Probe the read burst after the write and check if the expected data pattern is being returned.
6. Check for floating address pins if the expected data is not returned.
7. Check for any stuck-at level issues on DQ pins whose signal level does not change. If at allpossible probe at the receiver to check termination and signal integrity.
8. Check the DBG port signals and the full read data and comparison result to check the data ingeneral interconnect. The calibration algorithm has RTL logic to issue the commands andcheck the data. Check if the dbg_rd_valid aligns with the data pattern or is off. Set up atrigger when the error gets asserted to capture signals in the hardware debugger for analysis.
9. Re-check results from previous calibration stages. Compare passing byte lanes against failingbyte lanes for previous stages of calibration. If a failure occurs during complex patterncalibration, check the values found during simple pattern calibration for example.
10. All of the data comparison for complex read calibration occur in the general interconnect, soit can be useful to pull in the debug data in the hardware debugger and take a look at whatthe data looks like coming back as taps are adjusted, see figures below. The screen capturesshown are from simulation with a small loop count set for the data pattern. Look atdbg_rd_data, dbg_rd_valid, and dbg_cplx_err_log.
11. Using the Vivado Hardware Manager and while running the Memory IP Example Design withDebug Signals enabled, set the Read Complex calibration trigger to cal_r*_status[34]= R (rising edge). To view each byte, add an additional trigger on dbg_cmp_byte and set tothe byte of interest. The following simulation example shows how the debug signals shouldbehave during Read Complex Calibration.
The following figure shows the start of the complex calibration data pattern with an emphasison the dbg_cplx_config bus shown. The “read start” bit is Bit[0] and the number of loopsis set based on Bits[15:9], hence the figure shows the start of complex read pattern and theloop count set to 1 (for simulation only). The dbg_cplx_status goes to 1 to indicate thepattern is in progress. See Debug Signals section list of all debug signals.
Appendix B: Debugging
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12. When an unexpected data error occurs during complex read calibration, for example a byteshift, the entire bus would be 1. This is not the expected bit mismatch found in windowdetection but points to a true read versus write issue. Now, the read data should becompared with the expected (compare) data and the error debugged to determine if it is aread or write issue. Use dbg_rd_data and dbg_rd_dat_cmp to compare the received datato the expected data.
13. After failure during this stage of calibration, the design goes into a continuous loop of readcommands to allow board probing.
Related Information
Debug Signals
Debugging Write DQS to DQ/DBI Centering Complex Failures
Calibration Overview
The final stage of Write DQS-to-DQ/DBI centering that is completed before normal operation isrepeating the steps performed during Write DQS-to-DQ/DBI centering but with a difficult/complex pattern. The purpose of using a complex pattern is to stress the system for SI effectssuch as ISI and noise while calculating the write DQS center and write DQ positions. Thisensures the write center position can reliably capture data with margin in a true system.
1. Turn on DBI on the write path, turn off DM on the write path, and DBI on the read path (MRSsetting in the DRAM and fabric switch).
2. Write complex pattern into the DRAM memory and read back.
3. Find the left margin of the write data window by incrementing each DQ ODELAY and DBIODELAY(if enabled) by step size of 10 taps until invalid data pattern is detected. Oncecompleted, decrement each DQS ODELAY and DBI ODELAY (if enabled) by step size of 10taps. At the end of this stage, left margin value is saved asBRAM_WRCMPLX_LEFT_MARGIN_FCRSE.
4. Find the left margin of the write data window again by incrementing each DQ ODELAY andDBI ODELAY (if enabled) by one fine tap at a time until invalid data pattern is detected. Atthe end of this stage, left margin values are saved as BRAM_WRCMPLX_LEFT_MARGIN.
5. Find the right margin of the write data window by incrementing DQS ODELAY by step size of10 taps until invalid data pattern is detected. At the end of this stage, right margin values aresaved as BRAM_WRCMPLX_RIGHT_MARGIN_FCRSE.
6. Find the right margin of the write data window by incrementing DQS ODELAY by one finetap at a time until invalid data pattern is detected. At the end of this stage, right marginvalues are saved as BRAM_WRCMPLX_RIGHT_MARGIN.
Appendix B: Debugging
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To determine the status of Write DQS to DQ/DBI Centering Complex Calibration, click theWRITE_DQ_DBI_CAL_COMPLEX stage under the Status window and view the results within theMemory IP Properties window. The message displayed in the Memory IP Properties identifieshow the stage failed, or notes if it passed successfully.
Appendix B: Debugging
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Figure 106: Memory IP XSDB Debug GUI Example – Write DQS to DQ/DBI CenteringComplex
CAL_ERROR Decode for Write DQS to DQ/DBI Centering Complex
The status of Write DQS to DQ/DBI Centering Complex can also be determined by decoding theCAL_ERROR result according to the table below. Execute the Tcl commands noted in theManually Analyzing the XSDB Output section to generate the XSDB output containing the signalresults.
Table 121: CAL_ERROR Decode for Write DQS to DQ/DBI Centering Complex
Error Code Description Recommended Debug Step
55
Could not find the left edge of valid data windowby incrementing DQ and DBI ODELAY (ifenabled) together using step size of 10 taps.
Check for a mapping issue. This usually implies adelay is not moving when it should. Check theconnections going to the XPHY and ensure thecorrect RIU is selected based on the byte beingadjusted.
56Could not find the left edge of valid data windowby incrementing DQ and DBI ODELAY (ifenabled) together using step size of 1 tap.
Check for a mapping issue. This usually implies adelay is not moving when it should. Check theconnections going to the XPHY and ensure thecorrect RIU is selected based on the byte beingadjusted.
Appendix B: Debugging
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Table 121: CAL_ERROR Decode for Write DQS to DQ/DBI Centering Complex (cont'd)
Error Code Description Recommended Debug Step
57Could not find the right edge of valid datawindow by incrementing DQS ODELAY usingstep size of 10 taps.
Check for a mapping issue. This usually implies adelay is not moving when it should. Check theconnections going to the XPHY and ensure thecorrect RIU is selected based on the byte beingadjusted.
58Could not find the right edge of valid datawindow by incrementing DQS ODELAY usingstep size of 1 tap.
Check for a mapping issue. This usually implies adelay is not moving when it should. Check theconnections going to the XPHY and ensure thecorrect RIU is selected based on the byte beingadjusted.
59 Positive sanity check failed.
Check CAL_ERROR_BIT_*_*,CAL_ERROR_DATA_NIBBLE_*_*,CAL_ERROR_PHY_NIBBLE_*_* XSDB registers todetermine which nibbles/bits failed. Checkmargin found during previous stages ofcalibration for the given byte that failed.
60Could not find the right edge of valid datawindow by decrementing DQ ODELAY using stepsize of 10 taps.
Check for a mapping issue. This usually implies adelay is not moving when it should. Check theconnections going to the XPHY and ensure thecorrect RIU is selected based on the byte beingadjusted.
61Could not find the right edge of valid datawindow by decrementing DQ ODELAY using stepsize of 1 taps.
Check for a mapping issue. This usually implies adelay is not moving when it should. Check theconnections going to the XPHY and ensure thecorrect RIU is selected based on the byte beingadjusted.
62 Positive sanity check 1 failed.
Check CAL_ERROR_BIT_*_*,CAL_ERROR_DATA_NIBBLE_*_*,CAL_ERROR_PHY_NIBBLE_*_* XSDB registers todetermine which nibbles/bits failed. Checkmargin found during previous stages ofcalibration for the given byte that failed.
63 Write complex read DQS oscillator value to be 0.
64 Write complex computed tDQS2DQ value to beout of range.
Related Information
Manually Analyzing the XSDB Output
XSDB Registers of Interest during Write DQS to DQ/DBI Centering Complex Calibration
The following table shows the XSDB registers and values adjusted or used during the WriteLeveling Complex stage of calibration. The values can be analyzed in both successful and failingcalibrations to determine the resultant values and the consistency in results across resets. Thesevalues can be found within the Memory IP core properties in the Hardware Manager or byexecuting the Tcl commands noted in the Manually Analyzing the XSDB Output section.
Appendix B: Debugging
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Table 122: XSDB Registers of Interest during Write DQS to DQ/DBI Centering ComplexCalibration
XSDB Reg Usage Signal Description
BRAM_WRCMPLX_LEFT_MARGIN_FCRSE_BYTE* One per byteLeft edge of write data valid windowdetected by incrementing DQ/DBIODELAY using step size of 10 taps(Complex).
BRAM_WRCMPLX_LEFT_MARGIN_BYTE* One per byteLeft edge of write data valid windowdetected by incrementing DQ/DBIODELAY using step size of 1 tap(Complex).
BRAM_WRCMPLX_RIGHT_MARGIN_FCRSE_BYTE* One per byteRight edge of write data valid windowdetected by incrementing DQS ODELAYusing step size of 10 taps (Complex).
BRAM_WRCMPLX_RIGHT_MARGIN_BYTE* One per byteRight edge of write data valid windowdetected by incrementing DQS ODELAYusing step size of 1 tap (Complex).
BRAM_WRCMPLX_ODLY_DQS_FINAL_BYTE* One per byte Final DQS ODELAY value after WriteDQS to DQ/DBI Centering (Complex).
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT* One per bit Final DQ ODELAY value after Write DQSto DQ/DBI Centering (Complex).
BRAM_WRCMPLX_ODLY_DBI_FINAL_BYTE* One per byte Final DBI ODELAY value after Write DQSto DQ/DBI Centering (Complex).
This is a sample of results for Write DQS to DQ/DBI Centering Complex using the Memory IPDebug GUI within the Hardware Manager.
Note: Either the “Table” or “Chart” view can be used to look at the window.
Appendix B: Debugging
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Figure 107: Example of Complex Write Calibration Margin
This is a sample of the results for the Write DQS to DQ/DBI Centering Complex XSDB debugsignals:
BRAM_WRCMPLX_LEFT_MARGIN_FCRSE_BYTE0 int true 60BRAM_WRCMPLX_LEFT_MARGIN_FCRSE_BYTE1 int true 50BRAM_WRCMPLX_LEFT_MARGIN_FCRSE_BYTE2 int true 60BRAM_WRCMPLX_LEFT_MARGIN_FCRSE_BYTE3 int true 60BRAM_WRCMPLX_LEFT_MARGIN_FCRSE_BYTE4 int true 50BRAM_WRCMPLX_LEFT_MARGIN_FCRSE_BYTE5 int true 50BRAM_WRCMPLX_LEFT_MARGIN_FCRSE_BYTE6 int true 60
Appendix B: Debugging
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BRAM_WRCMPLX_LEFT_MARGIN_FCRSE_BYTE7 int true 60BRAM_WRCMPLX_LEFT_MARGIN_BYTE0 int true 64BRAM_WRCMPLX_LEFT_MARGIN_BYTE1 int true 58BRAM_WRCMPLX_LEFT_MARGIN_BYTE2 int true 60BRAM_WRCMPLX_LEFT_MARGIN_BYTE3 int true 62BRAM_WRCMPLX_LEFT_MARGIN_BYTE4 int true 59BRAM_WRCMPLX_LEFT_MARGIN_BYTE5 int true 58BRAM_WRCMPLX_LEFT_MARGIN_BYTE6 int true 62BRAM_WRCMPLX_LEFT_MARGIN_BYTE7 int true 65BRAM_WRCMPLX_RIGHT_MARGIN_FCRSE_BYTE0 int true 50BRAM_WRCMPLX_RIGHT_MARGIN_FCRSE_BYTE1 int true 70BRAM_WRCMPLX_RIGHT_MARGIN_FCRSE_BYTE2 int true 70BRAM_WRCMPLX_RIGHT_MARGIN_FCRSE_BYTE3 int true 70BRAM_WRCMPLX_RIGHT_MARGIN_FCRSE_BYTE4 int true 70BRAM_WRCMPLX_RIGHT_MARGIN_FCRSE_BYTE5 int true 60BRAM_WRCMPLX_RIGHT_MARGIN_FCRSE_BYTE6 int true 70BRAM_WRCMPLX_RIGHT_MARGIN_FCRSE_BYTE7 int true 70BRAM_WRCMPLX_RIGHT_MARGIN_BYTE0 int true 59BRAM_WRCMPLX_RIGHT_MARGIN_BYTE1 int true 72BRAM_WRCMPLX_RIGHT_MARGIN_BYTE2 int true 74BRAM_WRCMPLX_RIGHT_MARGIN_BYTE3 int true 71BRAM_WRCMPLX_RIGHT_MARGIN_BYTE4 int true 74BRAM_WRCMPLX_RIGHT_MARGIN_BYTE5 int true 69BRAM_WRCMPLX_RIGHT_MARGIN_BYTE6 int true 74BRAM_WRCMPLX_RIGHT_MARGIN_BYTE7 int true 76BRAM_WRCMPLX_ODLY_DQS_FINAL_BYTE0 int true 57BRAM_WRCMPLX_ODLY_DQS_FINAL_BYTE1 int true 111BRAM_WRCMPLX_ODLY_DQS_FINAL_BYTE2 int true 87BRAM_WRCMPLX_ODLY_DQS_FINAL_BYTE3 int true 54BRAM_WRCMPLX_ODLY_DQS_FINAL_BYTE4 int true 96BRAM_WRCMPLX_ODLY_DQS_FINAL_BYTE5 int true 89BRAM_WRCMPLX_ODLY_DQS_FINAL_BYTE6 int true 103BRAM_WRCMPLX_ODLY_DQS_FINAL_BYTE7 int true 84BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT00 int true 43BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT01 int true 49BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT02 int true 51BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT03 int true 58BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT04 int true 56BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT05 int true 62BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT06 int true 58BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT07 int true 59BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT08 int true 93BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT09 int true 102BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT10 int true 96BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT11 int true 102BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT12 int true 96BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT13 int true 105BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT14 int true 99BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT15 int true 93BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT16 int true 78BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT17 int true 74BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT18 int true 72BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT19 int true 78BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT20 int true 65BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT21 int true 80BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT22 int true 76BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT23 int true 77BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT24 int true 33BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT25 int true 36BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT26 int true 39BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT27 int true 43BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT28 int true 37BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT29 int true 40
Appendix B: Debugging
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BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT30 int true 42BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT31 int true 38BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT32 int true 77BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT33 int true 84BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT34 int true 78BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT35 int true 88BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT36 int true 82BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT37 int true 93BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT38 int true 85BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT39 int true 89BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT40 int true 78BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT41 int true 78BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT42 int true 80BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT43 int true 86BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT44 int true 80BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT45 int true 90BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT46 int true 78BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT47 int true 80BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT48 int true 96BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT49 int true 93BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT50 int true 91BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT51 int true 99BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT52 int true 95BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT53 int true 102BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT54 int true 98BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT55 int true 102BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT56 int true 64BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT57 int true 72BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT58 int true 75BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT59 int true 77BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT60 int true 70BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT61 int true 76BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT62 int true 73BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT63 int true 77BRAM_WRCMPLX_ODLY_DBI_FINAL_BYTE0 int true 58BRAM_WRCMPLX_ODLY_DBI_FINAL_BYTE1 int true 102BRAM_WRCMPLX_ODLY_DBI_FINAL_BYTE2 int true 76BRAM_WRCMPLX_ODLY_DBI_FINAL_BYTE3 int true 46BRAM_WRCMPLX_ODLY_DBI_FINAL_BYTE4 int true 82BRAM_WRCMPLX_ODLY_DBI_FINAL_BYTE5 int true 82BRAM_WRCMPLX_ODLY_DBI_FINAL_BYTE6 int true 101BRAM_WRCMPLX_ODLY_DBI_FINAL_BYTE7 int true 72
Related Information
Manually Analyzing the XSDB Output
Expected Results
• Look at the individual BRAM_WRCMPLX_ODLY_DQS_FINAL_BYTE*,BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT* andBRAM_WRCMPLX_ODLY_DBI_FINAL_BYTE* tap settings. The taps should only vary by 0 to20 taps. To calculate the write window, see Determining Window Size in ps section.
• Determine if any bytes completed successfully. The write calibration algorithm steps througheach DQS byte group detecting the capture edges.
• If the incorrect data pattern is detected, determine if the error is due to the write access orthe read access. See Determining If a Data Error is Due to the Write or Read.
Appendix B: Debugging
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• Both edges need to be found. This is possible at all frequencies because the algorithm uses90° of ODELAY taps to find the edges.
• To analyze the window size in ps, see Determining Window Size in ps section. As a generalrule of thumb, the window size for a healthy system should be ≥ 30% of the expected UI size.
Related Information
Determining Window Size in psDetermining If a Data Error is Due to the Write or Read
Hardware Measurements
1. If the write complex pattern fails, use high quality probes and scope the DQS-to-DQ phaserelationship at the memory during a write. Trigger at the start (cal_r*_status[38] = Rfor Rising Edge) and again at the end (cal_r*_status[39] = R for Rising Edge) of WriteComplex DQS Centering to view the starting and ending alignments. The alignment shouldbe approximately 90°.
2. If the DQS-to-DQ alignment is correct, observe the we_n-to-DQS relationship to see if itmeets CWL again using cal_r*_status[25] = R for Rising Edge as a trigger.
3. For all stages of write/read leveling, probe the write commands and read commands at thememory:
4. Using theVivado Hardware Manager and while running the Memory IP Example Design withthe Debug Signals enabled, set the trigger (cal_r*_status[38] = R for Rising Edge). Thefollowing simulation example shows how the debug signals should behave during successfulWrite DQS-to-DQ.
Appendix B: Debugging
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Figure 108: Expected Behavior during Write Complex Pattern Calibration
VT Tracking
Tracking Overview
Calibration occurs one time at start-up, at a set voltage and temperature to ensure reliablecapture of the data, but during normal operation the voltage and temperature can change or driftif conditions change. Voltage and temperature (VT) variations can change the relationshipbetween DQS and DQ used for read capture and change the time in which the DQS/DQ arrive atthe FPGA as part of a read.
DQS Gate Tracking
The arrival of the DQS at the FPGA as part of a read is calibrated at start-up, but as VT changesthe time in which the DQS arrives can change. DQS gate tracking monitors the arrival of theDQS with a signal from the XPHY and makes small adjustments as required if the DQS arrivesearlier or later a sampling clock in the XPHY. This adjustment is recorded as shown in followingtable.
Table 123: XSDB Registers of Interest for DQS Tracking
XSDB Reg Usage Signal DescriptionDQSTRACK_RLDLYRNK_CRSE_BYTE* One per byte Last recorded value for DQS gate
coarse setting.
Appendix B: Debugging
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Table 123: XSDB Registers of Interest for DQS Tracking (cont'd)
XSDB Reg Usage Signal Description
DQSTRACK_RLDLYRNK_FINE_BYTE* One per byte Last recorded value for DQS gate finesetting.
DQSTRACK_RLDLYRNK_CRSE_MAX_BYTE* One per byte Maximum coarse tap recorded duringDQS gate tracking.
DQSTRACK_RLDLYRNK_FINE_MAX_BYTE* One per byte Maximum fine tap recorded duringDQS gate tracking.
DQSTRACK_RLDLYRNK_CRSE_MIN_BYTE* One per byte Minimum coarse tap recorded duringDQS gate tracking.
DQSTRACK_RLDLYRNK_FINE_MIN_BYTE* One per byte Minimum fine tap recorded during DQSgate tracking.
BISC_ALIGN_PQTR_NIBBLE* One per nibble Initial 0° offset value provided by BISCat power-up.
BISC_ALIGN_NQTR_NIBBLE* One per nibble Initial 0° offset value provided by BISCat power-up.
BISC_PQTR_NIBBLE* One per nibble
Initial 90° offset value provided by BISCat power-up. Compute 90° value in tapsby taking (BISC_PQTR –BISC_ALIGN_PQTR). To estimate tapresolution take (¼ of the memory clockperiod)/ (BISC_PQTR –BISC_ALIGN_PQTR).
BISC_NQTR_NIBBLE* One per nibble
Initial 90° offset value provided by BISCat power-up. Compute 90° value in tapsby taking (BISC_PQTR –BISC_ALIGN_PQTR). To estimate tapresolution take (¼ of the memory clockperiod)/ (BISC_PQTR –BISC_ALIGN_PQTR).
This is a sample of the results for the DQS Gate Tracking XSDB debug signals:
DQSTRACK_RLDLYRNK_CRSE_BYTE0 int true 0DQSTRACK_RLDLYRNK_CRSE_BYTE1 int true 0DQSTRACK_RLDLYRNK_CRSE_BYTE2 int true 0DQSTRACK_RLDLYRNK_CRSE_BYTE3 int true 0DQSTRACK_RLDLYRNK_CRSE_BYTE4 int true 0DQSTRACK_RLDLYRNK_CRSE_BYTE5 int true 0DQSTRACK_RLDLYRNK_CRSE_BYTE6 int true 0DQSTRACK_RLDLYRNK_CRSE_BYTE7 int true 0DQSTRACK_RLDLYRNK_CRSE_BYTE8 int true 0DQSTRACK_RLDLYRNK_FINE_BYTE0 int true 0DQSTRACK_RLDLYRNK_FINE_BYTE1 int true 0DQSTRACK_RLDLYRNK_FINE_BYTE2 int true 0DQSTRACK_RLDLYRNK_FINE_BYTE3 int true 0DQSTRACK_RLDLYRNK_FINE_BYTE4 int true 0DQSTRACK_RLDLYRNK_FINE_BYTE5 int true 0DQSTRACK_RLDLYRNK_FINE_BYTE6 int true 0DQSTRACK_RLDLYRNK_FINE_BYTE7 int true 0DQSTRACK_RLDLYRNK_FINE_BYTE8 int true 0DQSTRACK_RLDLYRNK_CRSE_MAX_BYTE0 int true 0DQSTRACK_RLDLYRNK_CRSE_MAX_BYTE1 int true 0DQSTRACK_RLDLYRNK_CRSE_MAX_BYTE2 int true 0DQSTRACK_RLDLYRNK_CRSE_MAX_BYTE3 int true 0DQSTRACK_RLDLYRNK_CRSE_MAX_BYTE4 int true 0DQSTRACK_RLDLYRNK_CRSE_MAX_BYTE5 int true 0
Appendix B: Debugging
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DQSTRACK_RLDLYRNK_CRSE_MAX_BYTE6 int true 0DQSTRACK_RLDLYRNK_CRSE_MAX_BYTE7 int true 0DQSTRACK_RLDLYRNK_CRSE_MAX_BYTE8 int true 0DQSTRACK_RLDLYRNK_FINE_MAX_BYTE0 int true 0DQSTRACK_RLDLYRNK_FINE_MAX_BYTE1 int true 0DQSTRACK_RLDLYRNK_FINE_MAX_BYTE2 int true 0DQSTRACK_RLDLYRNK_FINE_MAX_BYTE3 int true 0DQSTRACK_RLDLYRNK_FINE_MAX_BYTE4 int true 0DQSTRACK_RLDLYRNK_FINE_MAX_BYTE5 int true 0DQSTRACK_RLDLYRNK_FINE_MAX_BYTE6 int true 0DQSTRACK_RLDLYRNK_FINE_MAX_BYTE7 int true 0DQSTRACK_RLDLYRNK_FINE_MAX_BYTE8 int true 0DQSTRACK_RLDLYRNK_CRSE_MIN_BYTE0 int true 0DQSTRACK_RLDLYRNK_CRSE_MIN_BYTE1 int true 0DQSTRACK_RLDLYRNK_CRSE_MIN_BYTE2 int true 0DQSTRACK_RLDLYRNK_CRSE_MIN_BYTE3 int true 0DQSTRACK_RLDLYRNK_CRSE_MIN_BYTE4 int true 0DQSTRACK_RLDLYRNK_CRSE_MIN_BYTE5 int true 0DQSTRACK_RLDLYRNK_CRSE_MIN_BYTE6 int true 0DQSTRACK_RLDLYRNK_CRSE_MIN_BYTE7 int true 0DQSTRACK_RLDLYRNK_CRSE_MIN_BYTE8 int true 0DQSTRACK_RLDLYRNK_FINE_MIN_BYTE0 int true 0DQSTRACK_RLDLYRNK_FINE_MIN_BYTE1 int true 0DQSTRACK_RLDLYRNK_FINE_MIN_BYTE2 int true 0DQSTRACK_RLDLYRNK_FINE_MIN_BYTE3 int true 0DQSTRACK_RLDLYRNK_FINE_MIN_BYTE4 int true 0DQSTRACK_RLDLYRNK_FINE_MIN_BYTE5 int true 0DQSTRACK_RLDLYRNK_FINE_MIN_BYTE6 int true 0DQSTRACK_RLDLYRNK_FINE_MIN_BYTE7 int true 0DQSTRACK_RLDLYRNK_FINE_MIN_BYTE8 int true 0BRAM_BISC_PQTR_ALIGN_NIBBLE0 int true 1BRAM_BISC_PQTR_ALIGN_NIBBLE1 int true 0BRAM_BISC_PQTR_ALIGN_NIBBLE2 int true 1BRAM_BISC_PQTR_ALIGN_NIBBLE3 int true 0BRAM_BISC_PQTR_ALIGN_NIBBLE4 int true 2BRAM_BISC_PQTR_ALIGN_NIBBLE5 int true 1BRAM_BISC_PQTR_ALIGN_NIBBLE6 int true 0BRAM_BISC_PQTR_ALIGN_NIBBLE7 int true 0BRAM_BISC_PQTR_ALIGN_NIBBLE8 int true 0BRAM_BISC_PQTR_ALIGN_NIBBLE9 int true 1BRAM_BISC_PQTR_ALIGN_NIBBLE10 int true 0BRAM_BISC_PQTR_ALIGN_NIBBLE11 int true 0BRAM_BISC_PQTR_ALIGN_NIBBLE12 int true 0BRAM_BISC_PQTR_ALIGN_NIBBLE13 int true 0BRAM_BISC_PQTR_ALIGN_NIBBLE14 int true 2BRAM_BISC_PQTR_ALIGN_NIBBLE15 int true 0BRAM_BISC_PQTR_ALIGN_NIBBLE16 int true 0BRAM_BISC_PQTR_ALIGN_NIBBLE17 int true 0BRAM_BISC_NQTR_ALIGN_NIBBLE0 int true 0BRAM_BISC_NQTR_ALIGN_NIBBLE1 int true 2BRAM_BISC_NQTR_ALIGN_NIBBLE2 int true 0BRAM_BISC_NQTR_ALIGN_NIBBLE3 int true 0BRAM_BISC_NQTR_ALIGN_NIBBLE4 int true 0BRAM_BISC_NQTR_ALIGN_NIBBLE5 int true 0BRAM_BISC_NQTR_ALIGN_NIBBLE6 int true 1BRAM_BISC_NQTR_ALIGN_NIBBLE7 int true 2BRAM_BISC_NQTR_ALIGN_NIBBLE8 int true 2BRAM_BISC_NQTR_ALIGN_NIBBLE9 int true 0BRAM_BISC_NQTR_ALIGN_NIBBLE10 int true 2BRAM_BISC_NQTR_ALIGN_NIBBLE11 int true 1BRAM_BISC_NQTR_ALIGN_NIBBLE12 int true 1BRAM_BISC_NQTR_ALIGN_NIBBLE13 int true 2BRAM_BISC_NQTR_ALIGN_NIBBLE14 int true 0
Appendix B: Debugging
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BRAM_BISC_NQTR_ALIGN_NIBBLE15 int true 2BRAM_BISC_NQTR_ALIGN_NIBBLE16 int true 0BRAM_BISC_NQTR_ALIGN_NIBBLE17 int true 1BRAM_BISC_PQTR_NIBBLE0 int true 200BRAM_BISC_PQTR_NIBBLE1 int true 200BRAM_BISC_PQTR_NIBBLE2 int true 202BRAM_BISC_PQTR_NIBBLE3 int true 200BRAM_BISC_PQTR_NIBBLE4 int true 202BRAM_BISC_PQTR_NIBBLE5 int true 201BRAM_BISC_PQTR_NIBBLE6 int true 200BRAM_BISC_PQTR_NIBBLE7 int true 198BRAM_BISC_PQTR_NIBBLE8 int true 199BRAM_BISC_PQTR_NIBBLE9 int true 200BRAM_BISC_PQTR_NIBBLE10 int true 200BRAM_BISC_PQTR_NIBBLE11 int true 201BRAM_BISC_PQTR_NIBBLE12 int true 200BRAM_BISC_PQTR_NIBBLE13 int true 200BRAM_BISC_PQTR_NIBBLE14 int true 201BRAM_BISC_PQTR_NIBBLE15 int true 197BRAM_BISC_PQTR_NIBBLE16 int true 201BRAM_BISC_NQTR_NIBBLE0 int true 200BRAM_BISC_NQTR_NIBBLE1 int true 197BRAM_BISC_NQTR_NIBBLE2 int true 201BRAM_BISC_NQTR_NIBBLE3 int true 202BRAM_BISC_NQTR_NIBBLE4 int true 202BRAM_BISC_NQTR_NIBBLE5 int true 201BRAM_BISC_NQTR_NIBBLE6 int true 200BRAM_BISC_NQTR_NIBBLE7 int true 201BRAM_BISC_NQTR_NIBBLE8 int true 202BRAM_BISC_NQTR_NIBBLE9 int true 202BRAM_BISC_NQTR_NIBBLE10 int true 204BRAM_BISC_NQTR_NIBBLE11 int true 204BRAM_BISC_NQTR_NIBBLE12 int true 201BRAM_BISC_NQTR_NIBBLE13 int true 205BRAM_BISC_NQTR_NIBBLE14 int true 202BRAM_BISC_NQTR_NIBBLE15 int true 202BRAM_BISC_NQTR_NIBBLE16 int true 201BRAM_BISC_NQTR_NIBBLE17 int true 202
BISC VT Tracking
The change in the relative delay through the FPGA for the DQS and DQ is monitored in theXPHY and adjustments are made to the delays to account for the change in resolution of thedelay elements. The change in the delays are recorded in the XSDB as shown in following table.
Table 124: XSDB Registers of Interest for VT Tracking
XSDB Reg Usage Signal DescriptionVTTRACK_RLDLYQTR_NIBBLE* One per nibble QTR position last read during BISC VT Tracking.
VTTRACK_RLDLYQTR_MAX_NIBBLE* One per nibble Maximum QTR value found during BISC VTTracking.
VTTRACK_RLDLYQTR_MIN_NIBBLE* One per nibble Minimum QTR value found during BISC VT Tracking.
BISC_ALIGN_PQTR_NIBBLE* One per nibble Initial 0° offset value provided by BISC at power-up.
BISC_ALIGN_NQTR_NIBBLE* One per nibble Initial 0° offset value provided by BISC at power-up.
Appendix B: Debugging
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Table 124: XSDB Registers of Interest for VT Tracking (cont'd)
XSDB Reg Usage Signal Description
BISC_PQTR_NIBBLE* One per nibble
Initial 90° offset value provided by BISC at power-up. Compute 90° value in taps by taking (BISC_PQTR– BISC_ALIGN_PQTR). To estimate tap resolutiontake (¼ of the memory clock period)/ (BISC_PQTR –BISC_ALIGN_PQTR).
BISC_NQTR_NIBBLE* One per nibble
Initial 90° offset value provided by BISC at power-up. Compute 90° value in taps by taking (BISC_PQTR– BISC_ALIGN_PQTR). To estimate tap resolutiontake (¼ of the memory clock period)/ (BISC_PQTR –BISC_ALIGN_PQTR).
This is a sample of the results for the VT Tracking XSDB debug signals:
VTTRACK_RLDLYQTR_NIBBLE0 int true 0VTTRACK_RLDLYQTR_NIBBLE1 int true 0VTTRACK_RLDLYQTR_NIBBLE2 int true 0VTTRACK_RLDLYQTR_NIBBLE3 int true 0VTTRACK_RLDLYQTR_NIBBLE4 int true 0VTTRACK_RLDLYQTR_NIBBLE5 int true 0VTTRACK_RLDLYQTR_NIBBLE6 int true 0VTTRACK_RLDLYQTR_NIBBLE7 int true 0VTTRACK_RLDLYQTR_NIBBLE8 int true 0VTTRACK_RLDLYQTR_NIBBLE9 int true 0VTTRACK_RLDLYQTR_NIBBLE10 int true 0VTTRACK_RLDLYQTR_NIBBLE11 int true 0VTTRACK_RLDLYQTR_NIBBLE12 int true 0VTTRACK_RLDLYQTR_NIBBLE13 int true 0VTTRACK_RLDLYQTR_NIBBLE14 int true 0VTTRACK_RLDLYQTR_NIBBLE15 int true 0VTTRACK_RLDLYQTR_NIBBLE16 int true 0VTTRACK_RLDLYQTR_NIBBLE17 int true 0VTTRACK_RLDLYQTR_MAX_NIBBLE0 int true 0VTTRACK_RLDLYQTR_MAX_NIBBLE1 int true 0VTTRACK_RLDLYQTR_MAX_NIBBLE2 int true 0VTTRACK_RLDLYQTR_MAX_NIBBLE3 int true 0VTTRACK_RLDLYQTR_MAX_NIBBLE4 int true 0VTTRACK_RLDLYQTR_MAX_NIBBLE5 int true 0VTTRACK_RLDLYQTR_MAX_NIBBLE6 int true 0VTTRACK_RLDLYQTR_MAX_NIBBLE7 int true 0VTTRACK_RLDLYQTR_MAX_NIBBLE8 int true 0VTTRACK_RLDLYQTR_MAX_NIBBLE9 int true 0VTTRACK_RLDLYQTR_MAX_NIBBLE10 int true 0VTTRACK_RLDLYQTR_MAX_NIBBLE11 int true 0VTTRACK_RLDLYQTR_MAX_NIBBLE12 int true 0VTTRACK_RLDLYQTR_MAX_NIBBLE13 int true 0VTTRACK_RLDLYQTR_MAX_NIBBLE14 int true 0VTTRACK_RLDLYQTR_MAX_NIBBLE15 int true 0VTTRACK_RLDLYQTR_MAX_NIBBLE16 int true 0VTTRACK_RLDLYQTR_MAX_NIBBLE17 int true 0VTTRACK_RLDLYQTR_MIN_NIBBLE0 int true 0VTTRACK_RLDLYQTR_MIN_NIBBLE1 int true 0VTTRACK_RLDLYQTR_MIN_NIBBLE2 int true 0VTTRACK_RLDLYQTR_MIN_NIBBLE3 int true 0VTTRACK_RLDLYQTR_MIN_NIBBLE4 int true 0VTTRACK_RLDLYQTR_MIN_NIBBLE5 int true 0VTTRACK_RLDLYQTR_MIN_NIBBLE6 int true 0VTTRACK_RLDLYQTR_MIN_NIBBLE7 int true 0VTTRACK_RLDLYQTR_MIN_NIBBLE8 int true 0
Appendix B: Debugging
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VTTRACK_RLDLYQTR_MIN_NIBBLE9 int true 0VTTRACK_RLDLYQTR_MIN_NIBBLE10 int true 0VTTRACK_RLDLYQTR_MIN_NIBBLE11 int true 0VTTRACK_RLDLYQTR_MIN_NIBBLE12 int true 0VTTRACK_RLDLYQTR_MIN_NIBBLE13 int true 0VTTRACK_RLDLYQTR_MIN_NIBBLE14 int true 0VTTRACK_RLDLYQTR_MIN_NIBBLE15 int true 0VTTRACK_RLDLYQTR_MIN_NIBBLE16 int true 0VTTRACK_RLDLYQTR_MIN_NIBBLE17 int true 0BRAM_BISC_PQTR_ALIGN_NIBBLE0 int true 1BRAM_BISC_PQTR_ALIGN_NIBBLE1 int true 0BRAM_BISC_PQTR_ALIGN_NIBBLE2 int true 1BRAM_BISC_PQTR_ALIGN_NIBBLE3 int true 0BRAM_BISC_PQTR_ALIGN_NIBBLE4 int true 2BRAM_BISC_PQTR_ALIGN_NIBBLE5 int true 1BRAM_BISC_PQTR_ALIGN_NIBBLE6 int true 0BRAM_BISC_PQTR_ALIGN_NIBBLE7 int true 0BRAM_BISC_PQTR_ALIGN_NIBBLE8 int true 0BRAM_BISC_PQTR_ALIGN_NIBBLE9 int true 1BRAM_BISC_PQTR_ALIGN_NIBBLE10 int true 0BRAM_BISC_PQTR_ALIGN_NIBBLE11 int true 0BRAM_BISC_PQTR_ALIGN_NIBBLE12 int true 0BRAM_BISC_PQTR_ALIGN_NIBBLE13 int true 0BRAM_BISC_PQTR_ALIGN_NIBBLE14 int true 2BRAM_BISC_PQTR_ALIGN_NIBBLE15 int true 0BRAM_BISC_PQTR_ALIGN_NIBBLE16 int true 0BRAM_BISC_PQTR_ALIGN_NIBBLE17 int true 0BRAM_BISC_NQTR_ALIGN_NIBBLE0 int true 0BRAM_BISC_NQTR_ALIGN_NIBBLE1 int true 2BRAM_BISC_NQTR_ALIGN_NIBBLE2 int true 0BRAM_BISC_NQTR_ALIGN_NIBBLE3 int true 0BRAM_BISC_NQTR_ALIGN_NIBBLE4 int true 0BRAM_BISC_NQTR_ALIGN_NIBBLE5 int true 0BRAM_BISC_NQTR_ALIGN_NIBBLE6 int true 1BRAM_BISC_NQTR_ALIGN_NIBBLE7 int true 2BRAM_BISC_NQTR_ALIGN_NIBBLE8 int true 2BRAM_BISC_NQTR_ALIGN_NIBBLE9 int true 0BRAM_BISC_NQTR_ALIGN_NIBBLE10 int true 2BRAM_BISC_NQTR_ALIGN_NIBBLE11 int true 1BRAM_BISC_NQTR_ALIGN_NIBBLE12 int true 1BRAM_BISC_NQTR_ALIGN_NIBBLE13 int true 2BRAM_BISC_NQTR_ALIGN_NIBBLE14 int true 0BRAM_BISC_NQTR_ALIGN_NIBBLE15 int true 2BRAM_BISC_NQTR_ALIGN_NIBBLE16 int true 0BRAM_BISC_NQTR_ALIGN_NIBBLE17 int true 1BRAM_BISC_PQTR_NIBBLE0 int true 200BRAM_BISC_PQTR_NIBBLE1 int true 200BRAM_BISC_PQTR_NIBBLE2 int true 202BRAM_BISC_PQTR_NIBBLE3 int true 200BRAM_BISC_PQTR_NIBBLE4 int true 202BRAM_BISC_PQTR_NIBBLE5 int true 201BRAM_BISC_PQTR_NIBBLE6 int true 200BRAM_BISC_PQTR_NIBBLE7 int true 198BRAM_BISC_PQTR_NIBBLE8 int true 199BRAM_BISC_PQTR_NIBBLE9 int true 200BRAM_BISC_PQTR_NIBBLE10 int true 200BRAM_BISC_PQTR_NIBBLE11 int true 201BRAM_BISC_PQTR_NIBBLE12 int true 200BRAM_BISC_PQTR_NIBBLE13 int true 200BRAM_BISC_PQTR_NIBBLE14 int true 201BRAM_BISC_PQTR_NIBBLE15 int true 197BRAM_BISC_PQTR_NIBBLE16 int true 201BRAM_BISC_NQTR_NIBBLE0 int true 200
Appendix B: Debugging
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BRAM_BISC_NQTR_NIBBLE1 int true 197BRAM_BISC_NQTR_NIBBLE2 int true 201BRAM_BISC_NQTR_NIBBLE3 int true 202BRAM_BISC_NQTR_NIBBLE4 int true 202BRAM_BISC_NQTR_NIBBLE5 int true 201BRAM_BISC_NQTR_NIBBLE6 int true 200BRAM_BISC_NQTR_NIBBLE7 int true 201BRAM_BISC_NQTR_NIBBLE8 int true 202BRAM_BISC_NQTR_NIBBLE9 int true 202BRAM_BISC_NQTR_NIBBLE10 int true 204BRAM_BISC_NQTR_NIBBLE11 int true 204BRAM_BISC_NQTR_NIBBLE12 int true 201BRAM_BISC_NQTR_NIBBLE13 int true 205BRAM_BISC_NQTR_NIBBLE14 int true 202BRAM_BISC_NQTR_NIBBLE15 int true 202BRAM_BISC_NQTR_NIBBLE16 int true 201BRAM_BISC_NQTR_NIBBLE17 int true 202
Debugging Data Errors
General Checks
As with calibration error debug, the General Checks section should be reviewed. Strict adherenceto proper board design is critical in working with high speed memory interfaces. Violation ofthese general checks is often the root cause of data errors.
Related Information
General Checks
Replicating Data Errors Using the Advanced Traffic Generator
When data errors are seen during normal operation, the Memory IP Advanced Traffic Generator(ATG) should be used to replicate the error. The ATG is a verified solution that can be configuredto send a wide range of data, address, and command patterns. It additionally presents debugstatus information for general memory traffic debug post calibration. The ATG stores the writedata and compares it to the read data. This allows comparison of expected and actual data whenerrors occur. This is a critical step in data error debug as this section will go through in detail.
ATG Setup
The default ATG configuration exercises predefined traffic instructions which are included in themem_v1_2_tg_instr_bram.sv module. To move away from the default configuration and usethe ATG for data error debug, use the provided VIO and ILA cores that are generated with theexample design.
Appendix B: Debugging
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Enable traffic generator to proceed from "START"state to "LOAD" state after calibration completes.If you do not plan to program instruction tableNOR PRBS data seed, tie this signal to 1'b1.If you plan to program instruction table OR PRBSdata seed, set this bit to 0 during reset. Afterreset deassertion and done with instruction/seedprogramming, set this bit to 1 to start trafficgenerator.
vio_tg_rst I 1
Reset traffic generator (synchronous reset, levelsensitive). If there is outstanding traffic inmemory pipeline, assert this signal long enoughuntil all outstanding transactions havecompleted.
vio_tg_restart
I 1
Restart traffic generator after traffic generationis complete, paused, or stopped with error (levelsensitive).If there is outstanding traffic in memory pipeline,assert this signal long enough until alloutstanding transactions have completed.
vio_tg_pause I 1 Pause traffic generator (level sensitive)
vio_tg_err_chk_en I 1If enabled, stop upon first error detected. Readtest is performed to determine whether "READ"or "WRITE" error occurred. If not enabled,continue traffic without stop.
vio_tg_err_clearI 1
Clear all errors excluding sticky error bit (positiveedge sensitive). Only use this signal whenvio_tg_status_state is either TG_INSTR_ERRDONEor TG_INSTR_PAUSE.
vio_tg_err_clear_all I 1Clear all errors including sticky error bit (positiveedge sensitive). Only use this signal whenvio_tg_status_state is either TG_INSTR_ERRDONEor TG_INSTR_PAUSE.
vio_tg_err_continue I 1Continue traffic after error(s) atTG_INSTR_ERRDONE state (positive edgesensitive).
Instruction Programming
Table 126: Instruction Programming
Instruction Programming I/O Width Description
vio_tg_direct_instr_en I 1
0: Traffic Table Mode – Traffic Generator usestraffic patterns programmed in 32-entry traffictable.1: Direct Instruction Mode – Traffic Generatoruses current traffic pattern presented at VIOinterface.
vio_tg_instr_program_en I 1 Enable instruction table programming (levelsensitive)
vio_tg_instr_num I 5 Instruction number to be programmed
Appendix B: Debugging
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Address mode to be programmed.• 0: LINEAR (with user defined start address)• 1: PRBS (PRBS supported range from 8 to 34
based on address width)• 2: WALKING1• 3: WALKING0• [4:15]: Reserved
vio_tg_instr_data_mode I 4
Data mode to be programmed.• 0: LINEAR• 1: PRBS (PRBS supported 8, 10, 23)• 2: WALKING1• 3: WALKING0• 4: HAMMER1• 5: HAMMER0• 6: Block RAM• 7: CAL_CPLX (Must be programmed along
with victim mode CAL_CPLX)• [8:15]: Reserved
vio_tg_instr_rw_mode I 4
• 0: Read Only (No data check)• 1: Write Only (No data check)• 2: Write / Read (Read performs after Write
and data value is checked against expectedwrite data)
• 3: Write Once and Read forever (Data checkon Read data)
• [4:15]: Reserved
vio_tg_instr_rw_submode I 2
Read/Write sub-mode to be programmed.This is a sub-mode option whenvio_tg_instr_rw_mode is set to "WRITE_READ"mode• 0: WRITE_READ (Send all Write commands
follow by Read commands defined in theinstruction)
• 1: WRITE_READ_SIMULTANEOUSLY (SendWrite and Read commands pseudo-randomly)
Note: Write is always ahead of Read.• [2:3] : Reserved
Appendix B: Debugging
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Victim mode to be programmed.One victim bit could be programmed usingglobal register vio_tg_victim_bit. The rest of thebits on signal bus are considered to beaggressors.The following program options define aggressorbehavior:• 0: NO_VICTIM• 1: HELD1 (All aggressor signals held at 1)• 2: HELD0 (All aggressor signals held at 0)• 3: NONINV_AGGR (All aggressor signals are
same as victim)• 4: INV_AGGR (All aggressor signals are
inversion of victim)• 5: DELAYED_AGGR (All aggressor signals are
delayed version of victim. Number of cycle ofdelay is programmed atvio_tg_victim_aggr_delay)
• 6: DELAYED_VICTIM (Victim signal is delayedversion of all aggressors)
• 7: CAL_CPLX (Complex Calibration patternmust be programed along with Data ModeCAL_CPLX)
vio_tg_instr_victim_aggr_delay I 5
Define aggressor/victim pattern to be N-delaycycle of victim/aggressor.It is used when victim mode "DELAY_AGGR" or"DELAY VICTIM" mode is used in traffic pattern
vio_tg_instr_victim_select I 3
Victim bit behavior programmed.• 0: VICTIM_EXTERNAL (Use Victim bit provided
in vio_tg_glb_victim_bit)• 1: VICTIM_ROTATE4 (Victim bit rotates from
Bit[0] to Bit[3] for every Nibble)• 2: VICTIM_ROTATE8 (Victim bit rotates from
Bit[0] to Bit[7] for every byte)• 3: VICTIM_ROTATE_ALL (Victim bit rotates
through all bits)• [4:7]: Reserved
vio_tg_instr_num_of_iter I 32Number of Read/Write commands to issue(number of issue must be > 0 for each instructionprogrammed)
vio_tg_instr_m_nops_btw_n_burst_m I 10
M: Number of NOP cycles in between Read/Writecommands at User interface at generalinterconnect clock.N: Number of Read/Write commands beforeNOP cycle insertion at User interface at generalinterconnect clock.
vio_tg_instr_m_nops_btw_n_burst_n I 32
M: Number of NOP cycles in between Read/Writecommands at User interface at generalinterconnect clock.N: Number of Read/Write commands beforeNOP cycle insertion at User interface at generalinterconnect clock.
Appendix B: Debugging
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Next instruction to run.To end traffic, next instruction should point atEXIT instruction.• 6’b000000-6’b011111 – valid instruction• 6’b1????? – EXIT instruction
Status Registers
Table 127: Status Registers
Status Registers I/O Width Descriptionvio_tg_status_state O 4 Traffic Generator state machine state
vio_tg_status_err_bit_valid O 1 Intermediate error detected. Used astrigger to detect read error.
vio_tg_status_err_bit O APP_DATA_WIDTH Intermediate error bit mismatch. Bitwisemismatch pattern.
vio_tg_status_err_addr O APP_DATA_WIDTH Intermediate error address. Addresslocation of failed read.
vio_tg_status_exp_bit_valid O 1 Expected read data valid
vio_tg_status_exp_bit O APP_DATA_WIDTH Expected read data
vio_tg_status_read_bit_valid O 1 Memory read data valid
vio_tg_status_read_bit O APP_DATA_WIDTH Memory read data
vio_tg_status_first_err_bit_valid O 1
If vio_tg_err_chk_en is set to 1,first_err_bit_valid is set to 1 when firstmismatch error is encountered.This register is not overwritten untilvio_tg_err_clear, vio_tg_err_continue,vio_tg_restart is triggered.
vio_tg_status_first_err_bit O APP_DATA_WIDTHIf vio_tg_status_first_err_bit_valid is set to1, error mismatch bit pattern is stored inthis register.
vio_tg_status_first_err_addr O APP_DATA_WIDTH If vio_tg_status_first_err_bit_valid is set to1, error address is stored in this register.
vio_tg_status_first_exp_bit_valid O 1If vio_tg_err_chk_en is set to 1, thisrepresents expected read data valid whenfirst mismatch error is encountered.
vio_tg_status_first_exp_bit O APP_DATA_WIDTHIf vio_tg_status_first_exp_bit_valid is set to1, expected read data is stored in thisregister.
vio_tg_status_first_read_bit_valid O 1If vio_tg_err_chk_en is set to 1, thisrepresents read data valid when firstmismatch error is encountered.
vio_tg_status_first_read_bit O APP_DATA_WIDTHIf vio_tg_status_first_read_bit_valid is setto 1, read data from memory is stored inthis register.
vio_tg_status_err_bit_sticky_valid O 1Accumulated error mismatch valid overtime. This register is reset byvio_tg_err_clear, vio_tg_err_continue,vio_tg_restart.
Appendix B: Debugging
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vio_tg_status_err_bit_sticky O APP_DATA_WIDTHIf vio_tg_status_err_bit_sticky_valid is setto 1, this represents accumulated errorbit.
vio_tg_status_err_type_valid O 1
If vio_tg_err_chk_en is set to 1, read test isperformed upon the first mismatch error.Read test returns error type of either"READ" or "WRITE" error. This registerstores valid status of read test error type.
vio_tg_status_err_type O 1
If vio_tg_status_err_type_valid is set to 1,this represents error type result fromread test.• 0: Write Error• 1: Read Error
vio_tg_status_done O 1
All traffic programmed completes.
Note: If infinite loop is programmed,vio_tg_status_done does not assert.
vio_tg_status_wr_done O 1 This signal pulses after a WRITE-READmode instruction completes.
vio_tg_status_watch_dog_hang O 1Watchdog hang. This register is set to 1 ifthere is no READ/WRITE command sentor no READ data return for a period oftime (defined in tg_param.vh).
compare_error O 1Accumulated error mismatch valid overtime. This register resets byvio_tg_err_clear, vio_tg_err_continue,vio_tg_restart.
ATG Debug Programming
The ATG provides three methods for traffic pattern programming:
This document assumes debug using “Direct Instruction through VIO.” The same concepts extendto both “Instruction Block RAM” and “Program Instruction Table.” “Direct Instruction throughVIO” is enabled using vio_tg_direct_instr_en. After vio_tg_direct_instr_en is setto 1, all of the traffic instruction fields can be driven by the targeted traffic instruction.
ATG identifies if a traffic error is a Read or Write Error when vio_tg_err_chk_en is set to 1.Assume EXP_WR_DATA is the expected write data. After the first traffic error is seen from a read(with a value of EXP_WR_DATA), ATG issues multiple read commands to the failed memoryaddress. If all reads return data EXP_WR_DATA, ATG classifies the error as a WRITE_ERROR(0).Otherwise, ATG classifies the error as READ_ERROR(1). ATG also tracks the first error bit, firsterror address seen.
Example 1: The following VIO setting powers on Read/Write Error Type check.
.vio_tg_err_chk_en (1'b1), // Powers on Error Type Check
.vio_tg_direct_instr_en (1'b1), // Powers on Direct Instruction Mode.vio_tg_instr_num (5'b00000),.vio_tg_instr_addr_mode (TG_PATTERN_MODE_LINEAR),.vio_tg_instr_data_mode (TG_PATTERN_MODE_PRBS),.vio_tg_instr_rw_mode (TG_RW_MODE_WRITE_READ),.vio_tg_instr_rw_submode (2'b00),.vio_tg_instr_victim_mode (TG_VICTIM_MODE_NO_VICTIM),.vio_tg_instr_victim_select (3'b000),.vio_tg_instr_victim_aggr_delay (5'd0),.vio_tg_instr_num_of_iter (32'd1000),.vio_tg_instr_m_nops_btw_n_burst_m (10'd0),.vio_tg_instr_m_nops_btw_n_burst_n (32'd10),.vio_tg_instr_nxt_instr (6’d0),
Appendix B: Debugging
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The following figure shows a Write Error waveform. Whenvio_tg_status_err_type_valid is 1, vio_tg_status_err_type shows a WRITEERROR (0). When vio_tg_status_first_err_bit_valid is 1, the following occurs:
• vio_tg_status_first_err_bit, 0x8 is the corrupted bit
• vio_tg_first_err_addr shows the address with the corrupted data as 0x678
Figure 109: VIO Write Error Waveform
The following figure shows a Read Error waveform. When vio_tg_status_err_type_validis 1, vio_tg_status_err_type shows a READ ERROR (0). Whenvio_tg_status_first_err_bit_valid is 1, the following occurs:
• vio_tg_status_first_err_bit, 0x60 is the corrupted bit
• vio_tg_first_err_addr shows the address with the corrupted data as 0x1B0
Appendix B: Debugging
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ATG Debug First Error Bit/First Error Address/Sticky Error Bit
When vio_tg_err_chk_en is set to 1, ATG stops after the first error. Whenvio_tg_err_chk_en is set to 0, ATG does not stop after the first error and would track errorcontinuously using vio_tg_status_err_bit_valid/vio_tg_status_err_bit/vio_tg_status_err_addr.
The signals vio_tg_status_err_bit_sticky_valid/vio_tg_status_err_bit_sticky accumulate all data bit(s) with error(s) seen.
Example 2: The following VIO setting powers off Read/Write Error Type check:
.vio_tg_err_chk_en (1'b0), // Powers on Error Type Check
.vio_tg_direct_instr_en (1'b1), // Powers on Direct Instruction Mode.vio_tg_instr_num (5'b00000),.vio_tg_instr_addr_mode (TG_PATTERN_MODE_LINEAR),.vio_tg_instr_data_mode (TG_PATTERN_MODE_PRBS),.vio_tg_instr_rw_mode (TG_RW_MODE_WRITE_READ),.vio_tg_instr_rw_submode (2'b00),.vio_tg_instr_victim_mode (TG_VICTIM_MODE_NO_VICTIM),.vio_tg_instr_victim_select (3'b000),.vio_tg_instr_victim_aggr_delay (5'd0),.vio_tg_instr_num_of_iter (32'd1000),.vio_tg_instr_m_nops_btw_n_burst_m (10'd0),.vio_tg_instr_m_nops_btw_n_burst_n (32'd10),.vio_tg_instr_nxt_instr (6’d0),
Appendix B: Debugging
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The following figure shows six addresses with read error (note that this is the same example aswas used with “Write Error” earlier. “Write Error” is not presented becausevio_tg_err_chk_en is disabled here): vio_tg_status_err_bit_valid is asserted sixtimes.
For each assertion, the corresponding bit error is presented at vio_tg_status_err_bit.After five assertions in vio_tg_status_err_bit_valid (yellow marker),vio_tg_status_err_bit_sticky shows bits 0x1E (binary 11110) has bit corruption.
Figure 111: VIO Read Error Waveform
ATG Debug Watchdog Hang
ATG expects the application interface to accept a command within a certain wait time. ATG alsolooks for the application interface to return data within a certain wait time after a read commandis issued. If either case is violated, ATG flags a Watchdog Hang.
When WatchDogHang is asserted, if vio_tg_status_state is in “*Wait” states, ATG iswaiting for read data return. If vio_tg_status_state is in “Exe” state, ATG is waiting for theapplication interface to accept the next command.
Example 3: The following example shows that ATG asserts WatchDogHang. This example sharesthe same VIO control setting as Example 2. In this example, ATG vio_tg_status_stateshows a “DNWait” state. Hence, ATG is waiting for read data return.
Appendix B: Debugging
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To further debug, vio_tg_instr_data_mode is updated to Linear data for betterunderstanding in data return sequence.
.vio_tg_err_chk_en (1'b0), // Powers on Error Type Check
.vio_tg_direct_instr_en (1'b1), // Powers on Direct Instruction Mode.vio_tg_instr_num (5'b00000),.vio_tg_instr_addr_mode (TG_PATTERN_MODE_LINEAR),.vio_tg_instr_data_mode (TG_PATTERN_MODE_LINEAR),.vio_tg_instr_rw_mode (TG_RW_MODE_WRITE_READ),.vio_tg_instr_rw_submode (2'b00),.vio_tg_instr_victim_mode (TG_VICTIM_MODE_NO_VICTIM),.vio_tg_instr_victim_select (3'b000),.vio_tg_instr_victim_aggr_delay (5'd0),.vio_tg_instr_num_of_iter (32'd1000),.vio_tg_instr_m_nops_btw_n_burst_m (10'd0),.vio_tg_instr_m_nops_btw_n_burst_n (32'd10),.vio_tg_instr_nxt_instr (6’d0),
With Linear data, the following figure shows that when an error is detected, read data(vio_tg_status_read_bit) is one request ahead of expected data(vio_tg_status_exp_bit). One possibility is read command with address 0x1B0 is dropped.Hence, the next returned data with read address 0x1B8 is being compared against the expecteddata of read address 0x1B0.
Appendix B: Debugging
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Figure 113: ATG Debug Watchdog Hang Waveform with Linear Data
Isolating the Data Error
Using either the Advanced Traffic Generator or the user design, the first step in data error debugis to isolate when and where the data errors occur. To perform this, the expected data and actualdata must be known and compared. Looking at the data errors, the following should be identified:
• Are the errors bit or byte errors?
○ Are errors seen on data bits belonging to certain DQS groups?
○ Are errors seen on specific DQ bits?
• Is the data shifted, garbage, swapped, etc.?
• Are errors seen on accesses to certain addresses, banks, or ranks of memory?
○ Designs that can support multiple varieties of DIMM modules, all possible address andbank bit combinations should be supported.
• Do the errors only occur for certain data patterns or sequences?
○ This can indicate a shorted or open connection on the PCB. It can also indicate an SSO orcrosstalk issue.
• Determine the frequency and reproducibility of the error
○ Does the error occur on every calibration/reset?
○ Does the error occur at specific temperature or voltage conditions?
• Determine if the error is correctable
○ Rewriting, rereading, resetting, and recalibrating.
Appendix B: Debugging
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The next step is to isolate whether the data corruption is due to writes or reads.
Determining If a Data Error is Due to the Write or Read
Determining whether a data error is due to the write or the read can be difficult because if writesare the cause, read back of the data is bad as well. In addition, issues with control or addresstiming affect both writes and reads.
Some experiments that can help to isolate the issue include:
• If the errors are intermittent, issue a small initial number of writes, followed by continuousreads from those locations. If the reads intermittently yield bad data, there is a potential readissue. If the reads always yield the same (wrong) data, there is a write issue.
• Using high quality probes and scope, capture the write at the memory and the read at theFPGA to view data accuracy, appropriate DQS-to-DQ phase relationship, and signal integrity.To ensure the appropriate transaction is captured on DQS and DQ, look at the initial transitionon DQS from 3-state to active. During a Write, DQS does not have a low preamble. During aread, the DQS has a low preamble.
• Analyze Read Timing:
○ Check the PQTR/NQTR values after calibration. Look for variations between PQTR/NQTRvalues. PQTR/NQTR values should be very similar for DQs in the same DQS group.
Analyzing Read and Write Margin
The XSDB output can be used to determine the available read and write margins duringcalibration. Starting with 2014.3, an XSDB Memory IP GUI is available through the HardwareManager to view the read calibration margins for both rising edge clock and failing edge clock.The margins are provided for both simple and complex pattern calibration. The complex patternresults are more representative of the margin expected during post calibration traffic.
Appendix B: Debugging
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When data errors occur, the results of calibration should be analyzed to ensure that the resultsare expected and accurate. Each of the debugging calibration sections notes what the expectedresults are such as how many edges should be found, how much variance across byte groupsshould exist, etc. Follow these sections to capture and analyze the calibration results.
Calibration Times
Calibration time depends on a number of factors, such as:
• General Interconnect Clock Frequency
• Number of DDR Ranks
• Memory Width
• Board Trace Lengths
Determining Window Size in ps
To determine the window size in ps, first calculate the tap resolution and then multiply theresolution by the number of taps found in the read and/or write window. The tap resolutionvaries across process (down to variance at each nibble within a part).
However, within a specific process, each tap within the delay chain is the same preciseresolution.
1. To compute the 90° offset in taps, take (BISC_PQTR – BISC_ALIGN_PQTR).
2. To estimate tap resolution, take (1/4 of the memory clock period) / (BISC_PQTR –BISC_ALIGN_PQTR).
3. The same then applies for NQTR.
BISC is run on a per nibble basis for both PQTR and NQTR. The write tap results are given on aper byte basis. To use the BISC results to determine the write window, take the average of theBISC PQTR and NQTR results for each nibble. For example, ((BISC_NQTR_NIBBLE0 +BISC_NQTR_NIBBLE1 + BISC_PQTR_NIBBLE0 + BISC_PQTR_NIBBLE1) / 4).
Conclusion
If this document does not help to resolve calibration or data errors, create a WebCase withXilinxTechnical Support (see related information). Attach all of the captured waveforms, XSDB anddebug signal results, and the details of your investigation and analysis.
Related Information
Technical Support
Appendix B: Debugging
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Xilinx ResourcesFor support resources such as Answers, Documentation, Downloads, and Forums, see XilinxSupport.
Documentation Navigator and Design HubsXilinx® Documentation Navigator (DocNav) provides access to Xilinx documents, videos, andsupport resources, which you can filter and search to find information. To open DocNav:
• From the Vivado® IDE, select Help → Documentation and Tutorials.
• On Windows, select Start → All Programs → Xilinx Design Tools → DocNav.
• At the Linux command prompt, enter docnav.
Xilinx Design Hubs provide links to documentation organized by design tasks and other topics,which you can use to learn key concepts and address frequently asked questions. To access theDesign Hubs:
• In DocNav, click the Design Hubs View tab.
• On the Xilinx website, see the Design Hubs page.
Note: For more information on DocNav, see the Documentation Navigator page on the Xilinx website.
ReferencesThese documents provide supplemental material useful with this guide:
Appendix C: Additional Resources and Legal Notices
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Debugging Read DQS to DQ/DBI Centering ComplexFailures
Added section.
Debugging Write DQS to DQ/DBI Centering ComplexFailures
Added section.
Analyzing Read and Write Margin Updated figures.
09/24/2021 Version 1.0
General updates Editorial updates only. No technical content updates.
12/04/2020 Version 1.0
Initial release. N/A
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Appendix C: Additional Resources and Legal Notices
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AUTOMOTIVE PRODUCTS (IDENTIFIED AS "XA" IN THE PART NUMBER) ARE NOTWARRANTED FOR USE IN THE DEPLOYMENT OF AIRBAGS OR FOR USE IN APPLICATIONSTHAT AFFECT CONTROL OF A VEHICLE ("SAFETY APPLICATION") UNLESS THERE IS ASAFETY CONCEPT OR REDUNDANCY FEATURE CONSISTENT WITH THE ISO 26262AUTOMOTIVE SAFETY STANDARD ("SAFETY DESIGN"). CUSTOMER SHALL, PRIOR TO USINGOR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE PRODUCTS, THOROUGHLY TESTSUCH SYSTEMS FOR SAFETY PURPOSES. USE OF PRODUCTS IN A SAFETY APPLICATIONWITHOUT A SAFETY DESIGN IS FULLY AT THE RISK OF CUSTOMER, SUBJECT ONLY TOAPPLICABLE LAWS AND REGULATIONS GOVERNING LIMITATIONS ON PRODUCTLIABILITY.
