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Introduction to VHDL

VHDLVHDL

Main topics:Main topics:

s Circuit design based on VHDLCircuit design based on VHDL

s VHDL basicsVHDL basicss Advanced VHDL language structuresAdvanced VHDL language structures

s Circuit examplesCircuit examples

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Shortly About the VHDLShortly About the VHDL

s VHDLVHDL is an acronym of VHSIC Hardware Descriptionis an acronym of VHSIC Hardware DescriptionLanguageLanguage

s VHSICVHSIC is an acronym of Very High Speed Integratedis an acronym of Very High Speed Integrated

CircuitsCircuitss A Formal Language for Specifying the Behavior andA Formal Language for Specifying the Behavior and

Structure of a Digital CircuitStructure of a Digital Circuit

s Allows Top-Down DesignAllows Top-Down Design

s Used to model digital system at many levels ofUsed to model digital system at many levels ofabstraction( algorithmic level to gate level)abstraction( algorithmic level to gate level)

s Complexity simple gate to complete digital electronicComplexity simple gate to complete digital electronicsystem or anything in between.system or anything in between.

s Digital system can be described hierarchically.Digital system can be described hierarchically.

s Timing can also be modeled in the same description.Timing can also be modeled in the same description.

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VHDL -INTRODUCTIONVHDL -INTRODUCTION

s Vhdl integrated amalgamation of the following languagesVhdl integrated amalgamation of the following languages

--sequential language+--sequential language+

--concurrent language+--concurrent language+

--netlist language+--netlist language+

--timing specifications+--timing specifications+

--waveform generation language--waveform generation language

allows to model the system as interconnection of components.allows to model the system as interconnection of components.

Defines the syntax ,clear simulation semantics for each language construct.Defines the syntax ,clear simulation semantics for each language construct.

--model can be verified using VHDL simulator--model can be verified using VHDL simulator--strongly typed language.--strongly typed language.

--sequential language part-ADA pgming language.--sequential language part-ADA pgming language.

--subset sufficient to model most applications--subset sufficient to model most applications

--complete language has sufficient power to capture the description of the--complete language has sufficient power to capture the description of the

most complex chips to complete electronic system.most complex chips to complete electronic system.

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VHDL DevelopmentVHDL Development

s Initial objective was modeling only and thus only aInitial objective was modeling only and thus only a

simulator was envisagedsimulator was envisaged

s Subsequently tools for VHDL synthesis were developedSubsequently tools for VHDL synthesis were developed

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HDL RequirementsHDL Requirements

s AbstractionAbstraction

s ModularityModularity

s ConcurrencyConcurrency

s

HierarchyHierarchy

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AbstractionAbstraction

VHDL supports description of components as well as systems at various levels of abstractionVHDL supports description of components as well as systems at various levels of abstraction

s Gate and component delaysGate and component delays

s Clock cyclesClock cycles

s Abstract behavior without any notion of delaysAbstract behavior without any notion of delays

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ModularityModularity

s Every component in VHDL is referred to as an entity and has a clear interfaceEvery component in VHDL is referred to as an entity and has a clear interface

s The interface is called an entity declarationThe interface is called an entity declaration

s The internals of the component are referred to as the architecture declarationThe internals of the component are referred to as the architecture declaration

s There can be multiple architectures at even different levels of abstraction associated with the sameThere can be multiple architectures at even different levels of abstraction associated with the same

entityentity

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constructsconstructs

used to express concurrent or sequential behavior of digitalused to express concurrent or sequential behavior of digital

system with or without timing specs.system with or without timing specs.

Test waveforms can be generatedTest waveforms can be generated

Combination of constructs provides comprehensiveCombination of constructs provides comprehensive

description of the system in a single model.description of the system in a single model.

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VHDL for Simulation & SynthesisVHDL for Simulation & Synthesis

Test Vector

Generator

A Series of

Refined

Models

Executable

Specification

Test

Vectors

Results,

Errors=

Final Chip

Model

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VHDL requirements for HW DescriptionVHDL requirements for HW Description

s Behavioral models =>Behavioral models =>

Combinatorial & Sequential LogicCombinatorial & Sequential Logic

RTL modelsRTL models

s Structural modelsStructural models

s Timing modelsTiming models

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Requirements for VHDL Synthesis ToolsRequirements for VHDL Synthesis Tools

s Pre- & post synthesis behavior should be identicalPre- & post synthesis behavior should be identical

s Synthesis should be efficient =>Synthesis should be efficient =>

Requires interaction with place & route toolsRequires interaction with place & route tools

Logic SynthesisLogic Synthesis

FSM SynthesisFSM Synthesis

Area & Timing OptimizationArea & Timing Optimization

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New possibilitiesNew possibilities

s VHDL frees the designer from having to use von NeumannVHDL frees the designer from having to use von Neumann

structuresstructures

(Neumann Jnos = John von Neumann)(Neumann Jnos = John von Neumann)

s It allows him to work with real concurrency instead ofIt allows him to work with real concurrency instead ofsequential machinessequential machines

s This opens up completely new possibilities for the designerThis opens up completely new possibilities for the designer

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Reasons for using VHDLReasons for using VHDL

s Shorter development times for electronic designShorter development times for electronic design

s Simpler maintenanceSimpler maintenance

s Traditional way:Traditional way: schematic designschematic design

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Origin of the VHDLOrigin of the VHDL

s VHDL originated in the early 1980sVHDL originated in the early 1980s

TThe American Department of Defense initiated the development ofhe American Department of Defense initiated the development of

VHDL in the early 1980sVHDL in the early 1980s

because the US military needed a standardized method of describingbecause the US military needed a standardized method of describing

electronic systemselectronic systems

s VHDL was standardized in 1987 by the IEEEVHDL was standardized in 1987 by the IEEE

s It is now accepted as one of the most important standardIt is now accepted as one of the most important standard

languages forlanguages for

specifyingspecifying

verifyingverifying

designing of electronicsdesigning of electronics

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StandardizationStandardization 11

s IEEE standard specification language (IEEE 1076-1993)IEEE standard specification language (IEEE 1076-1993)for describing digital hardware used by industry worldwidefor describing digital hardware used by industry worldwide

s VHDL enables hardware modeling from the gate level toVHDL enables hardware modeling from the gate level to

the system levelthe system level

s All the major tool manufacturers now support the VHDLAll the major tool manufacturers now support the VHDL

standardstandard

s VHDL is now a standardized language, with the advantageVHDL is now a standardized language, with the advantage

that it ithat it iss easy to move VHDL code between differenteasy to move VHDL code between differentcommercial platforms (tools)commercial platforms (tools)

=> VHDL code is interchangeable among the different tools=> VHDL code is interchangeable among the different tools

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s VHDL is an acronym of VHSIC Hardware DescriptionVHDL is an acronym of VHSIC Hardware DescriptionLanguageLanguage

s VHSIC is an acronym of Very High Speed IntegratedVHSIC is an acronym of Very High Speed Integrated

CircuitsCircuits

s All the major tool manufacturers now support the VHDLAll the major tool manufacturers now support the VHDLstandardstandard

s VHDL is now a standardized language, with the advantageVHDL is now a standardized language, with the advantage

that it it easy to move VHDL code between differentthat it it easy to move VHDL code between different

commercial platforms (tools)commercial platforms (tools)=> VHDL code is interchangeable among the different tools=> VHDL code is interchangeable among the different tools

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s It was the American Department of Defense which initiatedIt was the American Department of Defense which initiated

the development of VHDL in the early 1980s because the USthe development of VHDL in the early 1980s because the US

military needed a standardized method of describing electronicmilitary needed a standardized method of describing electronic

systemssystems

s VHDL was standardized in 1987 by the IEEEVHDL was standardized in 1987 by the IEEE IEEE Std-1076-1987

s ANSI Standard in 1988

s Added Support for RTL Design

VITAL: VHDL Initiative Towards ASIC Library

s Revised version in 1993

IEEE Std-1076-1993

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s 1995:1995:

numeric_std/bit: IEEE-1076.3numeric_std/bit: IEEE-1076.3

VITAL: IEEE-1076.4VITAL: IEEE-1076.4

s 1999: IEEE-1076.1 (VHDL-AMS )1999: IEEE-1076.1 (VHDL-AMS )

s 2000:2000:

IEEE-1076-2000IEEE-1076-2000

IEEE-1076.1-2000 (VITAL-2000, SDF 4.0)IEEE-1076.1-2000 (VITAL-2000, SDF 4.0)

s Added mixed-signal support to VHDL in 2001 ->

VHDL-AMS

IEEE Std-1076.1-2001

s 2002: IEEE-1076-20022002: IEEE-1076-2002

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ToolsTools

s Good VHDL tools, and VHDL simulators in particular,Good VHDL tools, and VHDL simulators in particular,

have also been developed for PCshave also been developed for PCs

s Prices have fallen dramatically, enabling smallerPrices have fallen dramatically, enabling smaller

companies to use VHDL, toocompanies to use VHDL, toos There are also PC synthesis tools, primarily for FPGAs andThere are also PC synthesis tools, primarily for FPGAs and

EPLDsEPLDs

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UsageUsage

s High-tech companiesHigh-tech companies

Texas Instruments, Intel use VHDL

most European companies use VHDL

s UniversitiesUniversitiess VHDL groups to support new usersVHDL groups to support new users

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Technology independenceTechnology independence

s The design of VHDL components can be technology-independentThe design of VHDL components can be technology-independentor more-or-less technology independent for a technical familyor more-or-less technology independent for a technical family

s The components can be stored in a library for reuse in severalThe components can be stored in a library for reuse in several

different designsdifferent designs

s VHDL models of commercial IC standard components can nowVHDL models of commercial IC standard components can nowbe bought, which is a great advantage when it comes to verifyingbe bought, which is a great advantage when it comes to verifying

entire circuit boardsentire circuit boards

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Analog worldAnalog world

s VHDL has not yet been standardized for analog electronicsVHDL has not yet been standardized for analog electronics

s Standardization is in progress on VHDL with an analogStandardization is in progress on VHDL with an analog

extension (AHDL) to allow analog systems to be describedextension (AHDL) to allow analog systems to be described

as wellas well

s This new standard will be based wholly on the VHDLThis new standard will be based wholly on the VHDL

standard and will have a number of additions for describingstandard and will have a number of additions for describing

analog functionsanalog functions

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CAPABILITIES OF VHDLCAPABILITIES OF VHDL

s Used as exchange medium b/w chip vendors & cad tool usersUsed as exchange medium b/w chip vendors & cad tool users

* different chip vendors can provide vhdl descriptions of their components to* different chip vendors can provide vhdl descriptions of their components tosystem designerssystem designers

* CAD Tool users can use it to capture the behavior of the design at high level* CAD Tool users can use it to capture the behavior of the design at high levelof abstraction for functional simulation.of abstraction for functional simulation.

s Used as communication medium b/w different CAD & CAE ToolsUsed as communication medium b/w different CAD & CAE Tools

schematic capture may be used to generate a VHDL description for theschematic capture may be used to generate a VHDL description for thedesign which can be used as i/p to simulation programdesign which can be used as i/p to simulation program

s Supports hierarchy-digital system can be modeled as set of interconnectedSupports hierarchy-digital system can be modeled as set of interconnected

components.components.

s Supports flexible design methodologies, top down ,bottom up or mixedSupports flexible design methodologies, top down ,bottom up or mixed

s Not technology specific but is capable of supporting techonology specificNot technology specific but is capable of supporting techonology specificfeaturesfeatures

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s

Supports both synchronous & asynchronous timing models.Supports both synchronous & asynchronous timing models.s Modeling techniques such as FSM Descriptions,algorithmicModeling techniques such as FSM Descriptions,algorithmic

Descriptions,boolean equations possibleDescriptions,boolean equations possible

s Publicly available,human readable ,machine readable not proprietary\Publicly available,human readable ,machine readable not proprietary\s IEEE & ANSI standardIEEE & ANSI standard

s Supports three basic descriptions styles ie structural,behavioral,dataflow orSupports three basic descriptions styles ie structural,behavioral,dataflow orcombination of thesecombination of these

s Supports wide range of abstraction levels ranging from abstract behavioralSupports wide range of abstraction levels ranging from abstract behavioraldescriptions to very precise gate level descriptionsdescriptions to very precise gate level descriptions

s Design can be captured @ mixed level using single coherent languageDesign can be captured @ mixed level using single coherent languages Arbitrarily large designs can be modeled -- no limitations on the size of theArbitrarily large designs can be modeled -- no limitations on the size of the

designdesign

s Language elements make large scale design modeling easier eg componentsLanguage elements make large scale design modeling easier eg components,functions ,procedures and packages,functions ,procedures and packages

s Test bench can be written using the same language to test vhdl modelsTest bench can be written using the same language to test vhdl models

s

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VHDL-Related NewsgroupsVHDL-Related Newsgroups

s comp.arch.fpgacomp.arch.fpga

s comp.lang.vhdlcomp.lang.vhdl

s comp.cad.synthesiscomp.cad.synthesis

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Other HDL languagesOther HDL languagess

There are several other language extensions built to either aid in RTL constructionThere are several other language extensions built to either aid in RTL constructionor assist in modeling:or assist in modeling:

ParaCore -ParaCore - http://www.dilloneng.com/paracore.shtmlhttp://www.dilloneng.com/paracore.shtml

RubyHDL -RubyHDL - http://www.aracnet.com/~ptkwt/ruby_stuff/RHDL/index.shtmlhttp://www.aracnet.com/~ptkwt/ruby_stuff/RHDL/index.shtml

MyHDL -MyHDL - http://jandecaluwe.com/Tools/MyHDL/Overview.shtmlhttp://jandecaluwe.com/Tools/MyHDL/Overview.shtml

JHDL -JHDL - http://www.jhdl.org/http://www.jhdl.org/ Lava -Lava - http://www.xilinx.com/labs/lava/http://www.xilinx.com/labs/lava/

HDLmaker -HDLmaker - http://www.polybus.com/hdlmaker/users_guide/http://www.polybus.com/hdlmaker/users_guide/

SystemCSystemC

AHDLAHDL http://www.altera.comhttp://www.altera.com

ItIt is goodis good for Altera-made chips only, which limits its usefulnessfor Altera-made chips only, which limits its usefulness But iBut it is easy to pick up andt is easy to pick up and use successfullyuse successfully

s The main purpose of a language -- programming, hdl, or otherwise -- is to ease theThe main purpose of a language -- programming, hdl, or otherwise -- is to ease the

expression of designexpression of design
http://www.dilloneng.com/paracore.shtmlhttp://www.dilloneng.com/paracore.shtmlhttp://www.aracnet.com/~ptkwt/ruby_stuff/RHDL/index.shtmlhttp://www.aracnet.com/~ptkwt/ruby_stuff/RHDL/index.shtmlhttp://jandecaluwe.com/Tools/MyHDL/Overview.shtmlhttp://jandecaluwe.com/Tools/MyHDL/Overview.shtmlhttp://www.jhdl.org/http://www.jhdl.org/http://www.xilinx.com/labs/lava/http://www.xilinx.com/labs/lava/http://www.polybus.com/hdlmaker/users_guide/http://www.polybus.com/hdlmaker/users_guide/http://www.altera.com/http://www.altera.com/http://www.altera.com/http://www.polybus.com/hdlmaker/users_guide/http://www.xilinx.com/labs/lava/http://www.jhdl.org/http://jandecaluwe.com/Tools/MyHDL/Overview.shtmlhttp://www.aracnet.com/~ptkwt/ruby_stuff/RHDL/index.shtmlhttp://www.dilloneng.com/paracore.shtml

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VHDL vs. VerilogVHDL vs. VerilogVHDL Verilog

All abstraction levels All abstraction levelsComplex grammar Easy language

Describe a system (everything) Describe a digital system

Lots of data types Few data types

User-defined package & library No user-defined packages

Full design parameterization Simple parameterization

Easier to handle large designs

Very consistent language. Code written andsimulated in one simulator will behave exactlythe same in another simulator. E.g. strong

typing rules.

Less consistent language. If you don't followsome adhoc methodology for coding styles,you will not get it right.

It executes differently on different platformsunless you follow some adhoc coding rules.

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VHDL vs. Verilog: Process blockVHDL vs. Verilog: Process block

s

VHDL:process (siga, sigb)

begin

...

end;

s Verilog:

always @ (siga or sigb)

begin

.

end

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VHDL vs. Verilog:VHDL vs. Verilog:

Concurrent Signal AssignmentConcurrent Signal Assignment

s VHDL:

c

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VHDL vs. Verilog: Signal DelaysVHDL vs. Verilog: Signal Delays

s VHDL:

a

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Verilog WeaknessVerilog Weakness

s Not well suited for complex, high level modeling

No user defined type definition

No concept of libraries, packages, configurations

No generate statement - cant build parameterized structural models

No complex types above a two-dimensional array

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Managing Large designsManaging Large designs

s VHDLVHDL::

Configuration, generate, generic and package statements all help manageConfiguration, generate, generic and package statements all help managelarge design structureslarge design structures

s VerilogVerilog::

There are no statements in Verilog that help manage large designsThere are no statements in Verilog that help manage large designs

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Procedures and TasksProcedures and Tasks

s VHDLVHDL::

allows concurrent procedure callsallows concurrent procedure calls

s VerilogVerilog::

does not allow concurrent task callsdoes not allow concurrent task calls

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Structural ReplicationStructural Replication

s VHDLVHDL::

TheThegenerategenerate statement replicates a number of instancesstatement replicates a number of instances

of the same design-unit or some sub part of a design, andof the same design-unit or some sub part of a design, andconnects it appropriatelyconnects it appropriately

s VerilogVerilog::

There is no equivalent to theThere is no equivalent to the generategenerate statement instatement in

Verilog.Verilog.

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Languages under developmentLanguages under development

s SystemVerilogSystemVerilog

Extending Verilog to higher levels of abstraction for architectural andExtending Verilog to higher levels of abstraction for architectural and

algorithm design and advanced verificationalgorithm design and advanced verification

s VHDL 200xVHDL 200x

Goal of VHDL Analysis and Standards Group (VASG):Goal of VHDL Analysis and Standards Group (VASG):

Enhance/update VHDL for to improve performance, modeling capability,Enhance/update VHDL for to improve performance, modeling capability,

ease of use, simulation control, and the type systemease of use, simulation control, and the type system

s e.g.:e.g.: Data types and abstractions:Data types and abstractions:

variant recordsvariant records

interfacesinterfaces

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VHDL ExampleVHDL Example

s And gateAnd gate

a

b

cAND

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VHDL Description: AND gateVHDL Description: AND gate

entityentity AND2AND2 isis

portport (a, b:(a, b: inin bit ;bit ;

c :c : outout bit);bit);

endend AND2;AND2;

architecturearchitecture behbeh ofofAND2AND2 isisbeginbegin

c

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Concurrency in VHDL DescriptionsConcurrency in VHDL Descriptions

signals

process 1 process 2 process n

signals

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Concurrent and Sequential ComputationsConcurrent and Sequential Computations

s Processes are concurrentProcesses are concurrent

s Sequential activity within each processSequential activity within each process

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Hierarchy in VHDLHierarchy in VHDL

S 1

S 2

C 4

S 3

S 1

S 1

S 4

S 5

C 5

C 1

S 6

C 6

S 7

S 8

S 9

S 1

C 7

C 2

S 1 1

S 1

C 3

C 0

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Modeling Styles in VHDL

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Modeling StylesModeling Styles

s Semantic model of VHDLSemantic model of VHDL

s Structural descriptionStructural description

s Data Flow descriptionData Flow description

s Algorithmic descriptionAlgorithmic description

s RTL descriptionRTL description

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Modeling Choices in VHDLModeling Choices in VHDL

s Behavioral and Structural DomainsBehavioral and Structural Domains

Several Levels of AbstractionSeveral Levels of Abstraction

s Multiple Styles of Behavioral Description:Multiple Styles of Behavioral Description:

Data Flow Style (concurrent)Data Flow Style (concurrent)

Procedural Style (sequential)Procedural Style (sequential)

s Combinations, variations and special cases of these, e.g.,Combinations, variations and special cases of these, e.g.,

special case of data flow style - FSM described using guarded blocksspecial case of data flow style - FSM described using guarded blocks

special case of procedural style - FSM described using case statement in aspecial case of procedural style - FSM described using case statement in aprocessprocess

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Structural DescriptionStructural Description

s Carries same information as a NET LISTCarries same information as a NET LIST

s Net List =Net List = (Component instances) + (Nets)(Component instances) + (Nets)

s Structural Description in VHDL =Structural Description in VHDL =

(Signals) + (Component instances + Port maps)(Signals) + (Component instances + Port maps)

s Many sophisticated features in VHDL to make it more versatile:Many sophisticated features in VHDL to make it more versatile:

* Variety of signal types* Variety of signal types

* Generic components* Generic components

* Generate statements for creating arrays of component instances* Generate statements for creating arrays of component instances

* Flexibility in binding components to design entities and architectures* Flexibility in binding components to design entities and architectures

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Behavioral DescriptionBehavioral Description

s ProceduralProcedural

(textual order => execution order)(textual order => execution order)

s Sequential statementsSequential statements

s Control constructs alter normal sequentialControl constructs alter normal sequentialflowflow

Called Behavioral description in VHDLCalled Behavioral description in VHDL

s Non-proceduralNon-procedural

(textual order NOT => execution order)(textual order NOT => execution order)

s Concurrent statementsConcurrent statements

s Data flow (or rather data dependencyData flow (or rather data dependencyrestricts concurrency)restricts concurrency)

Called Data flow description in VHDLCalled Data flow description in VHDL

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Example: 1-bit Full AdderExample: 1-bit Full Adder

entityentity FullAdderFullAdderisis

portport (X, Y, Cin:(X, Y, Cin: inin bit;bit; -- Inputs-- Inputs

Cout, Sum:Cout, Sum: outout bit);bit); -- Outputs-- Outputs

endend FullAdder;FullAdder;

XY

Cin

Sum

CoutFullAdder

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Example: 1-bit Full Adder (contd.)Example: 1-bit Full Adder (contd.)

ArchitectureArchitecture EquationsEquations ofofFullAdderFullAdderisis

beginbegin -- Concurrent Assignment-- Concurrent Assignment

Sum

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Example: 4-bit AdderExample: 4-bit Adder

entityentity Adder4Adder4 isis

portport (A, B:(A, B: inin bit_vector(3bit_vector(3 downtodownto 0);0);

Ci:Ci: inin bit;bit; -- Inputs-- Inputs

S:S: outoutbit_vector(3bit_vector(3 downtodownto 0);0);

Co:Co: outout bit);bit); -- Outputs-- Outputs

endend Adder4;Adder4;

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Example: 4-bit Adder (contd.)Example: 4-bit Adder (contd.)

ArchitectureArchitecture StructureStructure ofof Adder4Adder4 isis

ComponentComponent FullAdderFullAdder

port (X, Y, Cin:port (X, Y, Cin: inin bit; Cout, Sum:bit; Cout, Sum: outout bit);bit);

signalsignal C:C:bit_vectorbit_vector(3(3 downtodownto 1);1);

beginbegin -- Instantiations-- Instantiations

FA0: FullAdder port map (A(0), B(0), Ci, C(1), S(0));FA0: FullAdder port map (A(0), B(0), Ci, C(1), S(0));

FA1: FullAdder port map (A(1), B(1), C(1), C(2), S(1));FA1: FullAdder port map (A(1), B(1), C(1), C(2), S(1));

FA2: FullAdder port map (A(2), B(2), C(2), C(3), S(2));FA2: FullAdder port map (A(2), B(2), C(2), C(3), S(2));

FA3: FullAdder port map (A(3), B(3), C(3), Co, S(3));FA3: FullAdder port map (A(3), B(3), C(3), Co, S(3));

endend Structure;Structure;

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Example: 4-bit ComparatorExample: 4-bit Comparator

entityentity nibble_comparatornibble_comparatorisis

portport (a, b:(a, b: inin bit_vector (3bit_vector (3 downtodownto 0);0);

gt,eq,lt :gt,eq,lt : inin bit;bit;

a_gt_b, a_eq_b, a_lt_b :a_gt_b, a_eq_b, a_lt_b : outout bit);bit);

endend nibble_comparator;nibble_comparator;

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Structural Description (contd.)Structural Description (contd.)

architecturearchitecture iterativeiterative ofofnibble_comparatornibble_comparatorisiscomponentcomponent comp1comp1

portport (a, b, gt,eq,lt :(a, b, gt,eq,lt : inin bit; a_gt_b, a_eq_b, a_lt_b :bit; a_gt_b, a_eq_b, a_lt_b : outout bit);bit);end componentend component;;for allfor all : comp1: comp1 use entityuse entity work.bit_comparator(gate_level);work.bit_comparator(gate_level);signalsignal im: bit_vector (0 to 8);im: bit_vector (0 to 8);

beginbegin

c0:comp1c0:comp1port mapport map(a(0),b(0), gt, eq, lt, im(0), im(1), im(2));(a(0),b(0), gt, eq, lt, im(0), im(1), im(2));c1toc2:c1toc2: forforii inin 11 toto 22 generategeneratec:comp1c:comp1port mapport map(a(i),b(i),im(i*3-3),im(i*3-2),im(i*3-1),(a(i),b(i),im(i*3-3),im(i*3-2),im(i*3-1),

im(i*3+0),im(i*3+1),im(i*3+2));im(i*3+0),im(i*3+1),im(i*3+2));end generateend generate;;

c3: comp1c3: comp1port mapport map(a(3),b(3),im(6),im(7),im(8),(a(3),b(3),im(6),im(7),im(8),

a_gt_b, a_eq_b, a_lt_b);a_gt_b, a_eq_b, a_lt_b);

endend nibble_comparator;nibble_comparator;

E l 1 bit C tE l 1 bit C t

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Example: 1-bit ComparatorExample: 1-bit Comparator

(data flow)(data flow)

entityentity comp1comp1 isis

portport (a, b, gt,eq,lt :(a, b, gt,eq,lt : inin bit; a_gt_b, a_eq_b, a_lt_b :bit; a_gt_b, a_eq_b, a_lt_b : outout bit);bit);endend comp1;comp1;

architecturearchitecture dataflowdataflow ofofcomp1comp1 isissignalsignal s : bit;s : bit;

beginbegins

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s Behavioral Description in VHDLBehavioral Description in VHDL

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Modeling StylesModeling Styles

s Semantic model of VHDLSemantic model of VHDL

s Structural descriptionStructural description

s Data Flow descriptionData Flow description

s Algorithmic descriptionAlgorithmic description

s RTL descriptionRTL description

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Concurrent Statements in VHDLConcurrent Statements in VHDL

s process statementprocess statement -- behavior-- behavior

s concurrent procedure callconcurrent procedure call -- behavior-- behavior

s concurrent signal assign.concurrent signal assign. -- data flow-- data flow

s component instantiationcomponent instantiation -- structure-- structure

s generate statementgenerate statement -- structure-- structure

s block statementblock statement -- nesting-- nesting

s

concurrent assertion stmtconcurrent assertion stmt -- error check-- error check

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Example: D Flip-FlopExample: D Flip-Flop

entityentity DFFDFF isis

portport (D, CLK:(D, CLK: inin bit;bit;

Q:Q: outout bit; QN:bit; QN: outout bit := 1) ;bit := 1) ;

endend DFF;DFF;

D

CLK

Q

QNDFF

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Example: DFF (contd.)Example: DFF (contd.)

ArchitectureArchitecture BehBeh ofofDFFDFF isis

beginbegin processprocess (CLK)(CLK)

beginbegin ifif(CLK = 1(CLK = 1 thenthen

Q

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CASE Statement:CASE Statement:

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CASE Statement:CASE Statement:

4 to 1 Multiplexer4 to 1 Multiplexer

Case sel is

when 0 => y y y y

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VHDL Processes

General form of Processprocess(sensitivity-list)

begin

sequential-statements

end process;Process example

process (B, C, D)

begin

A

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Date post:	30-May-2018
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VHDL 160909

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