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VHDL ASSIGNMENT 1

Experiment 1

Write a vhdl code to describe behaviourally the operation of an AND gate

Block Diagram:

Port Map:

a,b: input

y: output

Functional Description:

library ieee;use ieee.std_logic_1164.all;

entity and1 is

port (a,b: in std_logic;

y: out std_logic);

end and1;

architecture and1 of and1 is

begin

process(a,b)

begin

y

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use ieee.std_logic_1164.all;

entity tand is

end tand;

architecture tand of tand is

signal a: std_logic;

signal b: std_logic;

signal y: std_logic;

component and1 is

port (a,b: in std_logic;

y: out std_logic);

end component;

begina1: and1 port map (a,b,y);

process

begin

a

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Experiment 2

Write a vhdl code to describe behaviourally the operation of an OR gate

Block Diagram:

Port Map:

a,b: input

y: output

Functional Description:

library ieee;

use ieee.std_logic_1164.all;

entity or1 is

port (a,b: in std_logic;

y: out std_logic);

end or1;

architecture or1 of or1 is

begin

process(a,b)

begin

y

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library ieee;

use ieee.std_logic_1164.all;

entity tor is

end tor;

architecture tor of tor is

signal a: std_logic;

signal b: std_logic;

signal y: std_logic;

component or1 is

port (a,b: in std_logic;

y: out std_logic);end component;

begin

a1: or1 port map (a,b,y);

process

begin

a

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Experiment 3

Write a vhdl code to describe behaviourally the operation of an NOT gate

Block Diagram:

Port Map:

a,: input

y: output

Functional Description:

library ieee;

use ieee.std_logic_1164.all;

entity not1 is

port(a: in std_logic;

y: out std_logic);

end not1;

architecture not1 of not1 is

begin

process(a)

begin

y

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Testing Strategy

library ieee;

use ieee.std_logic_1164.all;

entity tnot is

end tnot;

architecture tnot of tnot is

signal a: std_logic;

signal y: std_logic;

component not1

port(a: in std_logic;

y: out std_logic);

end component;

begin

n1: not1 port map(a,y);

process

begin

a

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Experiment 4

Write a vhdl code to describe behaviourally the operation of an XOR gate

Block Diagram:

Port Map:

a,b: input

y: output

Functional Description:

library ieee;

use ieee.std_logic_1164.all;

entity xor1 is

port(a,b: in std_logic;

y: out std_logic);

end xor1;

architecture xor1 of xor1 is

begin

process(a,b)

begin

y

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end txor;

architecture txor of txor is

signal a,b: std_logic;

signal s: std_logic;

signal e,f,g,h: std_logic;

component xor1 is

port(a: in std_logic;

b: in std_logic;

s: out std_logic);

end component;

begin

x1: xor1 port map (a,b,s);process

begin

a

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Experiment 5

Write a vhdl code to describe structurally the operation of an XOR gate

Block Diagram:

Port Map:

a,b: input

y: output

Functional Description:

library ieee;

use ieee.std_logic_1164.all;

entity xor1 is

port (a,b: in std_logic;

s: out std_logic);

end xor1;

architecture xor1 of xor1 is

component and1

port (a,b: in std_logic;

y: out std_logic);

end component and1;

component or1

port(a,b: in std_logic;

y: out std_logic);

end component or1;

component not1

port (a: in std_logic;

a b y

0

0

1

1

0

1

0

1

0

1

1

0

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y: out std_logic);

end component not1;

signal e,f,g,h: std_logic;

begin

m1: not1 port map(a,e);

a2: not1 port map(b,f);

a3: and1 port map (a,f,g);

a4: and1 port map(b,e,h);

a5: or1 port map (e,f,s);

end xor1;

Testing Strategy

library ieee;

use ieee.std_logic_1164.all;

entity txor is

end txor;

architecture txor of txor is

signal a,b: std_logic;

signal s: std_logic;

signal e,f,g,h: std_logic;

component xor1 is

port(a: in std_logic;

b: in std_logic;

s: out std_logic);

end component;

begin

x1: xor1 port map (a,b,s);

process

begin

a

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a

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Experiment 6

Write a vhdl code to describe structurally the operation of an NAND gate

Block Diagram:

Port Map:

a,b: input

y: output

Functional Description:

library ieee;

use ieee.std_logic_1164.all;

entity nands is

port (a,b: in std_logic;

y: out std_logic);

end nands;

architecture nands of nands is

component and1 is

port (a,b: in std_logic;

y: out std_logic);

end component;

component not1 is

port (a: in std_logic;

y: out std_logic);

end component;

signal s: std_logic;

begin

a1: and1 port map (a,b,s);

a2: not1 port map (s,y);

end nands;

a b y

0

0

1

1

0

1

0

1

1

1

1

0

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Testing Strategy

library ieee;

use ieee.std_logic_1164.all;

entity txor is

end txor;

architecture txor of txor is

signal a,b: std_logic;

signal s: std_logic;

signal e,f,g,h: std_logic;

component xor1 is

port(a: in std_logic;

b: in std_logic;

s: out std_logic);

end component;

begin

x1: xor1 port map (a,b,s);

process

begin

a

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Experiment 7

Write a vhdl code to describe structurally the operation of an NOR gate

Block Diagram:

Port Map:

a,b: input

y: output

Functional Description:

library ieee;

use ieee.std_logic_1164.all;

entity nors1 is

port (a,b: in std_logic;

y: out std_logic);

end nors1;

architecture nors1 of nors1 is

component or1 is

port (a,b: in std_logic;

y: out std_logic);

end component;

component not1 is

port (a: in std_logic;

y: out std_logic);

end component;

signal s: std_logic;

begin

a1: or1 port map (a,b,s);

a2: not1 port map (s,y);

end nors1;

a b y

0

0

1

1

0

1

0

1

1

0

0

1

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Testing Strategy

library ieee;

use ieee.std_logic_1164.all;

entity tnors is

end tnors;

architecture tnors of tnors is

signal a: std_logic;

signal b: std_logic;

signal y: std_logic;

component nors1 is

port (a,b: in std_logic;

y: out std_logic);

end component;

begin

a1: nors1 port map (a,b,y);

process

begin

a

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Result:

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Assignment no 2

Experiment 1

Write a vhdl code to describe behaviourally of the two input mux

Block Diagram:

Port Map:

a,b,s: input

y: output

Functional Description:

library ieee;

use ieee.std_logic_1164.all;

entity mux2 is

port (a: in std_logic;

b: in std_logic;

s: in std_logic;

y: out std_logic);

end mux2;

architecture mux2 of mux2 is

begin

process(s)

begin

if (s='0') then

y

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end process;

end mux2;

Testing Strategy

library ieee;

use ieee.std_logic_1164.all;

entity tmux2 is

end tmux2;

architecture tmux2 of tmux2 is

signal a: std_logic:='1';

signal b: std_logic:='0';

signal s: std_logic;

signal y: std_logic;

component mux2 is

port(a: in std_logic;

b: in std_logic;

s: in std_logic;

y: out std_logic);

end component;

begin

m1: mux2 port map(a,b,s,y);

process

begin

s

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Experiment 2

Write a vhdl code to describe behaviourally of the four input mux

Block Diagram:

Port Map:

a,b,c,d,s0,s1: input

y: output

Functional Description:

library ieee;

use ieee.std_logic_1164.all;

entity mux4s is

port (a,b,c,d: in std_logic;

s0: in std_logic;

s1: in std_logic;

y: out std_logic);

end mux4s;

architecture mux4s of mux4s is

component mux2 is

port (a,b: in std_logic;s: in std_logic;

y: out std_logic);

end component ;

signal t1,t2: std_logic;

begin

m1: mux2 port map (a,b,s0,t1);

m2: mux2 port map (c,d,s0,t2);

m3: mux2 port map (t1,t2,s1,y);

S0 S1 Y

0

0

1

1

0

1

0

1

a

b

c

d

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end mux4s;

Testing Strategy

library ieee;

use ieee.std_logic_1164.all;

entity tmux2 is

end tmux2;

architecture tmux2 of tmux2 is

signal a: std_logic:='1';

signal b: std_logic:='0';

signal s: std_logic;

signal y: std_logic;

component mux2 is

port(a: in std_logic;

b: in std_logic;

s: in std_logic;

y: out std_logic);

end component;

begin

m1: mux2 port map(a,b,s,y);

process

begin

s

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Experiment 3

Write a vhdl code to describe behaviourally the operation of the two input demux.

Block Diagram:

Port Map:

i,s: input

y: output

Functional Description:

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity demux2 is

port (i: in std_logic;

s : in std_logic;

y: out std_logic_vector(1 downto 0));

end demux2;

architecture demux2 of demux2 is

begin

process(s)

begin

if (s='0') then

y

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Testing Strategy

library ieee;

use ieee.std_logic_1164.all;

entity tdemux2 is

end tdemux2;

architecture tdemux2 of tdemux2 is

signal i,s:std_logic:='1';

signal y: std_logic_vector(1 downto 0);

component demux2 is

port(i,s: in std_logic;

y: out std_logic_vector(1 downto 0));

end component;

begin

d1: demux2 port map (i,s,y);

process

begin

s

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Experiment 4

Write a vhdl code to describe behaviourally the operation of an eight input priority encoder

Block Diagram:

Port Map:

i,s: input

y: output

Functional Description:

library ieee;

use ieee.std_logic_1164.all;

entity pe is

port(i: in std_logic_vector(7 downto 0);

y: out std_logic_vector(2 downto 0));

end pe;

architecture pe of pe is

begin

process (i)

begin

if(i(7)='1') then

y

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y

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i

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Experiment 5

Write a vhdl code to describe behaviourally the operation of the three input decoder.

Block Diagram:

Port Map:

i: input

y: output

Functional Description:

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity decod3 is

port (i: in std_logic_vector(2 downto 0);

y: out std_logic_vector(7 downto 0));

end decod3;

architecture decod3 of decod3 is

begin

process(i)

begin

case i is

when "000"=>yyyyyyyy

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end process;

end decod3;

Testing Strategy

library ieee;

use ieee.std_logic_1164.all;

entity tdecod3 is

end tdecod3;

architecture tdecod3 of tdecod3 is

signal i: std_logic_vector(2 downto 0);

signal y: std_logic_vector(7 downto 0);

component decod3 is

port(i: in std_logic_vector(2 downto 0);

y: out std_logic_vector(7 downto 0));

end component;

begin

d1:decod3 port map (i,y);

process

begin

i

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wait for 5 ns;

end process;

end tdecod3;

Result

Experiment 6

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Write a vhdl code to describe behaviourally the operation of a full adder.

Block Diagram:

Port Map:

A,b,c: input

S,ca: output

Functional Description:

library ieee;use ieee.std_logic_1164.all;

entity fa isport (a,b,c: in std_logic;

s,ca: out std_logic);end fa ;architecture fa of fa is

signal s1: std_logic;signal s2: std_logic;signal s3: std_logic;beginprocess(a,b,c)begins1

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entity fat is

end fat;

architecture fata of fat is

signal a,b,c: std_logic;

signal s,ca: std_logic;

component fa

port (a,b,c: in std_logic;s,ca: out std_logic);

end component;

beginf1: fa port map (a,b,c,s,ca);

process

begin

a

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Experiment 7

Write a vhdl code to describe structurally the operation of a full adder.

Block Diagram:

Port Map:

A,b,c: input

S,ca

: output

Functional Description:

library ieee;use ieee.std_logic_1164.all;

entity fas is

port(a,b,c: in std_logic;

s,ca: out std_logic);

end fas;

architecture fas of fas is

component ha is

port (a,b: in std_logic;

s,ca: out std_logic);

end component;

component or1 is

port (a,b: in std_logic;

y: out std_logic);

end component;

signal s1,s2,s3: std_logic;

begin

a b c s Ca

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

1

0

1

0

0

1

0

0

0

1

0

1

1

1

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a1: ha port map(a,b,s1,s2);

a2: ha port map(s1,c,s,s3);

a3: or1 port map (s2,s3,ca);

end fas;

Testing Strategy

library ieee;

use ieee.std_logic_1164.all;

entity tfas is

end tfas ;

architecture tfas of tfas is

signal a,b,c: std_logic;

signal s,ca: std_logic;

--signal s1,s2,s3: std_logic;

component fas is

port (a,b,c: in std_logic;

s,ca: out std_logic);

end component;

begin

process

begin

a

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a

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