VHDL by Pacific

8/8/2019 VHDL by Pacific

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VHDL PROGRAMMING

By Prashant PacificModule I

Fundamental VHDL Units , LIBRARY Declarations, ENTITY, ARCHITECTURE,

Introductory Examples, Specification of combinational systems using VHDL,

Introduction to VHDL, Basic language element of VHDL, Behavioral Modeling, Data

flow modeling, Structural modeling, Subprograms and overloading, VHDL description

of gates.

What the F*** is VHDL?VHDL is an acronym for VHSlC Hardware Description Language (VHSIC is an acronym for

Very High Speed Integrated Circuits). It is a hardware description language that can be usedto model a digital system at many levels of abstraction ranging from the algorithmic level to

the gate level.The VHDL language can be regarded as an integrated amalgamation of the following

languages:sequential language + concurrent language + net-list language +

timing specifications +waveform generation language => VHDL

Fundamental VHDL UnitsA standalone piece of VHDL code is composed of at least

three fundamental sections:

LIBRARY declarations: Contains a list of all libraries to be used in the design. Forexample: ieee, std, work, etc.

ENTITY: Specifies the I/O pins of the circuit.

ARCHITECTURE: Contains the VHDL code proper, which describes how the


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LIBRARY DeclarationsTo declare a LIBRARY (that is, to make it visible to the design) two lines of code

are needed, one containing the name of the library, and the other a use clause, as

shown in the syntax below.

LIBRARY library_name;

USE library_name.package_name.package_parts;

At least three packages, from three dierent libraries, are usually needed in adesign:

ieee.std_logic_1164 (from the ieee library), standard (from the std library), and work (work library).

Their declarations are as follows:

LIBRARY ieee; -- A semi-colon (;) indicatesUSE ieee.std_logic_1164.all; -- the end of a statement or

LIBRARY std; -- declaration, while a doubleUSE std.standard.all; -- dash (--) indicates a comment.

LIBRARY work;

USE work.all;

The libraries std and work shown above are made visible by default, so there is no

need to declare them; only the ieee library must be explicitly written. However, the

latter is only necessary when the STD_LOGIC (or STD_ULOGIC) data type is

employed in the design (data types will be studied in detail in the next chapter).

The purpose of the three packages/libraries mentioned above is the following: thestd_logic_1164 package of the ieee library specifies a multi-level logic system; std is a

resource library (data types, text i/o, etc.) for the VHDL design environment; and the

work library is where we save our design (the .vhd file, plus all files created by the

compiler, simulator, etc.).

ENTITYAn ENTITY is a list with specifications of all input and output pins (PORTS) of the

circuit. Its syntax is shown below.

ENTITY entity_name IS

PORT (

port_name : signal_mode signal_type;port_name : signal_mode signal_type;...);

END entity_name;

Example: Let us consider the NAND gate of figure 2.4. Its ENTITY can be specified

as:


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The meaning ofthe ENTITY above i the following:the ci cuithas three I/ pins,

being two inputs (a and b, mode IN) and one output (x, mode OUT). Allthree signals

are oft pe BIT. The name chosen forthe entit was nand gate.

The mode ofthe signal can be IN, OUT,

INOUT, orBUFFER. As illustrated in

figure 2.3, IN and OUT are trul

unidirectional pins, while INOUTis

bidirectional.

BUFFER, on the otherhand, is employed

when the output signal must be used

(read) internally.

The type ofthe signal can be BIT,STD_LOGIC, INTEGER, etc. Data types

willbe discussed LATER.

Fi ll the name of the entity can be

basically any name, except VHDL

reservedwords (VHDL reserved words are listedin appendix E)


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HALF ADDER

entity HALF_ADDER is

port (A, B: in BIT; SUM, CARRY: out BIT);

end HALF_ADDER;

FULL ADDER

entity FULL_ADDERis

port (A, B, CIN: in BIT; SUM, COUT: out BIT);

end FULL_ADDER;

2x4 DECODER

entity DECODER2x4 is

port (A, B, ENABLE: in BIT;Z: outBIT_VECTOR(0 to 3));end DECODER2x4;

MUX 2x1

entity MUX2x1 isPort ( A : in std_logic;

B : in std_logic;

S : in std_logic;Y : out std_logic);end MUX2x1;

DFF

entity DFF is

port ( D, CLK, RST: in STD_LOGIC;Q: out STD_LOGIC);

end DFF;


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ARCHITECTUREThe ARCHITECTURE is a description of how the circuit should behave (function).

Its syntax is the following:

ARCHITECTURE architecture_name OF entity_name IS

[declarations]

BEGIN(code)

END architecture_name;

As shown above, an architecture has two parts: a declarative part (optional), wheresignals and constants (among others) are declared, and the code part (from BEGIN

down). Like in the case of an entity, the name of an architecture can be basically anyname (except VHDL reserved words), including the same name as the entitys.

The internal details of an entity are specified by an architecture body using any of the

following modeling styles:

1. As a set of interconnected components (to represent structure),2. As a set of concurrent assignment statements (to represent dataflow),

3. As a set of sequential assignment statements (to represent be-hav.ior),4. Any combination of the above three.

Structural modelingIn the structural style of modeling, an entity is described as a set of interconnected

components.

architectureidentifierofentity_name is

architecture_declarative_partbegin

architecture_statement_part

end [ architecture_simple_name ] ;

architecture_declarative_part ::= { block_declarative_item }

architecture_statement_part ::= { concurrent_statement }

block_declarative_item ::=

subprogram_declaration

subprogram_body

type_declaration

subtype_declarationconstant_declaration

signal_declaration

alias_declaration

component_declaration


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6 | P a g e HALF ADDER architecture HA_STRUCTURE of HALF_ADDERis

component XOR2

port (X, Y:in BIT; Z:out BIT);

end component;

component AND

port (L, M:in BIT; N:out BIT);

end component;

begin

X1: XOR2 port map (A, B, SUM);A1: AND2 port map (A, B, CARRY);

end HA_STRUCTURE;

FULL ADDER

architecture FA_STRUCT of FULL_ADDERis

component XOR1

port (A,B:in BIT; S1:out BIT);

end component;

component XOR2

port (S1,CIN:in BIT; SUM:out BIT);

end component;

component AND1

port (CIN,S1:in BIT; N1:out BIT);end component;

component AND

port (A,B:in BIT; N2:out BIT);

end component;

component OR

port (N1,N2:in BIT;COUT:out BIT);

end component;

begin

X1: XOR1port map (A, B, S1);

A1: XOR2 port map (S1,CIN,SUM);

A1: AND1 port map (CIN,S1,N1);

A2: AND2 port map (A,B,N2);01: OR1 port map (N1,N2,COUT)

end FA_STRUCT;

2x4 DECODER

architecture DEC_STRofDECODER2x4 is

component INV

port (A:in BIT; Z:out BIT);

end component;

componentNAND3

port (A, B, C:in BIT; Z:out BIT);

end component;signalABAR, BBAR:BIT;

beginI0:INV port map (A, ABAR);

I1:INV port map (B, BBAR);

N0: NAND3 port map (ABAR, BBAR,ENABLE, Z(0));

N1: NAND3 port map (ABAR, B, ENABLE,Z(1));


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N2: NAND3 port map (A, BBAR, ENABLE,

Z(2));

N3: NAND3 port map (A, B, ENABLE, Z(3));

end DEC_STR;

MUX 2x1 architecture MUX_STRUCT of mux2to1is

component AND1

port (A,SEL: in BIT; S1: out BIT);

end component;

component INV

port (SEL: in BIT; K: out BIT);end component;

signal SELBAR: BIT;component AND2port (B,SELBAR: in BIT; S2: out BIT);

end component;

component 0Rport (S1,S2: in BIT; Z: out BIT);

end component;

begin

I0: INV port map (SEL, SELBAR);A1: AND1 port map (A,SEL);

A2: AND2 port map (SELBAR,B);

OR: ORport map (S1,S2);endMUX_STRUCT

DFF


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Data Flow ModelingIn this modeling style, the flow of data through the entity is expressed primarily using

concurrent signal assignment statements.The structure ofthe entity is not explicitly specifiedin this modeling style, butit can be implicitly deduced.

HALF ADDER

architecture HA_dataflow of HA

beginSUM


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Behavioral Style of ModelingIn contrast to the styles of modeling described earlier, the behavioral style of modelingspecifies the behavior of an entity as a set of statements that are executed sequentially in the

specified order. This set of sequential statements, that are specified inside a process

statement, do not explicitly specify the structure of the entity but merely specifies itsfunctionality. A process statement is a concurrent statement that can appear within an

architecture body.

MUX 2x1

architectureMUX_dataflow OF MUX_2to1 IS

signalx1, x2,SELBAR : BIT;

beginx1


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FULL ADDER

2x4 DECODER

Architecture dec_seq ofDECODER2x4 isbegin process (A, B, ENABLE)

variable ABAR, BBAR:BIT;

begin

ABAR:= not A;

BBAR:= notB;

if (ENABLE = '1')

then Z(3)


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Basic elements of the VHDL language

1. Data objects2. Literals3. Operators4. Object declarations (how to associate types with objects)

DATA OBJECTSA data object holds a value of a specified type. It is created by means of an object declaration.

An example isvariableCOUNT: INTEGER;

This results in the creation of a data object called COUNT which can hold integer values. Theobject COUNT is also declared to be ofvariable class.

Every data object belongs to one of the following three classes:1. Constant:An object of constant cla^s can hold a single value of a given type. This value is

assigned to the object before simulation starts and the value cannot be changed during the

course of the simulation.

2. Variable:An object of variable class can also hold a single value of a given type. However

in this case, different values can be assigned to the object at different times using a variable

assignment statement.

3.Signal:An object belonging to the signal class has a past history of values, a current value,

and a set of future values. Future values can be assigned to a signal object using a signal

assignment statement.

Signal objects can be regarded as wires in a circuit while variable and constant objects

are analogous to their counterparts in a high-level programming language like C or Pascal.

Signal objects are typically used to model wires and flip-flops while variable and constantobjects are typically used to model the behavior of the circuit.

An object declaration isused to declare an object, its type, and its class, and optionally assign

it a value. Some examples of object declarations of various types and classes follow.

Constant Declarations

Examples of constant declarations are

constantRISE_TIME: TIME := 10ns;

constantBUS_WIDTH: INTEGER := 8:

DFF

architecture LS_DFF_BEH ofLS_DFF is

begin

process (D, CLK)

begin

if(CLK = '1') thenQ


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The first declaration declares the object RISE_TIME that can hold a value of type TIME (apredefined type in the language) and the value assigned to the object at the start of simulation

is 10 ns. The second constant declaration declares a constant BUS_WIDTH of typeINTEGER with a value of 8.

An example of another form of constant declaration is

constantNO_OF_INPUTS: INTEGER;

The value of the constant has not been specified in this case. Such a constant is called adeferredconstantand it can appear only inside a package declaration. The complete constant

declaration with the associated value must appear in the corresponding package body.

Variable Declarations Examples of variable declarations are

variableCTRL_STATUS: BIT_VECTOR(10 downto 0);

variableSUM: INTEGERrange Oto 100 := 10;

variableFOUND, DONE: BOOLEAN;

The first declaration specifies a variable object CTRL_STATUS as an array of II

elements, with each array element of type BIT. In the second declaration, an explicit initial

value has been assigned to the variable SUM. When simulation starts, SUM will have an

initial value of 10. If no initial value is specified for a variable object, a default value is usedas an initial value. This default value is T'LEFT, where T is the object type and LEFT is a

predefined attribute of a type that gives the leftmost value in the set of values belonging totype T. In the third declaration, the initial values assigned to FOUND and DONE at start of

simulation is FALSE (FALSE is the leftmost value of the predefined type, BOOLEAN). Theinitial value for all the array elements of CTRL_STATUS is '0'.

Signal Declarations

Here are some examples of signal declarations.

signalCLOCK: BIT;

signalDATA_BUS: BIT_VECTOR(0 to 7);

signalGATE_DELAY: TIME := 10 ns;

The interpretation for these signal declarations is very similar to that of the variable

declarations. The first signal declaration declares the signal object CLOCK of type BIT and

gives it an initial value of '0' ('0' being the leftmost value of type BIT). The third signal

declaration declares a signal object GATE_DELAY of type TIME that has an initial value of

10 ns.

Other Ways to Declare Objects Not all objects in a VHDL description are created using object declarations. These other

objects are declared as

1.ports of an entity. All ports are signal objects.

2. generics of an entity .These are constant objects.

3. formal parameters of functions and procedures. Function parameters are constant objects or

signal objects while procedure parameters can belong to any object class,

4. a file declared by a file declaration.There are two other types of objects that are implicitly declared. These are the indices of a

for. . . loop statement and the generate statement. An example of such an implicit declaration

for the loop index in a for. . . loop statement is shown.

forCOUNT in 1 to 10 loop

SUM := SUM + COUNT;

end loop;


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In this for . . . loop statement, object COUNT has an implicit declaration of type INTEGERwith range I to 10, and therefore, need not be explicitly declared. The object COUNT is

created when the loop is first entered and ceases to exist after the loop is exited.

IDENTIFIERSAn identifier in VHDL is composed of a sequence of one or more characters. A legal

character is an upper-case letter (A... Z), or a lower-case letter (a. .. z), or a digit (0 . . . 9) orthe underscore ( _ ) character. The first character in an identifier must be a letter and the last

character may not be an underscore. Lower-case and upper-case letters are considered to beidentical when used in an identifier; as an example. Count, COUNT, and CouNT, all refer to

the same identifier. Also,-two underscore characters cannot appear consecutively. Some moreexamples of identifiers are

DRIVE_BUS SelectSignal RAM_AddressSET_CK_HIGH CONST32_59 r2d2

Comments in a description must be preceded by two consecutive hyphens (-); the commentextends to the end of the line. Comments can appear anywhere within a description.

Examples are

This is a comment; it ends at the end of this line. To continue a comment onto a second line, a separate

comment line must be started.

entityUART is end; --This comment starts after the entity declaration.The language defines a set of reserved words; these are listed in Appendix A.I. These words,

also called keywofds,have a specific meaning in the language, and therefore, cannot be usedas identifiers.

DATA TYPES(We have complete MODULE 2 on thisSo Well study this later in Detail)


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OPERATORSIn the order of Increasing Precedence

1.Logical 2.Relational 3.Adding 4.Multiplying 5.Misc.

The six logical

operators areand

or

nand

nor

xor

notThese

operators are

defined for the

predefined

types BIT and

BOOLEAN.They are also

defined forone-

dimensionalarrays of BIT

andBOOLEAN.

During

evaluation, bit

values '0' and

1' are treated as

FALSE andTRUE values

of the

BOOLEAN

type,

respectively.

The result of a

logical

operation hasthe same type

as its operands.The not

operator is aunaiy logical

operator andhas the same

precedence as

that of

miscellaneous

operators.

These are

=!=

=

The result types

for all relational

operations is

always

BOOLEAN. The

= (equality) and

the /=(inequality)

operators arepermitted on any

type except filetypes. The

remaining fourrelational

operators are

permitted on any

scalar type (e.g.,

integer or

enumeratedtypes) or

discrete array

type (i.e., arrays

in which

element values

belong to a

discrete type).

When operandsare discrete

array types,comparison is

performed oneelement at a

time from left toright.

These are

+-

&The operands

for the +

(addition) and -

(subtraction)

operators must

be of the same

numeric type

with the result

being of the

same numerictype. The

addition andsubtraction

operators mayalso be used as

unaryoperators, in

which case, the

operand and the

result type must

be the same.

The operandsfor the &

(concatenation)

operator can be

either a I-

dirnensional

array type or an

element type.

The result isalways an array

type. Forexample,

'0' & '1'

results in an

array ofcharacters

"01".

These are

*/

mod

rem

The *

(multiplication)

and / (division)

operators are

predefined for both

operands being of

the same integer or

floating point type.

The result is alsoof the same type.

The multiplicationoperator is also

defined for thecase when one of

the operands is ofa physical type and

the second operand

is of integer or real

type. The result is

of physical type.

For the divisionoperator, division

of an object of a

physical type by

either an integer or

a real type object

is allowed and the

result type is of the

physical type.Same goes for

mod and rem.

The

miscellaneousoperators are

abs

**The abs

(absolute)

operator is

defined for any

numeric type.

The **

(exponentiation)

operator is

defined for theleft operand to

be of integer orfloating point

type and theright operand

(i.e., theexponent) to be

of integer type

only.

The not logical

operator has the

sameprecedence as

the above two

operators


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LITERALS

1.Comments

Comments in VHDL start with two adjacent hyphens (--) and extend to

the end of the line. They have no part in the meaning of a VHDL

description.

2.IdentifiersIdentifiers in VHDL are used as reserved words and as programmer

defined names. They must conform to the rule:

identifier ::= letter { [ underline ] letter_or_digit }

Note that case of letters is not considered significant, so the identifiers catand Cat are the same. Underline characters in identifiers are significant,

so This_Name and ThisName are different identifiers.

3.NumbersLiteral numbers may be expressed either in decimal or in a base

between two and sixteen. If the literal includes a point, it represents a realnumber, otherwise it represents an integer. Decimal literals are defined

by:

decimal_literal ::= integer [ . integer ] [ exponent ]

integer ::= digit { [ underline ] digit }

exponent ::= E [ + ] integer | E - integer

Some examples are:

0 1 123_456_789 987E6 -- integer literals

0.0 0.5 2.718_28 12.4E-9 -- real literals

Based literal numbers are defined by:

based_literal ::= base # based_integer [ . based_integer ] # [ exponent ]

base ::= integer

based_integer ::= extended_digit { [ underline ] extended_digit }2-2 The VHDL Cookbook

extended_digit ::= digit | letterThe base and the exponent are expressed in decimal. The exponent

indicates the power of the base by which the literal is multiplied. Theletters A to F (upper or lower case) are used as extended digits to represent

10 to 15. Some examples:2#1100_0100# 16#C4# 4#301#E1 -- the integer 196

2#1.1111_1111_111#E+11 16#F.FF#E2 -- the real number 4095.0

4.CharactersLiteral characters are formed by enclosing an ASCII character in

single-quote marks. For example:

'A' '*' ''' ' '

5.Strings

Literal strings of characters are formed by enclosing the characters in

double-quote marks. To include a double-quote mark itself in a string, a

pair of double-quote marks must be put together. A string can be used as a

value for an object which is an array of characters.


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6.Bit StringsVHDL provides a convenient way of specifying literal values for arrays of

type bit ('0's and '1's, see Section 2.2.5). The syntax is:bit_string_literal ::= base_specifier " bit_value "

base_specifier ::= B | O | X

bit_value ::= extended_digit { [ underline ] extended_digit }

Base specifier B stands for binary, O for octal and X for hexadecimal. Someexamples:

B"1010110" -- length is 7

O"126" -- length is 9, equivalent to B"001_010_110"

SUBPROGRAMSThere are two kinds of subprograms: procedures and functions.

Both procedures and functions written in VHDL must havea body and may have declarations.

Procedures perform sequential computations and return valuesin global objects or by storing values into formal parameters.

Functions perform sequential computations and return a value

as the value of the function. Functions do not change theirformal parameters.

Subprograms may exist as just a procedure body or a function body.

Subprograms may also have a procedure declarations or a

function declaration.

When subprograms are provided in a package, the subprogram declaration

is placed in the package declaration and the subprogram body isplaced in the package body.

OVERLOADING

VHDL allows two subprograms to have the same name, provided thenumber or base types of parameters differs. The subprogram name is then

said to be overloaded. When a subprogram call is made using anoverloaded name, the number of actual parameters, their order, their base

types and the corresponding formal parameter names (if named

association is used) are used to determine which subprogram is meant. If

the call is a function call, the result type is also used. For example, suppose

we declared the two subprograms:

functioncheck_limit(value : integer) return boolean;

functioncheck_limit(value : word_32) returnboolean;

Then which of the two functions is called depends on whether a value of

type integer or word_8 is used as the actual parameter.


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Sotest := check_limit(4095)

would call the first function, andtest := check_limit(X"0000_0FFF")

would call the second function.

The designator used to define a subprogram can be either an identifieror a string representing any of the operator symbols listed in Section2.3.

The latter case allows extra operand types to be defined for those operators.

For example, the addition operator might be overloaded to add word_32

operands by declaring a function:

function"+" (a, b : word_32) return word_32 is

begin

returnint_to_word_32( word_32_to_int(a) + word_32_to_int(b) );

end"+";

Within the body of this function, the addition operator is used to add

integers, since its operands are both integers. However, in the expression:X"1000_0010" + X"0000_FFD0"

the newly declared function is called, since the operands to the additionoperator are both of type word_32. Note that it is also possible to call

operators using the prefix notation used for ordinary subprogram calls, forexample:

"+" (X"1000_0010", X"0000_FFD0")


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VHDL PROGRAMMING

By Prashant Pacific

Module II

Data Types; Pre-Defined Data Types, User-Defined Data Types, Subtypes, Arrays, Port

Array, Records, Signed and Unsigned Data Types, Data Conversion

Pre-Defined Data TypesVHDL contains a series of pre-defined data types, specified through the IEEE 1076and IEEE 1164 standards. More specifically, such data type definitions can be found

in the following packages / libraries:

PACKAGE DATA TYPES

standard of library std Defines BIT, BOOLEAN, INTEGER, and

REALdata types.

std_logic_1164 of library ieee Defines STD_LOGIC and STD_ULOGICdata types.

std_logic_arith of library ieee Defines SIGNED and UNSIGNEDdata types, plus several data conversion

functions, like conv_integer(p),conv_unsigned(p, b), conv_signed(p, b), and

conv_std_logic_vector(p, b).

std_logic_signed and std_logic_unsigned of

library ieee

Contain functions

that allow operations withSTD_LOGIC_VECTOR data to be

performed as if thedata were of type SIGNED or UNSIGNED,

respectively.

User-Defined Data TypesVHDL also allows the user to define his/her own data types. Two categories of userdefined

data types are shown below: integer and enumerated.

User-defined integer types:

TYPE my_integer IS RANGE -32 TO 32;

-- A user-defined subset of integers.

TYPE student_grade IS RANGE 0 TO 100;

-- A user-defined subset of integers or naturals.

User-defined enumerated types:

TYPE state IS (idle, forward, backward, stop);-- An enumerated data type, typical of finite state machines.

TYPE color IS (red, green, blue, white);-- Another enumerated data type.

TYPE my_logic IS ('0', '1', 'Z');-- A user-defined subset of std_logic.


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The encoding of enumerated types is done sequentially and automatically (unlessspecified otherwise by a user-defined attribute.

A SUBTYPE is a TYPE with a constraint. The main reason for using a subtype

rather than specifying a new type is that, though operations between data of dierent

types are not allowed, they are allowed between a subtype and its corresponding base

type.

Examples:

SUBTYPE natural IS INTEGER RANGE 0 TO INTEGER'HIGH;

-- As expected, NATURAL is a subtype (subset) of INTEGER.

SUBTYPE my_logic IS STD_LOGIC RANGE '0' TO 'Z';

-- Recall that STD_LOGIC=('X','0','1','Z','W','L','H',' -').

-- Therefore, my_logic=('0','1','Z').

SUBTYPE my_color IS color RANGE red TO blue;-- Since color=(red, green, blue, white), then

-- my_color=(red, green, blue).

SUBTYPE small_integer IS INTEGER RANGE -32 TO 32;-- A subtype of INTEGER.

ArraysArrays are collections of objects of the same type. They can be one-dimensional

(1D), two-dimensional (2D), or one-dimensional-by-one-dimensional (1Dx1D). They

can also be of higher dimensions, but then they are generally not synthesizable.

To specify a new array type:

TYPE type_name IS ARRAY (specification OF data_type;

To make use of the new array type:

SIGNAL signal_name: type_name [:= initial_value];

In the syntax above, a SIGNAL was declared. However, it could also be a CONSTANT

or a VARIABLE. Notice that the initial value is optional (for simulation

only).


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Port ArrayAs we have seen, there are no pre-defined data types of more than one dimension.

However, in the specification of the input or output pins (PORTS) of a circuit (which

is made in the ENTITY), we might need to specify the ports as arrays of vectors.

Since TYPE declarations are not allowed in an ENTITY, the solution is to declare

user-defined data types in a PACKAGE, which will then be visible to the whole design

(thus including the ENTITY).

RecordsRecords are similar to arrays, with the only dierence that they contain objects of

dierent types.Example:

TYPE birthday IS RECORDday: INTEGER RANGE 1 TO 31;

month: month_name;

END RECORD;

Signed and Unsigned Data TypesAs mentioned earlier, these types are defined in the std_logic_arith package of the

ieee library. Their syntax is illustrated in the examples below.

Examples:

SIGNAL x: SIGNED (7 DOWNTO 0);

SIGNAL y: UNSIGNED (0 TO 3);

Notice that their syntax is similar to that of STD_LOGIC_VECTOR, not like that

of an INTEGER, as one might have expected.To use SIGNED or UNSIGNED data types, the std_logic_arith package, of

the ieee library, must be declared.Despite their syntax, SIGNED and UNSIGNED

data types are intended mainly for arithmetic operations, that is, contrary toSTD_LOGIC_VECTOR, they accept arithmetic operations. On the other hand,

logical operations are not allowed. With respect to relational (comparison) operations,there are no restrictions.

Example: Legal and illegal operations with

signed/unsigned data types.

LIBRARY ieee;USE ieee.std_logic_1164.all;

USE ieee.std_logic_arith.all; -- extra package

necessary

...

SIGNAL a: IN SIGNED (7 DOWNTO 0);

SIGNAL b: IN SIGNED (7 DOWNTO 0);SIGNAL x: OUT SIGNED (7 DOWNTO 0);

...

v


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Despite the constraint mentioned above, there is a simple way of allowing data oftype STD_LOGIC_VECTOR to participate directly in arithmetic operations. For

that, the ieee library provides two packages, std_logic_signed and std_logic_unsigned,which allow operations with STD_LOGIC_VECTOR data to be performed as if the

data were of type SIGNED or UNSIGNED, respectively.

Example: Arithmetic operations with std_logic_vector.

LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_unsigned.all; -- extra package included

SIGNAL a: IN STD_LOGIC_VECTOR (7 DOWNTO 0);SIGNAL b: IN STD_LOGIC_VECTOR (7 DOWNTO 0);

SIGNAL x: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);...

v


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Example: Data conversion.

LIBRARY ieee;USE ieee.std_logic_1164.all;

USE ieee.std_logic_arith.all;

...

SIGNAL a: IN UNSIGNED (7 DOWNTO 0);SIGNAL b: IN UNSIGNED (7 DOWNTO 0);

SIGNAL y: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);

...

y


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VHDL PROGRAMMING

By Prashant Pacific

Module III

Sequential codes:

PROCESS: Signals and Variables, IF, WAIT, CASE, LOOP, CASE versus IF, CASE

versus WHEN, Bad Clocking, Using Sequential Code to Design Combinational Circuits

Description and design of sequential circuits using VHDL

SEQUENTIAL CODES

VHDL code is inherently concurrent. PROCESSES,

FUNCTIONS, and PROCEDURES are the only sections of code that are executed

sequentially. However, as a whole, any of these blocks is still concurrent with anyother statements placed outside it.

One important aspect of sequential code is that it is not limited to sequential logic.Indeed, with it we can build sequential circuits as well as combinational circuits. Sequential

code is also called behavioral code.

PROCESSA PROCESS is a sequential section of VHDL code. It is characterized by the presence

of IF, WAIT, CASE, or LOOP, and by a sensitivity list (except when WAIT isused). A PROCESS must be installed in the main code, and is executed every time a

signal in the sensitivity list changes (or the condition related to WAIT is fulfilled). Its

syntax is shown below.

[label:] PROCESS (sensitivity list)

[VARIABLE name type [range] [:= initial_value;]]

BEGIN

(sequential code)

END PROCESS [label];

VARIABLES are optional. If used, they must be declared in the declarative part

of the PROCESS (before the word BEGIN, as indicated in the syntax above). The

initial value is not synthesizable, being only taken into consideration in simulations.

The use of a label is also optional. Its purpose is to improve code readability. Thelabel can be any word, except VHDL reserved words.

SIGNALS AND VARIABLES

VHDL has two ways of passing non-static values around: by means of a SIGNAL

or by means of a VARIABLE.

A SIGNAL can be declared in a PACKAGE,ENTITY or ARCHITECTURE (in its

declarative part), while

A VARIABLE canonly be declared inside a piece of sequential code (in a PROCESS, for

example).

Therefore, while the value of the former can be global, the latter is always local.

The value of a VARIABLE can never be passed out of the PROCESS directly; if

necessary, then it must be assigned to a SIGNAL. On the other hand, the update of aVARIABLE is immediate, that is, we can promptly count on its new value in the

next line of code. That is not the case with a SIGNAL (when used in a PROCESS),


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for its new value is generally only guaranteed to be available after the conclusion ofthe present run of the PROCESS.

SIGNAL Assignment Statement-signal-object


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wait onsensitivity-listuntil boolean-expression for time-expression;

Some examples ofwait statements are

wait on A, B, C; -- statement 1

wait until (A = B); -- statement 2

wait for 10ns; -- statement 3

wait on CLOCKfor 20ns; -- statement 4

wait until (SUM > 100) for 50 ms; -- statement 5

IF

An if statement selects a sequence of statements for execution based on the value of a

condition. The condition can be any expression that evaluates to a boolean value. The general

form of an if statement is

ifboolean-expressionthen

sequential-statements

[ elsifboolean-expression thensequential-statements]

[ elsesequential-statements]

end if;

The if statement is executed by checking each condition sequentially until the first true

condition is found; then, the set of sequential statements associated with this condition is

executed. The if statement can have zero or more else if clauses and an optional else clause.

An if statement is also a sequential statement, and therefore, the previous syntax allows for

arbitrary nesting of if statements.

CASE

CASE is another statement intended exclusively for sequential code (along with IF,LOOP,and WAIT). Its syntax is shown below.

CASE identifierIS

WHEN value => assignments;

WHEN value => assignments;

...

END CASE;


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A model for a 4*1 multiplexer using a case statement is shown next.

entityMUX is

port(A, B, C, D: in BIT; CTRL: in BIT_VECTOR(0 to 1);

Z: out BIT);

endMUX;

architectureMUX_BEHAVIORofMUX is

constantMUX_DELAY: TIME := 10 ns;

begin

PMUX: process (A, B, C, D, CTRL)

variableTEMP: BIT;

begin

caseCTRL is

when"00" => TEMP := A:

when"01" => TEMP := B;

when"10" => TEMP := C;

when"11" => TEMP := D;

end case;

Z


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CASE versus IF

Though in principle the presence of ELSE in the IF/ELSE statement might infer the

implementation of a priority decoder (which would never occur with CASE), this will

generally not happen. For instance, when IF (a sequential statement) is used to implement

a fully combinational circuit, a multiplexer might be inferred instead. Therefore,

after optimization, the general tendency is for a circuit synthesized from a

VHDL code based on IF not to dier from that based on CASE.

NULL

The statementnull;is a sequential statement that does not cause any action to take place andexecution continues with the next statement. One example of this statement's use is in an if

statement or in a case statement where for certain conditions, it may be useful or necessary to

explicitly specify that no action needs to be performed.

LOOP

Aloop statement is used to iterate through a set of sequential statements. The syntax of a loopstatement is

[ loop-label: ] iteration-scheme loop

sequential-statements

end loop [ loop-label] ;

There are three types of iteration schemes.

FOR / LOOP: The loop is repeated a fixed number of times.

[label:] FOR identifier IN range LOOP(sequential statements)END LOOP [label];

WHILE / LOOP: The loop is repeated until a condition no longer holds.

[label:] WHILE condition LOOP(sequential statements)END LOOP [label];


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EXIT: Used for ending the loop.

[label:] EXIT [label] [WHEN condition];

NEXT: Used for skipping loop steps

[label:] NEXT [loop_label] [WHEN condition];

Bad ClockingThe compiler will generally not be able to synthesize codes that contain assignments

to the same signal at both transitions of the reference (clock) signal (that is, at the

rising edge plus at the falling edge). This is particularly true when the target technology

contains only single-edge flip-flops (CPLDs, for exampleappendix A). In

this case, the compiler might display a message of the type signal does not hold

value after clock edge or similar.

Using Sequential Code to Design Combinational CircuitsWe have already seen that sequential code can be used to implement either sequential

or combinational circuits. In the former case, registers are necessary, so will be inferred

by the compiler. However, this should not happen in the latter case. Moreover,if the code is intended for a combinational circuit, then the complete truth-tableshould be clearly specified in the code.

In order to satisfy the criteria above, the following rules should be observed:

Rule 1: Make sure that all input signals used (read) in the PROCESS appear in itssensitivity list.

Rule 2: Make sure that all combinations of the input/output signals are included inthe code; that is, make sure that, by looking at the code, the circuits complete truthtable

can be obtained (indeed, this is true for both sequential as well as concurrent

code).

Failing to comply with rule 1 will generally cause the compiler to simply issue awarning saying that a given input signal was not included in the sensitivity list, and

then proceed as if the signal were included. Even though no damage is caused to the

design in this case, it is a good design practice to always take rule 1 into consideration.

With respect to rule 2, however, the consequences can be more serious because

incomplete specifications of the output signals might cause the synthesizer to infer

latches in order to hold their previous values. This fact is illustrated in the example

below.


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VHDL PROGRAMMING

By Prashant Pacific

Module IV

Standard combinational modules, Design of a Serial Adder with Accumulator, State

Graph for Control Network, design of a Binary Multiplier, Multiplication of a SignedBinary Number, Design of a Binary Divider.


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VHDL PROGRAMMING

By Prashant Pacific

Module V

Micro programmed Controller, Structure of a micro programmed controller, Basic

component of a micro system, memory subsystem. Overview of PAL, PLA, FPGA,CPLD.

Microprogramming is an orderly method of designing the control unit of a conventionalcomputer(Wil es 1951). The term microprogramming is based on the analogy between

sequence oftransferrequired to execute a machine instruction and the sequence ofindividualinstructions in conventional userprogram. Each step is calledmicroinstruction and complete

set of steps required to process a machine instruction is called themicro program.

Block diagram for a MCU

In a mic

p

mmedc t

lunit, the values of control signals are read from an

appropriate address location in a ROM (instead of being generated by combinationallogicgates). The contents of each address in the ROM are called ac nt

lword.

Basic microprogrammed control unit (example)

We use two-way branching address generation Each control word contains 64 bits of data

The condition select field (CW(63:40)) contains information needed to selectthe input

condition signalthatis used to compute the address ofthe nextinstruction. In the BMCU we

use a one-hot code to selectthe condition signal.

MAR - a-bit address

register

ROM - memory with a w-

bit words

MIR - w- bit instruction

register

AGP - address generating

lo ic


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If Ci is selected and Ci = 1 then address NAD field is the address of the next control word to

be fetched. If Ci = 0, then the memory address [MAR] is incremented to compute the next

address.

Control word

Every designer must observe the constraints imposed by the controller. These constraints

include such things as the number of control signals that can be generated, the number of

status signals that can be handled, and limits imposed by the address generation logic.

The maximum number of control signals is 32. ROM size is 256 words.

Address generation logic

The correct sequence of control signals is obtained by generating the proper sequence of

addresses at the ROM inputs.

The address generating logic varies considerably from design to design and is a major

contributor to the constraints imposed by the controller.

Timing signals for the control unit and the data unit must be closely coordinated.


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The controller works best if the sequencing of addresses is relatively simple. Usually, the

address generating logic circuit (AG) is a counter with the option to parallel load a new

address when one wishes to jump to a new point in the control sequence. If the controller

usually goes to the next higher sequential address for the next set of control signal values

(increment) with just an occasional need to parallel load a new address (branch), the AG canbe a low complexity circuit.

Address generation logic organization (example

Address Generation Logic for BMCUc

anbe

designe

d using

a

vec

tormu

lti

lexer.

Synthesis of microprogrammed controllers

1. Prepare a table showing all transitions from each state and the conditions that defineeach transition by scanning the statements in the VHDL description.

2. Make a list of the conditions from step 1. After the assignment of ROM addresses tostates, some of these conditions may not be needed.

3. Identify a reset state.


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4. Assign a ROM address to each state.

5. Remove the redundant signals from the condition list created in step2 and assign thecondition signals to the condition inputs in an arbitrary manner.

6. Create a list of transfers during each state and a list of outputs required during eachstate.

7. From the list of transfers and outputs created in step 6, generate a list of controlsignals needed to time the transfers and outputs.

8. Draw a block diagram showing the condition and control signals produced.

9. Determine the ROM program using the information in the lists produced in steps 1-8.This procedure is similar to that performed by an assembler program.

BASIC LAYOUT OF A MICROPROGRAMMED CONTROL

UNIT

Control memory stores a microprogram corresponding to each op-code of a conventionalinstruction.

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