VHDL Examples

VHDL Examples

Subra GanesanReference: Professor Haskell’s Notes, Digital design with VHDL book by Vranesic

n-line 2-to-1 Multiplexer

n-line2 x 1 MUX

a(n-1:0)

b(n-1:0)y(n-1:0)

sel

sel y 0 a 1 b

2

library IEEE;use IEEE.std_logic_1164.all; entity mux2g is generic (width:positive); port ( a: in STD_LOGIC_VECTOR(width-1 downto 0); b: in STD_LOGIC_VECTOR(width-1 downto 0); sel: in STD_LOGIC; y: out STD_LOGIC_VECTOR(width-1 downto 0) );end mux2g;

An n-line 2 x 1 MUX

a(n-1:0)

b(n-1:0)

y(n-1:0)

sel

n-line2 x 1MUX

3


Entity Each entity must begin with these library and use

statements

port statement defines inputs and outputs

generic statement defineswidth of bus

4


Entity

Mode: in or out

Data type: STD_LOGIC,STD_LOGIC_VECTOR(width-1 downto 0);

5

Standard Logic

type std_ulogic is ( ‘U’, -- Uninitialized‘X’ -- Forcing unknown‘0’ -- Forcing zero‘1’ -- Forcing one‘Z’ -- High impedance‘W’ -- Weak unknown‘L’ -- Weak zero‘H’ -- Weak one‘-’); -- Don’t care

library IEEE;use IEEE.std_logic_1164.all;

6

Standard Logic

Type std_ulogic is unresolved.

Resolved signals provide a mechanismfor handling the problem of multipleoutput signals connected to one signal.

subtype std_logic is resolved std_ulogic;

7

architecture mux2g_arch of mux2g isbegin mux2_1: process(a, b, sel) begin if sel = '0' then y <= a; else y <= b; end if; end process mux2_1;end mux2g_arch;

Architecture

a(n-1:0)

b(n-1:0)

y(n-1:0)

sel

n-line2 x 1MUX

Note: <= is signal assignment

8

architecture mux2g_arch of mux2g isbegin mux2_1: process(a, b, sel) begin if sel = '0' then y <= a; else y <= b; end if; end process mux2_1;end mux2g_arch;

Architecture entity name

process sensitivity list

Sequential statements (if…then…else) must

be in a process

Note begin…endin processNote begin…end

in architecture9

library IEEE;use IEEE.STD_LOGIC_1164.all;use IEEE.std_logic_unsigned.all;

entity Lab1 is port(

SW : in STD_LOGIC_VECTOR(7 downto 0); BTN0 : in STD_LOGIC; LD : out STD_LOGIC_VECTOR(3 downto 0)

);end Lab1;

4-line2-to-1MUX

a

b

y

sel

SW(7:4)

SW(3:0)

BTN0

LD(3:0)

Top-level design for Lab 1

10

architecture Lab1_arch of Lab1 is

component mux2ggeneric(

width : POSITIVE);port(

a : in std_logic_vector((width-1) downto 0);b : in std_logic_vector((width-1) downto 0);sel : in std_logic;y : out std_logic_vector((width-1) downto 0));

end component;

constant bus_width: integer := 4;begin

mux2: mux2g generic map(width => bus_width) port map(a => SW(7 downto 4),b => SW(3 downto 0), sel => BTN0, y => LD);

end Lab1_arch;

4-line2-to-1MUX

a

b

y

sel

SW(7:4)

SW(3:0)

BTN0

LD(3:0)

11

Example of case statement

architecture mux4g_arch of mux4g isbegin process (sel, a, b, c, d) begin case sel is when "00" => y <= a; when "01" => y <= b; when "10" => y <= c; when others => y <= d; end case; end process;end mux4g_arch;

Must include ALL possibilitiesin case statement

Note implies operator =>

Sel y“00” a“01” b“10” c“11” d

12

7-Segment Display

D a b c d e f g0 1 1 1 1 1 1 01 0 1 1 0 0 0 02 1 1 0 1 1 0 13 1 1 1 1 0 0 14 0 1 1 0 0 1 15 1 0 1 1 0 1 16 1 0 1 1 1 1 17 1 1 1 0 0 0 0

a

b

c

d

e

f g

a

b

c

d

e

f g

D a b c d e f g8 1 1 1 1 1 1 19 1 1 1 1 0 1 1A 1 1 1 0 1 1 1b 0 0 1 1 1 1 1C 1 0 0 1 1 1 0d 0 1 1 1 1 0 1E 1 0 0 1 1 1 1F 1 0 0 0 1 1 1

Truth tableseg7decD(3:0) AtoG(6:0)

13

case(D) 0: AtoG = 7'b1111110; 1: AtoG = 7'b0110000; 2: AtoG = 7'b1101101; 3: AtoG = 7'b1111001; 4: AtoG = 7'b0110011; 5: AtoG = 7'b1011011; 6: AtoG = 7'b1011111; 7: AtoG = 7'b1110000; 8: AtoG = 7'b1111111; 9: AtoG = 7'b1111011; 'hA: AtoG = 7'b1110111; 'hb: AtoG = 7'b0011111; 'hC: AtoG = 7'b1001110; 'hd: AtoG = 7'b0111101; 'hE: AtoG = 7'b1001111; 'hF: AtoG = 7'b1000111;

default: AtoG = 7'b1111110; // 0 endcase

7-Segment Display

a

b

c

d

e

f g

a

b

c

d

e

f g

Behavior

Verilog

seg7decD(3:0) AtoG(6:0)

14

-- seg7decwith digit select

ssg <= "1001111" when "0001", --1"0010010" when "0010", --2"0000110" when "0011", --3"1001100" when "0100", --4"0100100" when "0101", --5"0100000" when "0110", --6"0001111" when "0111", --7"0000000" when "1000", --8"0000100" when "1001", --9"0001000" when "1010", --A"1100000" when "1011", --b"0110001" when "1100", --C"1000010" when "1101", --d"0110000" when "1110", --E"0111000" when "1111", --F"0000001" when others; --0

7-Segment Display

a

b

c

d

e

f g

a

b

c

d

e

f g

Behavior(Active LOW)

VHDL

AtoG

seg7decdigit(3:0) sseg(6:0)

15

Comparators

XNOR

X Y Z0 0 10 1 01 0 01 1 1

Z = !(X $ Y)Z = X xnor YZ = ~(X @ Y)

Recall that an XNOR gate can be used as an equality detector

XY

Zif X = Y then Z <= '1';else Z <= '0';end if;

16

4-Bit Equality Comparator

A0

A1

A2

A3

B0

B1

B2

B3

A_EQ_B

C0

C1

C3

C2

A: in STD_LOGIC_VECTOR(3 downto 0);B: in STD_LOGIC_VECTOR(3 downto 0);A_EQ_B: out STD_LOGIC;

17

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity eqdet4 is Port ( A : in std_logic_vector(3 downto 0); B : in std_logic_vector(3 downto 0); A_EQ_B : out std_logic);end eqdet4;

architecture Behavioral of eqdet4 issignal C: std_logic_vector(3 downto 0);begin

C <= A xnor B;

A_EQ_B <= C(0) and C(1) and C(2) and C(3);

end Behavioral;

A0

A1

A2

A3

B0

B1

B2

B3

A_EQ_B

C0

C1

C3

C2

18

Comparators

comp

A(n-1:0)

B(n-1:0)

A_EQ_B

A_GT_B

A_LT_B

A_UGT_B

A_ULT_B

A, Bsigned

A, Bunsigned

Signed: 2's complement signed numbers

19

-- Comparator for unsigned and signed numbers

library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all;use IEEE.std_logic_unsigned.all;

entity comp is generic(width:positive); port (

A: in STD_LOGIC_VECTOR(width-1 downto 0);B: in STD_LOGIC_VECTOR(width-1 downto 0);A_EQ_B: out STD_LOGIC;A_GT_B: out STD_LOGIC;A_LT_B: out STD_LOGIC;A_ULT_B: out STD_LOGIC;A_UGT_B: out STD_LOGIC

);end comp;

compA(n-1:0)

B(n-1:0)

A_EQ_BA_GT_BA_LT_BA_UGT_BA_ULT_B

20

architecture comp_arch of comp isbegin CMP: process(A,B) variable AVS, BVS: signed(width-1 downto 0); begin for i in 0 to width-1 loop

AVS(i) := A(i);BVS(i) := B(i);

end loop;A_EQ_B <= '0';A_GT_B <= '0';A_LT_B <= '0';A_ULT_B <= '0';A_UGT_B <= '0';

if (A = B) thenA_EQ_B <= '1';

end if; if (AVS > BVS) then

A_GT_B <= '1';end if; if (AVS < BVS) then

A_LT_B <= '1';end if; if (A > B) then

A_UGT_B <= '1';end if; if (A < B) then

A_ULT_B <= '1';end if;

end process CMP;end comp_arch;

compA(n-1:0)

B(n-1:0)

A_EQ_BA_GT_BA_LT_BA_UGT_BA_ULT_B

Note: All outputs must beassigned some value.

The last signal assignmentin a process is the value assigned

21

4-Bit Comparator

22

Full Adder

0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1

Ci Ai Bi Si Ci+1

0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1

Ci Ai Bi Si Ci+1

Truth table

Ci CombinationalLogic

CombinationalLogicAi

Bi

Si

Ci+1

Behavior

Ci+1:Si = Ci + Ai + Bi

23

Full Adder

Full Adder

A B

C C

S

i i

i+1 i

i

Block Diagram

24

4-Bit Adder

C 1 1 1 0 0:A 0 1 1 0 1 0:B 0 0 1 1 1C4:S 1 0 1 0 0

Full Adder

A B

0C

S

0 0

1

0

Full Adder

A B

C

S

1 1

2

1

Full Adder

A B

C

S

2 2

3

2

Full Adder

A B

C S

3 3

4 3

C 0

25

library IEEE;use IEEE.STD_LOGIC_1164.all;use IEEE.STD_LOGIC_unsigned.all;

entity adder4 is port(

A : in STD_LOGIC_VECTOR(3 downto 0); B : in STD_LOGIC_VECTOR(3 downto 0); carry : out STD_LOGIC; S : out STD_LOGIC_VECTOR(3 downto 0)

);end adder4;

architecture adder4 of adder4 isbegin

process(A,B)variable temp: STD_LOGIC_VECTOR(4 downto 0);begin

temp := ('0' & A) + ('0' & B);S <= temp(3 downto 0);carry <= temp(4);

end process;end adder4; 26

4-Bit Adder

27

3-to-8 Decoder

Behaviorfor i in 0 to 7 loop if(i = conv_integer(A)) then Y(i) <= ‘1’; else Y(i) <= ‘0’; end if;end loop;

A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

0 0 0 1 0 0 0 0 0 0 00 0 1 0 1 0 0 0 0 0 00 1 0 0 0 1 0 0 0 0 00 1 1 0 0 0 1 0 0 0 01 0 0 0 0 0 0 1 0 0 01 0 1 0 0 0 0 0 1 0 01 1 0 0 0 0 0 0 0 1 01 1 1 0 0 0 0 0 0 0 1

A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

0 0 0 1 0 0 0 0 0 0 00 0 1 0 1 0 0 0 0 0 00 1 0 0 0 1 0 0 0 0 00 1 1 0 0 0 1 0 0 0 01 0 0 0 0 0 0 1 0 0 01 0 1 0 0 0 0 0 1 0 01 1 0 0 0 0 0 0 0 1 01 1 1 0 0 0 0 0 0 0 1

A: in STD_LOGIC_VECTOR(2 downto 0);Y: out STD_LOGIC_VECTOR(0 to 7);

28

library IEEE;use IEEE.STD_LOGIC_1164.all;use IEEE.STD_LOGIC_arith.all;use IEEE.STD_LOGIC_unsigned.all;

entity decode38 is port(

A : in STD_LOGIC_VECTOR(2 downto 0); Y : out STD_LOGIC_VECTOR(0 to 7)

);end decode38;

architecture decode38 of decode38 isbegin process(A) variable j: integer; begin

j := conv_integer(A);for i in 0 to 7 loop

if(i = j) then Y(i) <= '1'; else Y(i) <= '0'; end if;

end loop; end process;end decode38;

3-to-8 Decoder

29

Shifters

Shift rightShift leftArithmetic shift right

Shifter

D3 D2 D1 D0

Y3 Y2 Y1 Y0

s1

s0

s1 s0 0 0 noshift D3 D2 D1 D0 0 1 U2/ 0 D3 D2 D1 1 0 2* D2 D1 D0 0 1 1 2/ D3 D3 D2 D1

30

library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_unsigned.all;

entity shifter is generic(width:positive := 4); port ( D: in STD_LOGIC_VECTOR(width-1 downto 0); s: in STD_LOGIC_VECTOR(1 downto 0); Y: out STD_LOGIC_VECTOR(width-1 downto 0) );end shifter;

shift4.vhd

Shifter

D3 D2 D1 D0

Y3 Y2 Y1 Y0

s1

s0

31

architecture shifter_arch of shifter isbegin shift_1: process(D, s) begin case s is when "00" => -- no shift Y <= D;

when "01" => -- U2/Y <= '0' & D(width-1 downto 1);

when "10" => -- 2*Y <= D(width-2 downto 0) & '0';

when "11" => -- 2/

Y <= D(width-1) & D(width-1 downto 1);

when others => -- no shiftY <= D;

end case; end process shift_1;end shifter_arch;

32

Code Converters

• Gray Code Converter• Binary-to-BCD Converter

33

Gray Code

One method for generating a Gray code sequence:Start with all bits zero and successively flip the right-most bit that produces a new string.

Binary coding {0...7}: {000, 001, 010, 011, 100, 101, 110, 111}

Gray coding {0...7}: {000, 001, 011, 010, 110, 111, 101, 100}

Definition: An ordering of 2n binary numbers such that only one bit changes from one entry to the next.

Not unique

34

Binary coding {0...7}: {000, 001, 010, 011, 100, 101, 110, 111}

Gray coding {0...7}: {000, 001, 011, 010, 110, 111, 101, 100}

Binary - Gray Code ConversionsGray code: G(i), i = n – 1 downto 0Binary code: B(i), i = n – 1 downto 0

Convert Binary to Gray: Copy the most significant bit. For each smaller iG(i) = B(i+1) xor B(i)

Convert Gray to Binary: Copy the most significant bit. For each smaller iB(i) = B(i+1) xor G(i)

35

library IEEE;use IEEE.STD_LOGIC_1164.all;

entity bin2gray is generic(width:positive := 3); port(

B : in STD_LOGIC_VECTOR(width-1 downto 0); G : out STD_LOGIC_VECTOR(width-1 downto 0)

);end bin2gray;

architecture bin2gray of bin2gray isbegin

process(B)begin

G(width-1) <= B(width-1);for i in width-2 downto 0 loop

G(i) <= B(i+1) xor B(i);end loop;

end process;

end bin2gray;

bin2gray.vhd

36

library IEEE;use IEEE.STD_LOGIC_1164.all;

entity gray2bin is generic(width:positive := 3); port(

G : in STD_LOGIC_VECTOR(width-1 downto 0); B : out STD_LOGIC_VECTOR(width-1 downto 0)

);end gray2bin;

architecture gray2bin of gray2bin isbegin

process(G)variable BV: STD_LOGIC_VECTOR(width-1 downto 0);begin

BV(width-1) := G(width-1);for i in width-2 downto 0 loop

BV(i) := BV(i+1) xor G(i);end loop;B <= BV;

end process;

end gray2bin;

gray2bin.vhd

37

Binary-to-BCD Conversion

• Shift and add 3 algorithm• RTL solution• Behavioral solution

38

Shift and Add-3 Algorithm 11. Shift the binary number left one bit.22. If 8 shifts have taken place, the BCD number is in the

Hundreds, Tens, and Units column.33. If the binary value in any of the BCD columns is 5 or greater,

add 3 to that value in that BCD column.44. Go to 1.

Operation Hundreds Tens Units Binary HEX F F Start 1 1 1 1 1 1 1 1

39

Operation Hundreds Tens Units Binary B 7 4 3 0

HEX F F Start 1 1 1 1 1 1 1 1

Shift 1 1 1 1 1 1 1 1 1 Shift 2 1 1 1 1 1 1 1 1 Shift 3 1 1 1 1 1 1 1 1 Add 3 1 0 1 0 1 1 1 1 1 Shift 4 1 0 1 0 1 1 1 1 1 Add 3 1 1 0 0 0 1 1 1 1 Shift 5 1 1 0 0 0 1 1 1 1 Shift 6 1 1 0 0 0 1 1 1 1 Add 3 1 0 0 1 0 0 1 1 1 1 Shift 7 1 0 0 1 0 0 1 1 1 1 Add 3 1 0 0 1 0 1 0 1 0 1 Shift 8 1 0 0 1 0 1 0 1 0 1 BCD 2 5 5

P 9 8 7 4 3 0 z 17 16 15 12 11 8 7 4 3 0

Steps to convert an 8-bit binary number to BCD

40

Truth table for Add-3 Module

A3 A2 A1 A0 S3 S2 S1 S0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 1 0 1 0 0 0 1 0 0 0 1 0 1 1 0 0 0 0 1 1 0 1 0 0 1 0 1 1 1 1 0 1 0 1 0 0 0 1 0 1 1 1 0 0 1 1 1 0 0 1 0 1 0 X X X X 1 0 1 1 X X X X 1 1 0 0 X X X X 1 1 0 1 X X X X 1 1 1 0 X X X X 1 1 1 1 X X X X

C

A3 A2 A1 A0

S3 S2 S1 S0

41

C1

C2

C3

C4C6

C5C7

B7

0

0 B6 B5 B4 B3 B2 B1 B0

P7 P6 P5 P4 P3 P2 P1 P0P9 P8

8-bit binary input

BCD output

hunds tens units

1 1 1 1 1 1 1 1

1 0 1 0

1 0 0 0

1 1 0 0 0 1

1 0 0 1 0 0 1 1

1 0 0 1 0 1 0 1 0 1

1 1

2 5 5

Hex FF

Binary-to-BCDConverter

RTL Solution

42

-- Title: Binary-to-BCD Converter

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

entity binbcd is

port (

B: in STD_LOGIC_VECTOR (7 downto 0);

P: out STD_LOGIC_VECTOR (9 downto 0)

);

end binbcd;

Binary-to-BCD Converter: Behavioral Solution

43

architecture binbcd_arch of binbcd isbegin bcd1: process(B)

variable z: STD_LOGIC_VECTOR (17 downto 0);

begin for i in 0 to 17 loop

z(i) := '0'; end loop; z(10 downto 3) := B; for i in 0 to 4 loop

if z(11 downto 8) > 4 then z(11 downto 8) := z(11 downto 8) + 3;end if;if z(15 downto 12) > 4 then z(15 downto 12) := z(15 downto 12) + 3;end if;z(17 downto 1) := z(16 downto 0);

end loop;P <= z(17 downto 8);

end process bcd1; end binbcd_arch;

Operation Hundreds Tens Units Binary B 7 4 3 0

HEX F F Start 1 1 1 1 1 1 1 1

Shift 1 1 1 1 1 1 1 1 1 Shift 2 1 1 1 1 1 1 1 1 Shift 3 1 1 1 1 1 1 1 1 Add 3 1 0 1 0 1 1 1 1 1 Shift 4 1 0 1 0 1 1 1 1 1 Add 3 1 1 0 0 0 1 1 1 1 Shift 5 1 1 0 0 0 1 1 1 1 Shift 6 1 1 0 0 0 1 1 1 1 Add 3 1 0 0 1 0 0 1 1 1 1 Shift 7 1 0 0 1 0 0 1 1 1 1 Add 3 1 0 0 1 0 1 0 1 0 1 Shift 8 1 0 0 1 0 1 0 1 0 1 BCD 2 5 5

P 9 8 7 4 3 0 z 17 16 15 12 11 8 7 4 3 0

44

C1

C2

C3

C4C14

C5C15

B150 B14 B13 B12 B11B10 B9 B8

16-bit binary input

B7 B6 B5 B4 B3 B2 B1 B0

BCD output

hundreds tens units

C6C16

C7C17C24

C8C18C25

C9C19C26

C11C21C28C32

C12C22C29C33

C13C23C30C34

0

0

C10C20C27C31

0

thousandsten thousands

P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0P19 P17P18 P16

16-bitBinary-to-BCDConverter

45

module binbcd(B,P);

input [15:0] B;

output [15:0] P;

reg [15:0] P;

reg [31:0] z;

integer i;

Verilog binbcd C1

C2

C3

C4C14

C5C15

B150 B14 B13 B12 B11B10 B9 B8

16-bit binary input

B7 B6 B5 B4 B3 B2 B1 B0

BCD output

hundreds tens units

C6C16

C7C17C24

C8C18C25

C9C19C26

C11C21C28C32

C12C22C29C33

C13C23C30C34

0

0

C10C20C27C31

0



46

always @(B) begin for(i = 0; i <= 31; i = i+1)

z[i] = 0; z[18:3] = B;

for(i = 0; i <= 12; i = i+1) begin

if(z[19:16] > 4)z[19:16] = z[19:16] + 3;

if(z[23:20] > 4) z[23:20] = z[23:20] + 3;

if(z[27:24] > 4) z[27:24] = z[27:24] + 3;

if(z[31:28] > 4) z[31:28] = z[31:28] + 3;

z[31:1] = z[30:0]; end P = z[31:16]; end endmodule

C1

C2

C3

C4C14

C5C15

B150 B14 B13 B12 B11B10 B9 B8

16-bit binary input

B7 B6 B5 B4 B3 B2 B1 B0

BCD output

hundreds tens units

C6C16

C7C17C24

C8C18C25

C9C19C26

C11C21C28C32

C12C22C29C33

C13C23C30C34

0

0

C10C20C27C31

0



47

Arithmetic Logic Units

• ALU1– Shifting, Increment and Decrement Instructions

• ALU2– Arithmetic and Logic Instructions

• ALU3– Comparators

48

a(n-1:0) y(n-1:0)

Sel(2:0)

n-line

ALU1

Sel y Name

'000' a + 1 1+

'001' a - 1 1-

'010' not a invert

'011' LSL a 2*

'100' LSR a U2/

'101' ASR a 2/

'110' All ones true

'111' All zeros false

ALU1Shifting, Increment and Decrement Instructions

49


entity alu1 is generic(width:positive); port ( a: in STD_LOGIC_VECTOR(width-1 downto 0); sel: in STD_LOGIC_VECTOR(2 downto 0); y: out STD_LOGIC_VECTOR(width-1 downto 0) );end alu1;

a(n-1:0) y(n-1:0)

Sel(2:0)

n-line

ALU1

alu1.vhd

50

architecture alu1_arch of alu1 isbegin alu_1: process(a, sel) variable true, false: STD_LOGIC_VECTOR (width-1 downto 0); begin

-- true is all ones; false is all zeros for i in 0 to width-1 loop

true(i) := '1';false(i) := '0';

end loop;case sel is

when "000" => -- 1+ y <= a + 1; when "001" => -- 1- y <= a - 1; when "010" => -- invert

y <= not a; when "011" => -- 2*

y <= a(width-2 downto 0) & '0'; when "100" => -- U2/

y <= '0' & a(width-1 downto 1); when "101" => -- 2/

y <= a(width-1) & a(width-1 downto 1); when "110" => -- TRUE

y <= true; when others => -- FALSE

y <= false; end case; end process alu_1;end alu1_arch;

51

Sel y Name

'000' a + b +

'001' b - a -

'010' a and b AND

'011' a or b OR

'100' a xor b XOR

'101' true if a = 0

false otherwise

0=

'110' true if a < 0

false otherwise

0<

'111' true if b > a

false otherwise

U>

ALU2Arithmetic and Logic Instructions

a(n-1:0)y(n-1:0)

sel(2:0)

n-line

ALU2

b(n-1:0)

52


entity alu2 is generic(width:positive); port ( a: in STD_LOGIC_VECTOR(width-1 downto 0);

b: in STD_LOGIC_VECTOR(width-1 downto 0); sel: in STD_LOGIC_VECTOR(2 downto 0); y: out STD_LOGIC_VECTOR(width-1 downto 0) );end alu2;

alu2.vhd

a(n-1:0)y(n-1:0)

sel(2:0)

n-line

ALU2

b(n-1:0)

53

architecture alu2_arch of alu2 isbegin alu_2: process(a, b, sel) variable true, false: STD_LOGIC_VECTOR (width-1 downto 0); variable Z: STD_LOGIC; begin

Z := '0'; for i in 0 to width-1 loop

true(i) := '1'; -- true is all ones; false(i) := '0'; -- false is all zeros Z := Z or a(i); -- Z = '0' if all a(i) = '0'

end loop;

case sel is when "000" => -- + y <= a + b; when "001" => -- - y <= b - a; when "010" => -- AND

y <= a and b;

when "011" => -- OR y <= a or b;

when "100" => -- XOR y <= A xor B;

54

when "101" => -- 0= NOT if (Z = '0') then

y <= true; else y <= false; end if;

when "110" => -- 0< if (a(width-1) = '1') then y <= true; else y <= false; end if;

when "111" => -- U> if (b > a) then y <= true;

else y <= false; end if; when others => null;

end case; end process alu_2;end alu2_arch; 55

Sel y Name

'000' true if b = a

false otherwise

=

'001' true if b /= a

false otherwise

<>

'010' true if b < a (unsigned)

false otherwise

U<

'011' true if b > a (unsigned)

false otherwise

U>

'100' true if b <= a (unsigned)

false otherwise

U<=

'101' true if b < a (signed)

false otherwise

<

'110' true if b > a (signed)

false otherwise

>

'111' true if b <= a (signed)

false otherwise

<=

ALU3Comparators

a(n-1:0)y(n-1:0)

sel(2:0)

n-line

ALU3

b(n-1:0)

56

library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all;use IEEE.std_logic_unsigned.all;

entity alu3 is generic(width:positive); port ( a: in STD_LOGIC_VECTOR(width-1 downto 0);

b: in STD_LOGIC_VECTOR(width-1 downto 0); sel: in STD_LOGIC_VECTOR(2 downto 0); y: out STD_LOGIC_VECTOR(width-1 downto 0) );end alu3;

alu3.vhd

a(n-1:0)y(n-1:0)

sel(2:0)

n-line

ALU3

b(n-1:0)

57

architecture alu3_arch of alu3 isbegin alu_3: process(a, b, sel) variable true, false: STD_LOGIC_VECTOR (width-1 downto 0); variable avs, bvs: signed(width-1 downto 0); begin for i in 0 to width-1 loop

true(i) := '1'; -- true is all ones;false(i) := '0'; -- false is all zerosavs(i) := a(i);bvs(i) := b(i);

end loop;

case sel is when "000" => -- = if (a = b) then


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when "001" => -- <> if (a /= b) then


when "010" => -- U< if (b < a) then


when "011" => -- U> if (b > a) then


when "100" => -- U<= if (b <= a) then

y <= true; else y <= false; end if; 59

when "101" => -- < if (bvs < avs) then


when "110" => -- > if (bvs > avs) then


when "111" => -- <= if (bvs <= avs) then

y <= true; else y <= false; end if; when others => null;

end case; end process alu_3;end alu3_arch;

60

ROM

85C4E65567D4F4C6

addr(2:0) M(7:0)

01234567

61


entity ROM is port ( addr: in STD_LOGIC_VECTOR (2 downto 0); M: out STD_LOGIC_VECTOR (7 downto 0) );end ROM;

85C4E65567D4F4C6

addr(2:0) M(7:0)

01234567

ROM.vhd

62

architecture ROM_arch of ROM isconstant data0: STD_LOGIC_VECTOR (7 downto 0) := "10000101";constant data1: STD_LOGIC_VECTOR (7 downto 0) := "11000100";constant data2: STD_LOGIC_VECTOR (7 downto 0) := X"E6";constant data3: STD_LOGIC_VECTOR (7 downto 0) := X"55";constant data4: STD_LOGIC_VECTOR (7 downto 0) := X"67";constant data5: STD_LOGIC_VECTOR (7 downto 0) := X"D4";constant data6: STD_LOGIC_VECTOR (7 downto 0) := "11110100";constant data7: STD_LOGIC_VECTOR (7 downto 0) := "11000110";

type rom_array is array (NATURAL range <>) of STD_LOGIC_VECTOR (7 downto 0);constant rom: rom_array := (

data0, data1, data2, data3,data4, data5, data6, data7);

begin process(addr) variable j: integer; begin j := conv_integer(addr); M <= rom(j); end process; end ROM_arch;

85C4E65567D4F4C6

addr(2:0) M(7:0)

01234567

63

architecture alu3_arch of alu3 isbegin alu_3: process(a, b, sel) variable true, false: STD_LOGIC_VECTOR (width-1 downto 0); variable avs, bvs: signed(width-1 downto 0); begin for i in 0 to width-1 loop

true(i) := '1'; -- true is all ones;false(i) := '0'; -- false is all zerosavs(i) := a(i);bvs(i) := b(i);

end loop;

case sel is when "000" => -- = if (a = b) then


64

Date post:	05-Feb-2016
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