VHDL Examples - Combinational Logic

7/17/2019 VHDL Examples - Combinational Logic

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VHDL Examples

Combinational Logic



Figure 6.27 VHDL code for a 2-to- multiplexer

L!"#$#% ieee &

'(E ieee.std)logic)6*.all &

E+,!,% mux2to !(

#, / 01 0 s 3 !+ (,D)L4!C &

f 3 ', (,D)L4!C 5 &

E+D mux2to &

$#CH!,EC,'#E "eaior F mux2to !(

"E4!+

8!,H s (ELEC,

f 9: 01 8HE+ ;1;

0 8HE+ ,HE#( &

E+D "eaior &

(a) Graphical symbol

f

s

w0

w1

0

1

(b) Truth table

0

1

f s

w0

w1

A 2-to-1 multiplexer – WITH-SELECT-WHEN statement



Figure 6.< $ 2-to- multiplexer using a conditional signal assignment

L!"#$#% ieee &


E+,!,% mux2to !(

#, /01 0 s 3 !+ (,D)L4!C &f 3 ', (,D)L4!C 5 &

E+D mux2to &

$#CH!,EC,'#E "eaior F mux2to !("E4!+

f 9: 01 8HE+ s : ;1; EL(E 0 &

E+D "eaior &


f

s

w0

w1

0

1

(b) Truth table

0

1

f s

w0

w1

A 2-to-1 multiplexer – WHEN-ELSE statement



Figure 6.<= $lternatie code for a 2-to- multiplexer

L!"#$#% ieee &


E+,!,% mux2to !(

#, / 01 0 s 3 !+ (,D)L4!C &

f 3 ', (,D)L4!C 5 &

E+D mux2to &

$#CH!,EC,'#E "eaior F mux2to !(

"E4!+

#CE(( / 01 0 s 5

"E4!+

f 9: 01 &

!F s : ;; ,HE+f 9: 0 &

E+D !F &

E+D #CE(( &

E+D "eaior &

A 2-to-1 multiplexer – IF statement


f

s

w0

w1

0

1

(b) Truth table

0

1

f s

w0

w1



Figure 6.*> $ C$(E statement tat represents a 2-to- multiplexer

L!"#$#% ieee &


E+,!,% mux2to !(

#, / 01 0 s 3 !+ (,D)L4!C &

f 3 ', (,D)L4!C 5 &

E+D mux2to &

$#CH!,EC,'#E "eaior F mux2to !("E4!+

#CE(( / 01 0 s 5

"E4!+

C$(E s !(

8HE+ ;1; :?

f 9: 01 &8HE+ ,HE#( :?

f 9: 0 &

E+D C$(E &

E+D #CE(( &

E+D "eaior &

A 2-to-1 multiplexer – CASE statement


f

s

w0

w1

0

1

(b) Truth table

0

1

f s

w0

w1



L!"#$#% ieee &


E+,!,% mux*to !(

#, / 01 0 02 0< 3 !+ (,D)L4!C &

s 3 !+ (,D)L4!C)VEC,#/ D8+, 15 &

f 3 ', (,D)L4!C 5 &

E+D mux*to &

$#CH!,EC,'#E "eaior F mux*to !(

"E4!+

8!,H s (ELEC,

f 9: 01 8HE+ @11@

0 8HE+ @1@02 8HE+ @1@

0< 8HE+ ,HE#( &

E+D "eaior &

Figure 6.2A VHDL code for a *-to- multiplexer

A 4-to-1 multiplexer

f

s1

w0

w1

00

01

(b) Truth table

w0

w1

s0

w2

w3

10

11

0

0

1

1

1

0

1

fs1

0

s0

w2

w3

(a) Graphic symbol



Figure 6.2A Component declaration for te *-to- multiplexer

L!"#$#% ieee &


$CB$4E mux*to)pacage !(

C+E+, mux*to#, / 01 0 02 0< 3 !+ (,D)L4!C &

s 3 !+ (,D)L4!C)VEC,#/ D8+, 15 &

f 3 ', (,D)L4!C 5 &

E+D C+E+, &

E+D mux*to)pacage &

f

s1

w0

w1

s0

w2

w3




Figure 6.* $ 6-to- multiplexer

w8

w11

s1

w0

s0

w3

w4

w7

w12

w15

s3

s2

f




Figure 6.2= Hierarcical code for a 6-to- multiplexer

L!"#$#% ieee &


L!"#$#% 0or &

'(E 0or.mux*to)pacage.all &

E+,!,% mux6to !(

#, / 0 3 !+ (,D)L4!C)VEC,#/1 , >5 &

s 3 !+ (,D)L4!C)VEC,#/< D8+, 15 &

f 3 ', (,D)L4!C 5 &

E+D mux6to &

$#CH!,EC,'#E (tructure F mux6to !(

(!4+$L m 3 (,D)L4!C)VEC,#/1 , <5 &

"E4!+

ux3 mux*to #, $ / 0/15 0/5 0/25 0/<5 s/ D8+, 15 m/15 5 &

ux23 mux*to #, $ / 0/*5 0/>5 0/65 0/75 s/ D8+, 15 m/5 5 &ux<3 mux*to #, $ / 0/A5 0/=5 0/15 0/5 s/ D8+, 15 m/25 5 &

ux*3 mux*to #, $ / 0/25 0/<5 0/*5 0/>5 s/ D8+, 15 m/<5 5 &

ux>3 mux*to #, $

/ m/15 m/5 m/25 m/<5 s/< D8+, 25 f 5 &

E+D (tructure &

A 16-to-1 multiplexer – Strutural mo!el



Figure 6.<6 Code for a 6-to- multiplexer using a generate statement

L!"#$#% ieee &


'(E 0or.mux*to)pacage.all &

E+,!,% mux6to !(

#, / 0 3 !+ (,D)L4!C)VEC,#/1 , >5 &

s 3 !+ (,D)L4!C)VEC,#/< D8+, 15 &

f 3 ', (,D)L4!C 5 &

E+D mux6to &

$#CH!,EC,'#E (tructure F mux6to !(

(!4+$L m 3 (,D)L4!C)VEC,#/1 , <5 &

"E4!+

43 F# i !+ 1 , < 4E+E#$,E

uxes3 mux*to #, $ /

0/*i5 0/*i5 0/*i25 0/*i<5 s/ D8+, 15 m/i5 5 &

E+D 4E+E#$,E &

ux>3 mux*to #, $ / m/15 m/5 m/25 m/<5 s/< D8+, 25 f 5 &

E+D (tructure &

A 16-to-1 multiplexer – "ENE#ATE Statement



Figure 6.<1 VHDL code for a 2-to-* binarG decoder

L!"#$#% ieee &


E+,!,% dec2to* !(

#, / 0 3 !+ (,D)L4!C)VEC,#/ D8+, 15 &

En 3 !+ (,D)L4!C &

G 3 ', (,D)L4!C)VEC,#/1 , <5 5 &

E+D dec2to* &

$#CH!,EC,'#E "eaior F dec2to* !(

(!4+$L En0 3 (,D)L4!C)VEC,#/2 D8+, 15 &

"E4!+

En0 9: En 0 &

8!,H En0 (ELEC,

G 9: @111@ 8HE+ @11@@111@ 8HE+ @1@

@111@ 8HE+ @1@

@111@ 8HE+ @@

@1111@ 8HE+ ,HE#( &

E+D "eaior &

A 2-to-4 $inar% !eo!er – WITH-SELECT-WHEN statement

0

0

1

1

1

0

1

y0w1

0

w0

x x

1

1

0

1

1

En

0

0

0

1

0

y1

1

0

0

0

0

y2

0

1

0

0

0

y3

0

0

1

0

0

w0

En

y0w1 y1

y2 y3

(a) Truth table

(b) Graphic symbol



Figure 6.*6 $ 2-to-* binarG decoder

L!"#$#% ieee &


E+,!,% dec2to* !(

#, / 0 3 !+ (,D)L4!C)VEC,#/ D8+, 15 &

En 3 !+ (,D)L4!C &G 3 ', (,D)L4!C)VEC,#/1 , <5 5 &

E+D dec2to* &

$#CH!,EC,'#E "eaior F dec2to* !(

"E4!+

#CE(( / 0 En 5"E4!+

!F En : ;; ,HE+

C$(E 0 !(

8HE+ @11@ :? G 9: @111@ &

8HE+ @1@ :? G 9: @111@ &

8HE+ @1@ :? G 9: @111@ &

8HE+ ,HE#( :? G 9: @111@ &E+D C$(E &

EL(E

G 9: @1111@ &

E+D !F &

E+D #CE(( &

E+D "eaior &

A 2-to-4 $inar% !eo!er – CASE statement



Figure 6.A $ *-to-6 decoder built using a decoder tree

w0

En

y0w1 y1

y2 y3

y8 y9 y10

y11

w2

w0 y0 y1 y2

y3

w0

En

y0w1 y1

y2

y3

w0

En

y0w1 y1

y2 y3

y4 y5 y6 y7

w1

w0

En

y0w1 y1

y2 y3

y12

y13

y14

y15

w0

En

y0

w1 y1 y2 y3

w3

En

A 4-to-16 $inar% !eo!er - Ciruit



Figure 6.<7 Hierarcical code for a *-to-6 binarG decoder

L!"#$#% ieee &


E+,!,% dec*to6 !(

#, / 0 3 !+ (,D)L4!C)VEC,#/< D8+, 15 &En 3 !+ (,D)L4!C &

G 3 ', (,D)L4!C)VEC,#/1 , >5 5 &

E+D dec*to6 &

$#CH!,EC,'#E (tructure F dec*to6 !(

C+E+, dec2to*

#, / 0 3 !+ (,D)L4!C)VEC,#/ D8+, 15 &

En 3 !+ (,D)L4!C &

G 3 ', (,D)L4!C)VEC,#/1 , <5 5 &

E+D C+E+, &

(!4+$L m 3 (,D)L4!C)VEC,#/1 , <5 &

"E4!+

43 F# i !+ 1 , < 4E+E#$,EDec)ri3 dec2to* #, $ / 0/ D8+, 15 m/i5 G/*i , *i<5 5&

423 !F i:< 4E+E#$,E

Dec)left3 dec2to* #, $ / 0/i D8+, i-5 En m 5 &

E+D 4E+E#$,E &

E+D 4E+E#$,E &

E+D (tructure &

A 4-to-16 $inar% !eo!er



Figure 6.<2 VHDL code for a prioritG encoder

L!"#$#% ieee &


E+,!,% prioritG !(

#, / 0 3 !+ (,D)L4!C)VEC,#/< D8+, 15 &

G 3 ', (,D)L4!C)VEC,#/ D8+, 15 &

I 3 ', (,D)L4!C 5 &

E+D prioritG &

$#CH!,EC,'#E "eaior F prioritG !(

"E4!+

G 9: @@ 8HE+ 0/<5 : ;; EL(E

@1@ 8HE+ 0/25 : ;; EL(E

@1@ 8HE+ 0/5 : ;; EL(E@11@ &

I 9: ;1; 8HE+ 0 : @1111@ EL(E ;; &

E+D "eaior &

A priorit% eno!er

d

0

01

0

10

w0 y 1

d

y 0

1 1

0

1

1

11

z

1

xx

0

x

w1

0

1x

0

x

w2

0

01

0

x

w3

0

00

0

1



Figure 6.<< Less efficient code for a prioritG encoder

L!"#$#% ieee &


E+,!,% prioritG !(

#, / 0 3 !+ (,D)L4!C)VEC,#/< D8+, 15 &G 3 ', (,D)L4!C)VEC,#/ D8+, 15 &

I 3 ', (,D)L4!C 5 &

E+D prioritG &


"E4!+

8!,H 0 (ELEC,G 9: @11@ 8HE+ @111@

@1@ 8HE+ @111@

@1@ 8HE+ @11@

@1@ 8HE+ @111@

@1@ 8HE+ @11@

@1@ 8HE+ @11@@1@ 8HE+ @1@

@@ 8HE+ ,HE#( &

8!,H 0 (ELEC,

I 9: ;1; 8HE+ @1111@

;; 8HE+ ,HE#( &

E+D "eaior &

A priorit% eno!er



Figure 6.*1 $ prioritG encoder specified using if-ten-else

L!"#$#% ieee &


E+,!,% prioritG !(

#, / 0 3 !+ (,D)L4!C)VEC,#/< D8+, 15 &

G 3 ', (,D)L4!C)VEC,#/ D8+, 15 &

I 3 ', (,D)L4!C 5 &

E+D prioritG &


"E4!+

#CE(( / 0 5"E4!+

!F 0/<5 : ;; ,HE+

G 9: @@ &

EL(!F 0/25 : ;; ,HE+

G 9: @1@ &

EL(!F 0/5 : ;; ,HE+

G 9: @1@ &EL(E

G 9: @11@ &

E+D !F &

E+D #CE(( &

I 9: ;1; 8HE+ 0 : @1111@ EL(E ;; &

E+D "eaior &

A priorit% eno!er – IF statement &1'



Figure 6.* $lternatie code for te prioritG encoder

L!"#$#% ieee &


E+,!,% prioritG !(#, / 0 3 !+ (,D)L4!C)VEC,#/< D8+, 15 &

G 3 ', (,D)L4!C)VEC,#/ D8+, 15 &

I 3 ', (,D)L4!C 5 &

E+D prioritG &


"E4!+

#CE(( / 0 5

"E4!+

G 9: @11@ &

!F 0/5 : ;; ,HE+ G 9: @1@ & E+D !F &

!F 0/25 : ;; ,HE+ G 9: @1@ & E+D !F &

!F 0/<5 : ;; ,HE+ G 9: @@ & E+D !F &

I 9: ;; &

!F 0 : @1111@ ,HE+ I 9: ;1; & E+D !F &

E+D #CE(( &

E+D "eaior &

A priorit% eno!er – IF statement &2'



Figure 6.<* VHDL code for a four-bit comparator

L!"#$#% ieee &


'(E ieee.std)logic)unsigned.all &

E+,!,% compare !(

#, / $ " 3 !+ (,D)L4!C)VEC,#/< D8+, 15 &

$eJ" $gt" $lt" 3 ', (,D)L4!C 5 &

E+D compare &

$#CH!,EC,'#E "eaior F compare !(

"E4!+

$eJ" 9: ;; 8HE+ $ : " EL(E ;1; &

$gt" 9: ;; 8HE+ $ ? " EL(E ;1; &

$lt" 9: ;; 8HE+ $ 9 " EL(E ;1; &

E+D "eaior &

A (our-$it omparator



Figure 6.<> $ four-bit comparator using si)ne! num$ers

L!"#$#% ieee &


'(E ieee.std)logic)arit.all &

E+,!,% compare !(

#, / $ " 3 !+ SI"NE*&+ *,WNT, 5 &

$eJ" $gt" $lt" 3 ', (,D)L4!C 5 &

E+D compare &

$#CH!,EC,'#E "eaior F compare !(

"E4!+

$eJ" 9: ;; 8HE+ $ : " EL(E ;1; &

$gt" 9: ;; 8HE+ $ ? " EL(E ;1; &

$lt" 9: ;; 8HE+ $ 9 " EL(E ;1; &

E+D "eaior &

A (our-$it omparator usin) si)ne! num$ers



,able 6. ,e functionalitG of te 7*<A $L'

T.e /4+01 AL



Figure 6.*A Code tat

represents te functionalitG

of te 7*<A $L'

L!"#$#% ieee &


'(E ieee.std)logic)unsigned.all &

E+,!,% alu !(

#, / s 3 !+ (,D)L4!C)VEC,#/2 D8+, 15 &

$ " 3 !+ (,D)L4!C)VEC,#/< D8+, 15 &F 3 ', (,D)L4!C)VEC,#/< D8+, 15 5 &

E+D alu &

$#CH!,EC,'#E "eaior F alu !(

"E4!+

#CE(( / s $ " 5

"E4!+C$(E s !(

8HE+ @111@ :? F 9: @1111@ &

8HE+ @11@ :? F 9: " - $ &

8HE+ @11@ :? F 9: $ - " &

8HE+ @1@ :? F 9: $ " &

8HE+ @11@ :? F 9: $ K# " &8HE+ @1@ :? F 9: $ # " &

8HE+ @1@ :? F 9: $ $+D " &

8HE+ ,HE#( :?

F 9: @@ &

E+D C$(E &

E+D #CE(( &

E+D "eaior &

T.e /4+01 AL



Figure 6.*= ,iming simulation for te 7*<A $L' code

T.e /4+01 AL

A C* t / t !i l ! t



Figure 6.2> $ "CD-to-7-segment displaG code conerter

ce

1

0

1

1

1

1

1

w0 a

1

b

0 1

1

1

1

0

1

1

0

1

0

0

w1

0

1

1

0

0

w2

0

0

0

0

1

w3

0

0

0

0

0

c

1

0

1

0

0

1

1

0

1

1

1

0

0

0

0

1

1001

1

11

1

01

1

0

1 1

1

1

1

1

1

0

1

1

1

d

0

1

0

0

1

0

e

1

0

1

1

1

0

1

0

0

1

0

0

0

1

f

1

0

0

1

1

1

g

1

0

1

1

1

1

1

1

0

1

(c) Truth table

(a) Code converter

w0

a

w1

b

c

d

w2w3

ef

g

a

g

bf

d

(b) 7-segment display

A C*-to-/-se)ment !ispla% o!e on3erter

A C* t / t ! !



Figure 6.*7 $ "CD-to-7-segment decoder

L!"#$#% ieee &


E+,!,% seg7 !(

#, / bcd 3 !+ (,D)L4!C)VEC,#/< D8+, 15 &

leds 3 ', (,D)L4!C)VEC,#/ , 75 5 &E+D seg7 &

$#CH!,EC,'#E "eaior F seg7 !(

"E4!+

#CE(( / bcd 5

"E4!+

C$(E bcd !( -- abcdefg

8HE+ @1111@ :? leds 9: @1@ &8HE+ @111@ :? leds 9: @11111@ &

8HE+ @111@ :? leds 9: @11@ &

8HE+ @11@ :? leds 9: @11@ &

8HE+ @111@ :? leds 9: @111@ &

8HE+ @11@ :? leds 9: @11@ &

8HE+ @11@ :? leds 9: @1@ &

8HE+ @1@ :? leds 9: @1111@ &

8HE+ @111@ :? leds 9: @@ &

8HE+ @11@ :? leds 9: @11@ &

8HE+ ,HE#( :? leds 9: @-------@ &

E+D C$(E &

E+D #CE(( &

E+D "eaior &

A C*-to-/-se)ment !eo!er



* "it #ipple CarrG $dder

$ "

(

CiCo

$ "

(

CiCo

$ "

(

CiCo

$ "

(

CiCo Cin

$/15

Cout

"/15$/5 "/5$/25 "/25$/<5 "/<5

C/15C/5C/25C/<5C/*5

(um/15(um/5(um/25(um/<5

8ant to 0rite a VHDL model for a * bit ripple carrG adder. Logic eJuation for eac full adder is3

sum 9: a xor b xor ci&

co 9: /a and b5 or /ci and /a or b55&

* i i l C d l



* "it #ipple CarrG odellibrarG ieee&

use ieee.std)logic)6*.all&

entitG adder*bit is

port / ab3 in std)logic)ector/< do0nto 15& cin 3 in std)logic&

cout3 out std)logic&

sum3 out std)logic)ector/< do0nto 15

5&

end adder*bit&

arcitecture bruteforce of adder*bit is

-- temporarG signals for internal carries signal c 3 std)logic)ector/* do0nto 15& .

begin

process /a b cin c5

begin

c/15 9: cin&

-- full adder 1 sum/15 9: a/15 xor b/15 xor c/15&

c/5 9: /a/15 and b/155 or /c/15 and /a/15 or b/1555&

-- full adder

sum/5 9: a/5 xor b/5 xor c/5&

c/25 9: /a/5 and b/55 or /c/5 and /a/5 or b/555&

-- full adder 2

sum/25 9: a/25 xor b/25 xor c/25&

c/<5 9: /a/25 and b/255 or /c/25 and/a/25 or b/2555&

-- full adder <

sum/<5 9: a/<5 xor b/<5 xor c/<5&

c/*5 9: /a/<5 and b/<55 or /c/<5 and

/a/<5 or b/<555&

cout 9: c/*5&

end process&end bruteforce&

(traigt for0ard

implementation. +oting

0rong 0it tis.Ho0eer is tere an

easier 0aG



4 it #ipple Carr% o!el usin) For Statement

arcitecture forloop of adder*bit is

signal c 3 std)logic)ector/* do0nto 15& -- temporarG signals for internal carries. begin

process /a b cin c5

begin

c/15 9: cin&

for i in 1 to < loop -- all four full adders

sum/i5 9: a/i5 xor b/i5 xor c/i5&

c/i5 9: /a/i5 and b/i55 or /c/i5 and /a/i5 or b/i555&

end loop&

cout 9: c/*5&

end process&

end forloop&

Date post:	08-Jan-2016
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VHDL Examples - Combinational Logic

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