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Vko,MDa, 27.9.1999 OH 1
TKK S-88.133 autumn1999
Digital design with Hardware Description Languages
Autumn 1999
Mikael Platan ([email protected])
Mark Davidson ([email protected])
Vesa Koskela ([email protected])
Autumn VHDL course for TKK
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Vko,MDa, 27.9.1999 OH 2
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VHDL = VHSIC Hardware Description Language
This course will cover two main topics:
1.) The VHDL language and it constraints.
2.) Why one would want to use the language in digital design.
However, other questions will be answered such as
Where does it fit on the world map of hardware design?
Why is it here?
Why ever use VHDL?
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VHDL
VHSIC Hardware Description Language
VHSIC = Very High Speed Integrated Circuit
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TKK S-88.133 autumn1999
Hardware Description Languages
There are many HDLs with different features and goals:
- VHDL: U.S. Department of Defense sponsored project (first standard 1987)Most wide spread in Europe
- VERILOG: Proprietary language first then opened to the public (late 80s)Most wide spread in the USA
- UDL/I: Unified Design Language for IC:s. Developed in Japan for commoninterchange format between CAD tools.
- SILAGE: Suited for DSP application.
VHDL and VERILOG are the most common!
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TKK S-88.133 autumn1999
VHDL History
- Originated from the US Government VHSIC program
A need was seen for a method in which to describe a digital circuit insuch a manner that it was free from any technical constraints. Thiswould allow the Department of Defense to replace an obsoletecomponent with a new one without large amounts of re-design work.
- Further developed by Institute of Electrical and Electronics Engineers(IEEE)
- Adopted as an IEEE STANDARD1076 in 1987 Hence VHDL-87!
- All IEEE standards are subject to a review every 5 years
This is where VHDL-93 comes from!
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Vko,MDa, 27.9.1999 OH 6
TKK S-88.133 autumn1999
VHDL - language
IEEE standard hardwaredescription language 1076-1987VHDL-87
Is based on the ADA language
VHDLs worst competitor isVERILOG
New VHDL version was approvedin 1993. VHDL-93
New VHDL version to beapproved early this year. Itcontains analog signal support.
For digital design/modeling Also aAHDL (Analog HDL) is beingdeveloped. This is due to thegrowing importance of mixedsignal systems.
Most important application is inASIC (Application SpecificIntegrated Circuit) design
It is used for modeling, simulation,logic synthesis and testing
Common method of modelingbetween designers and design tools
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Vko,MDa, 27.9.1999 OH 7
TKK S-88.133 autumn1999
VHDL features
Parallelisms. Different processescan be active independently ofeach other. This is fundamentallyan accurate model for a digitalsystem.
Supports hierarchical design, top-down or bottom-up.
Supports reuse through itslibrary/package functions wherefunctions and components can becollected
Strongly typed language. This issimilar to Pascal and otherSoftware programming languages.It means that operands must be ofthe correct type for a operator to becalled
Dynamic types and their use withe.g. attributes:
FOR i IN jrange LOOP ...
where the variable js range candynamically changed.
Overloading. E.g. the same
function can be called withdifferent types of parameters. Thisis related to typing. To use thesame function (operator) ondifferent types of objects (operand)one must define it multiply to becompatible with all the requiredtypes.
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TKK S-88.133 autumn1999
VHDL - world
Good overview from Internet:http://vhdl.org
FAQ, Frequently Asked Questions,in VHDL:http://vhdl.org/vi/comp.lang.vhdl/
VHDL International organizations
e.g. standardization Usenet news groups:
comp.lang.vhdl
Tutorials on the net, VHDLmodels, libraries, news etc
Many conferences. e.g. DAC
http://www.mkp.com
Documents: 1076-1987 StandardVHDL Language ReferenceManual, IEEE standard VHDL...(-93)
Numerous books: e.g. Perry -VHDL, Bhasker - A VHDLprimer
Numerous VHDL products, alsosome Public Domain.
The most known manufacturers:Synopsys, Mentor, Cadence,Summit, Renoir, TransEDA
Design, Lecturing, Consulting,
Subcontracting
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Vko,MDa, 27.9.1999 OH 9
TKK S-88.133 autumn1999
Modeling Digital Systems
Digital system = Any digital circuit that processes or storesinformation
These systems are complex: We need to recognize them as complexand have to find ways to deal with the complexity
The most important way is to adopt a systematic methodology ofdesign
The term MODEL will refer to our understanding of a system. Amodel should allow us to make predictions about the system.
There can be several models of one system!
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Why MODELs
1) Formal model to communicate requirements.
2) Communicate and enhance the understanding of the function of asystem
3) Models will allow testing and verification of a design usingsimulation. Thus allowing for the correction of errors before thesystem is manufactured.
4) Formal verification of the correctness of a design
5) To allow SYNTHESIS of circuits
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TKK S-88.133 autumn1999
Why use Hardware Description Language for modeling
To model the design
To verify the model
To implement the model in hardware (synthesizing)
Using a language to do this allows for more levels of abstraction.Giving the designer more freedom to implement ideas, rather thanspecifics, results in higher quality designs in a shorter time.
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TKK S-88.133 autumn1999
Remember!
The idea behind all of these arguments is that:
We want to achieve maximum reliability in the design process
for a
minimum cost and design time!!
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Domains and Levels of Modeling
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Functional
At the most abstract level the system may be described in terms of
ALGORITHMS
NOTE! This is often called BEHAVIOURAL MODELING
Example:
loopfor each data input loop
read the value on this input;
scale the value using the current scale factor for this input
convert and write....
end loop;wait for 10ms;
end loop;
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Structural
The system may be described as an interconnection of components likeprocessors, memories and i/o devices.
Sometimes called as the Processor Memory Switch, PMS, level.
Example:
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Geometric
Top level abstraction: How the components described in the structuralmodel are organized on the silicon die.
Pad frame
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Next level in abstraction: REGISTER TRANSFER LEVEL
Register Transfer Level: Structural model:
Example:
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Register Transfer Language (RTL)
In the functional domain a Register Transfer Language is used to specifythe operation of a system at the Register Transfer Level:
Example:
MAR
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Most designers work more and more away from the center
Tools help designers
work away from the
center
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TKK S-88.133 autumn1999
Why VHDL as modeling language?
Includes facilities to describe structure and function at VARIOUSlevels of abstraction (above gate level)
Has an attribute mechanism to annotate information from thegeometric domain.
It can be used for specification, simulation and hardware synthesis
It is widely supported by CAD tool vendors. It is a standard being continuously reviewed.
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TKK S-88.133 autumn1999
Graphical Entry tools - need anymore to learn VHDL?!
Today many Graphical Entry tools that automatically generate VHDLcode exist (Summit, Renoir)
They are becoming so good that they are already being used inproduction
The need for writing actual code may have been reduced due to GE
tools but:1) the need to understand what was auto generated is still there
2) we still have to manage large amounts of vhdl blocks
3) VHDL is still the descriptive part
4) Many of the GE tools are not producing correct or optimized code inall situations.
GE tools should be viewed as a complement not a replacement toVHDL.
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Vko,MDa, 27.9.1999 OH 22
TKK S-88.133 autumn1999
VHDL Modeling Concepts
We have discussed three domains of modeling:
1) Function
2) Structure
3) Geometry
We will now introduce VHDL elements to describe the basic modelingconcept in each of the above 3 domains.
NB: The objective is to GET A FEEL for VHDL as a descriptionlanguage - All these will be discussed in detail later.
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TKK S-88.133 autumn1999
Entity
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TKK S-88.133 autumn1999
Elements of Behavior
- Internal function of an entity is called ARCHITECTURE
- An architecture can have a number ofalternative functions
- A behavioral architecture of an entity consists ofProcess statements
- Process statements are a collection of actions executed in sequence(sequential statements)
Example:
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architecture behav of reg4 isbegin
storage : process isvariable stored_d0, stored_d1, stored_d2, stored_d3 : bit;
begin ifen = '1' and clk = '1' then
stored_d0 := d0;
stored_d1 := d1;stored_d2 := d2;stored_d3 := d3;
end if;q0
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Vko,MDa, 27.9.1999 OH 26
TKK S-88.133 autumn1999
Elements of Structure
An implementation of an entity can be viewed as being composed ofsubsystems
An architecture body that only has interconnected subsystems iscalled an structural architecture body
Example:
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Structural composition
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TKK S-88.133 autumn1999
Subsystem description
entity d_latch isport ( d, clk : in bit; q : out bit );
end d_latch;
architecture basic ofd_latch isbegin
latch_behavior : process is
beginif clk = '1' thenq
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Structural architecture
architecture struct ofreg4 is
signal int_clk : bit;
begin
bit0 : entity work.d_latch(basic)port map (d0, int_clk, q0);
bit1 : entity work.d_latch(basic)port map (d1, int_clk, q1);
bit2 : entity work.d_latch(basic)port map (d2, int_clk, q2);
bit3 : entity work.d_latch(basic)port map (d3, int_clk, q3);
gate : entity work.and2(basic)port map (en, clk, int_clk);
end architecture struct;
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TKK S-88.133 autumn1999
Mixed Models
In models it can be and is often useful to
mix structural and behavioral models
One of the strengths of VHDL is the amount of freedom it gives to thedesigner.
Good design is using the appropriate method of modeling.
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TKK S-88.133 autumn1999
Test benches
It is an entirely self-contained entity, with no port list, that stimulatesthe VHDL block under test.
The block under test is instantiated as a component in the test benchand structurally connected to the test bench.
Test benches will be covered more in detail in lecture #6.
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TKK S-88.133 autumn1999
Analysis, Elaboration and Execution
Analysis: The process of checking the syntax and semantics of thecode
Elaboration: Going through the design hierarchy and creating all of theobjects defined in the declarations.
Execution: The passage of time is simulated in discrete steps.
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Reserved Words in VHDL -93
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Extended Backus-Naur Format (EBNF)
For syntax description EBNF is used throughout the book.