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VHDLPractical Exam Guide
Contents
1. Multiplier 4*4
2. Multiplier 8*8
3. RAM 128*8
4. RAM 16*4
5. ROM 128*8
6. ROM 8*2
Contents
1. TLC
2. Sequence Detector
3. Vending Machine
4. EDL
5. Smart Door
6. Suez Canal
1 2
1. Multiplier 4*42. Multiplier 8*83. RAM 128*84. RAM 16*45. ROM 128*86. ROM 8*2
1
Contents
Multiplier
4 bit * 4 bit
C:\FPGAdv52\Libraries\S\src\@mult\@r@[email protected] 11/03/11 13:45:45
-- hds header_start---- VHDL Architecture S.Mult.RTL---- Created:-- by - Pharaoh.UNKNOWN (S)-- at - 13:07:36 11/03/2011---- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)---- hds header_endLIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all;
ENTITY Mult IS-- Declarations Port ( x,y : In STD_Logic_Vector ( 3 downto 0 ); z : Out STD_Logic_Vector (7 downto 0));END Mult ;
-- hds interface_endARCHITECTURE RTL OF Mult ISsignal pp1: unsigned (3 downto 0);signal pp2: unsigned (4 downto 0);signal pp3: unsigned (5 downto 0);signal pp4: unsigned (6 downto 0);signal ppp1: unsigned (5 downto 0);signal ppp2: unsigned (7 downto 0);signal pppp1: unsigned (7 downto 0);
BEGIN
pp1 <= unsigned (x) when y(0)='1' else (others => '0');pp2 <= unsigned (x&'0') when y(1)='1' else (others => '0');pp3 <= unsigned (x&"00") when y(2)='1' else (others => '0');pp4 <= unsigned (x&"000") when y(3)='1' else (others => '0');
ppp1 <= ("00"&pp1) + ('0'&pp2);ppp2 <= ("00"&pp3) + ('0'&pp4);
pppp1 <= ("00"&ppp1) + ppp2;
z <= STD_Logic_Vector(pppp1);
END RTL;
Page: 1
Mult 4.4 Simulation Codeforce -freeze sim:/mult/x 1111 0force -freeze sim:/mult/y 1010 0add wave sim:/mult/*runrunrunrunrun
Page 1
15
10
150
0000
11110
000000
1111000
011110
01111000
10010110
0 100 200 300 400 500 600 700 800 900 1 us
/mult/x 15
/mult/y 10
/mult/z 150
/mult/pp1 0000
/mult/pp2 11110
/mult/pp3 000000
/mult/pp4 1111000
/mult/ppp1 011110
/mult/ppp2 01111000
/mult/pppp1 10010110
Entity:mult Architecture:rtl Date: Fri Dec 30 13:45:41 HDS 2011 Row: 1 Page: 1
Multiplier
8 bit * 8 bit
C:\FPGAdv52\Libraries\S\src\@mult_8\@r@[email protected] 12/30/11 13:55:20
-- hds header_start---- VHDL Architecture S.Mult_8.RTL---- Created:-- by - Pharaoh.UNKNOWN (S)-- at - 14:09:52 11/16/2011---- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)---- hds header_endLIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all;
ENTITY Mult_8 IS-- Declarations PORT ( x,y : IN STD_Logic_Vector (7 Downto 0); z : OUT STD_Logic_Vector (15 Downto 0));END Mult_8 ;
-- hds interface_endARCHITECTURE RTL OF Mult_8 ISSignal p1: unsigned (7 Downto 0);Signal p2: unsigned (8 Downto 0);Signal p3: unsigned (9 Downto 0);Signal p4: unsigned (10 Downto 0);Signal p5: unsigned (11 Downto 0);Signal p6: unsigned (12 Downto 0);Signal p7: unsigned (13 Downto 0);Signal p8: unsigned (14 Downto 0);
Signal pp1: unsigned (9 Downto 0);Signal pp2: unsigned (11 Downto 0);Signal pp3: unsigned (13 Downto 0);Signal pp4: unsigned (15 Downto 0);
Signal ppp1: unsigned (11 Downto 0);Signal ppp2: unsigned (15 Downto 0);
Signal pppp1: unsigned (15 Downto 0);
BEGIN
p1 <= unsigned (x) when y(0) = '1' else (others => '0');p2 <= unsigned ( x & '0') when y(1) = '1' else (others => '0');p3 <= unsigned ( x & "00") when y(2) = '1' else (others => '0');p4 <= unsigned ( x & "000") when y(3) = '1' else (others => '0');p5 <= unsigned ( x & "0000") when y(4) = '1' else (others => '0');p6 <= unsigned ( x & "00000") when y(5) = '1' else (others => '0');p7 <= unsigned ( x & "000000") when y(6) = '1' else (others => '0');p8 <= unsigned ( x & "0000000") when y(7) = '1' else (others => '0');
pp1 <= ("00" & p1) + ('0' & p2);pp2 <= ("00" & p3) + ('0' & p4);pp3 <= ("00" & p5) + ('0' & p6);pp4 <= ("00" & p7) + ('0' & p8);
ppp1 <= ("00" & pp1) + pp2;ppp2 <= ("00" & pp3) + pp4;
pppp1 <= ("0000" & ppp1) + ppp2;
z <= STD_Logic_Vector(pppp1);
END RTL;
Page: 1
Mult 8.8 Simulation Codeforce -freeze sim:/mult_8/x 01100100 0force -freeze sim:/mult_8/y 00001100 0add wave sim:/mult_8/*runrunrunrunrunrun
Page 1
100
12
1200
00000000
000000000
0110010000
01100100000
000000000000
0000000000000
00000000000000
000000000000000
0000000000
010010110000
00000000000000
0000000000000000
010010110000
0000000000000000
0000010010110000
0 500 1 us 1500 2 us
/mult_8/x 100
/mult_8/y 12
/mult_8/z 1200
/mult_8/p1 00000000
/mult_8/p2 000000000
/mult_8/p3 0110010000
/mult_8/p4 01100100000
/mult_8/p5 000000000000
/mult_8/p6 0000000000000
/mult_8/p7 00000000000000
/mult_8/p8 000000000000000
/mult_8/pp1 0000000000
/mult_8/pp2 010010110000
/mult_8/pp3 00000000000000
/mult_8/pp4 0000000000000000
/mult_8/ppp1 010010110000
/mult_8/ppp2 0000000000000000
/mult_8/pppp1 0000010010110000
Entity:mult_8 Architecture:rtl Date: Fri Dec 30 13:56:15 HDS 2011 Row: 1 Page: 1
RAM
128 * 8
1024 bit
128 Byte
C:\FPGAdv52\Libraries\S\src\@r@a@m_128_8\rtl.vhd 12/30/11 12:10:54
-- hds header_start---- VHDL Architecture S.RAM_128_8.rtl---- Created:-- by - Pharaoh.UNKNOWN (S)-- at - 11:42:32 12/30/2011---- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)---- hds header_endLIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all;
ENTITY RAM_128_8 IS-- Declarations PORT (din: IN STD_Logic_Vector (7 downto 0); dout: OUT STD_Logic_Vector (7 downto 0); addr: IN STD_Logic_Vector ( 6 downto 0); wr,clk: IN STD_Logic);END RAM_128_8 ;
-- hds interface_endARCHITECTURE rtl OF RAM_128_8 IS
type mem_type is array (0 to 127) of STD_Logic_vector (7 downto 0);signal mem: mem_type;BEGIN Process (clk) begin if(rising_edge(clk)) then if(wr='1') then mem(conv_integer(unsigned(addr))) <= din; end if; end if; End Process; dout <= mem(conv_integer(unsigned(addr)));END rtl;
Page: 1
RAM 128.8 Simulation Codeforce -freeze sim:/ram_128_8/clk 1 0, 0 {50 ns} -r 100
force -freeze sim:/ram_128_8/wr 1 0force -freeze sim:/ram_128_8/addr 0000000 0force -freeze sim:/ram_128_8/din 00000000 0
force -freeze sim:/ram_128_8/addr 0000000 100force -freeze sim:/ram_128_8/addr 0000001 200force -freeze sim:/ram_128_8/addr 0000010 300force -freeze sim:/ram_128_8/addr 0000011 400force -freeze sim:/ram_128_8/addr 0000100 500force -freeze sim:/ram_128_8/addr 0000101 600force -freeze sim:/ram_128_8/addr 0000110 700force -freeze sim:/ram_128_8/addr 0000111 800force -freeze sim:/ram_128_8/addr 0001000 900force -freeze sim:/ram_128_8/addr 0001001 1000
force -freeze sim:/ram_128_8/din 01100100 100force -freeze sim:/ram_128_8/din 01100101 200force -freeze sim:/ram_128_8/din 01100110 300force -freeze sim:/ram_128_8/din 01100111 400force -freeze sim:/ram_128_8/din 01101000 500force -freeze sim:/ram_128_8/din 01101001 600force -freeze sim:/ram_128_8/din 01101010 700force -freeze sim:/ram_128_8/din 01101011 800force -freeze sim:/ram_128_8/din 01101100 900force -freeze sim:/ram_128_8/din 01101101 1000
force -freeze sim:/ram_128_8/wr 0 1100
force -freeze sim:/ram_128_8/addr 0000000 1200force -freeze sim:/ram_128_8/addr 0000001 1300force -freeze sim:/ram_128_8/addr 0000010 1400force -freeze sim:/ram_128_8/addr 0000011 1500force -freeze sim:/ram_128_8/addr 0000100 1600force -freeze sim:/ram_128_8/addr 0000101 1700force -freeze sim:/ram_128_8/addr 0000110 1800
Page 1
RAM 128.8 Simulation Codeforce -freeze sim:/ram_128_8/addr 0000111 1900force -freeze sim:/ram_128_8/addr 0001000 2000force -freeze sim:/ram_128_8/addr 0001001 2100
add wave sim:/ram_128_8/*runrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrun
Page 2
0 100 101 102 103 104 105 106 107 108 109
X 100 101 102 103 104 105 106 107 108 109 100 101 102 103 104 105 106 107 108 109
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9
0 500 1 us 1500 2 us
/ram_128_8/din 0 100 101 102 103 104 105 106 107 108 109
/ram_128_8/dout X 100 101 102 103 104 105 106 107 108 109 100 101 102 103 104 105 106 107 108 109
/ram_128_8/addr 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9
/ram_128_8/wr
/ram_128_8/clk
/ram_128_8/mem
Entity:ram_128_8 Architecture:rtl Date: Fri Dec 30 12:17:46 HDS 2011 Row: 1 Page: 1
RAM
16 * 4
64 bit
8 Byte
C:\FPGAdv52\Libraries\S\src\@r@a@m_16_4\@r@[email protected] 12/30/11 12:19:28
-- hds header_start---- VHDL Architecture S.RAM_16_4.RTL---- Created:-- by - Pharaoh.UNKNOWN (S)-- at - 17:25:54 11/16/2011---- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)---- hds header_endLIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all;
ENTITY RAM_16_4 IS-- DeclarationsPORT (addr,din: IN STD_Logic_Vector (3 downto 0); dout: OUT STD_Logic_Vector (3 downto 0); wr,clk: IN STD_Logic);END RAM_16_4 ;
-- hds interface_endARCHITECTURE RTL OF RAM_16_4 IStype mem_type is array (0 to 15) of STD_Logic_vector (3 downto 0);signal mem: mem_type;BEGIN Process (clk) begin if(rising_edge(clk)) then if(wr='1') then mem(conv_integer(unsigned(addr))) <= din; end if; end if; End Process; dout <= mem(conv_integer(unsigned(addr)));END RTL;
Page: 1
RAM 16.4 Simulation Codeforce -freeze sim:/ram_16_4/clk 1 0, 0 {50 ns} -r 100
force -freeze sim:/ram_16_4/wr 1 0
force -freeze sim:/ram_16_4/addr 0000 0force -freeze sim:/ram_16_4/din 0000 0
force -freeze sim:/ram_16_4/addr 0000 100force -freeze sim:/ram_16_4/addr 0001 200force -freeze sim:/ram_16_4/addr 0010 300force -freeze sim:/ram_16_4/addr 0011 400force -freeze sim:/ram_16_4/addr 0100 500force -freeze sim:/ram_16_4/addr 0101 600force -freeze sim:/ram_16_4/addr 0110 700force -freeze sim:/ram_16_4/addr 0111 800force -freeze sim:/ram_16_4/addr 1000 900force -freeze sim:/ram_16_4/addr 1001 1000force -freeze sim:/ram_16_4/addr 1010 1100force -freeze sim:/ram_16_4/addr 1011 1200force -freeze sim:/ram_16_4/addr 1100 1300force -freeze sim:/ram_16_4/addr 1101 1400force -freeze sim:/ram_16_4/addr 1110 1500force -freeze sim:/ram_16_4/addr 1111 1600
force -freeze sim:/ram_16_4/din 1111 100force -freeze sim:/ram_16_4/din 1110 200force -freeze sim:/ram_16_4/din 1101 300force -freeze sim:/ram_16_4/din 1100 400force -freeze sim:/ram_16_4/din 1011 500force -freeze sim:/ram_16_4/din 1010 600force -freeze sim:/ram_16_4/din 1001 700force -freeze sim:/ram_16_4/din 1000 800force -freeze sim:/ram_16_4/din 0111 900force -freeze sim:/ram_16_4/din 0110 1000force -freeze sim:/ram_16_4/din 0101 1100force -freeze sim:/ram_16_4/din 0100 1200force -freeze sim:/ram_16_4/din 0011 1300
Page 1
RAM 16.4 Simulation Codeforce -freeze sim:/ram_16_4/din 0010 1400force -freeze sim:/ram_16_4/din 0001 1500force -freeze sim:/ram_16_4/din 0000 1600
force -freeze sim:/ram_16_4/wr 0 1700
force -freeze sim:/ram_16_4/addr 0000 1800force -freeze sim:/ram_16_4/addr 0001 1900force -freeze sim:/ram_16_4/addr 0010 2000force -freeze sim:/ram_16_4/addr 0011 2100force -freeze sim:/ram_16_4/addr 0100 2200force -freeze sim:/ram_16_4/addr 0101 2300force -freeze sim:/ram_16_4/addr 0110 2400force -freeze sim:/ram_16_4/addr 0111 2500force -freeze sim:/ram_16_4/addr 1000 2600force -freeze sim:/ram_16_4/addr 1001 2700force -freeze sim:/ram_16_4/addr 1010 2800force -freeze sim:/ram_16_4/addr 1011 2900force -freeze sim:/ram_16_4/addr 1100 3000force -freeze sim:/ram_16_4/addr 1101 3100force -freeze sim:/ram_16_4/addr 1110 3200force -freeze sim:/ram_16_4/addr 1111 3300
add wave sim:/ram_16_4/*runrunrunrunrunrunrunrunrunrunrun
Page 2
RAM 16.4 Simulation Coderunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrun
Page 3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
X 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
{1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000}
0 500 1 us 1500 2 us 2500 3 us 3500 4 us 4500
/ram_16_4/addr 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
/ram_16_4/din 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
/ram_16_4/dout X 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
/ram_16_4/wr
/ram_16_4/clk
/ram_16_4/mem {1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000}
Entity:ram_16_4 Architecture:rtl Date: Fri Dec 30 13:27:44 HDS 2011 Row: 1 Page: 1
ROM
128 * 8
1024 bit
128 Byte
C:\FPGAdv52\Libraries\S\src\@r@o@m_128_8\@r@[email protected] 12/30/11 12:19:53
-- hds header_start---- VHDL Architecture S.ROM_128_8.RTL---- Created:-- by - Pharaoh.UNKNOWN (S)-- at - 16:39:55 11/16/2011---- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)---- hds header_endLIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all;
ENTITY ROM_128_8 IS-- DeclarationsPORT (addr: IN STD_Logic_Vector (6 downto 0); dout: OUT STD_Logic_Vector (7 downto 0); clk: IN STD_Logic);END ROM_128_8 ;
-- hds interface_endARCHITECTURE RTL OF ROM_128_8 IStype rom_type is array (0 to 127) of STD_Logic_Vector(7 downto 0);constant rom: rom_type:= ("00000001","00000010","00000011","00000100","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010","00000001","00000010","00000011","00000100");BEGINProcess (clk)Begin if (rising_edge(clk)) then dout <= rom(conv_integer(unsigned(addr))); end if;End Process;
END RTL;
Page: 1
ROM 128.8 Simulation Codeforce -freeze sim:/rom_128_8/clk 1 0, 0 {50 ns} -r 100force -freeze sim:/rom_128_8/addr 0000000 0force -freeze sim:/rom_128_8/addr 0000001 200force -freeze sim:/rom_128_8/addr 0000010 400force -freeze sim:/rom_128_8/addr 0000011 600force -freeze sim:/rom_128_8/addr 0000100 800force -freeze sim:/rom_128_8/addr 1111011 1000force -freeze sim:/rom_128_8/addr 1111100 1200force -freeze sim:/rom_128_8/addr 1111101 1400force -freeze sim:/rom_128_8/addr 1111110 1600force -freeze sim:/rom_128_8/addr 1111111 1800add wave sim:/rom_128_8/*runrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrun
Page 1
0000000 0000001 0000010 0000011 0000100 1111011 1111100 1111101 1111110 1111111
XXXXXXXX 00000001 00000010 00000011 00000100 10101010 00000001 00000010 00000011 00000100
0 500 1 us 1500 2 us
/rom_128_8/addr 0000000 0000001 0000010 0000011 0000100 1111011 1111100 1111101 1111110 1111111
/rom_128_8/dout XXXXXXXX 00000001 00000010 00000011 00000100 10101010 00000001 00000010 00000011 00000100
/rom_128_8/clk
Entity:rom_128_8 Architecture:rtl Date: Fri Dec 30 13:34:57 HDS 2011 Row: 1 Page: 1
ROM
8 * 2
16 bit
2 Byte
C:\FPGAdv52\Libraries\S\src\@r@o@m_8_2\rtl.vhd 12/30/11 13:38:58
-- hds header_start---- VHDL Architecture s.ROM_8_2.rtl---- Created:-- by - Pharaoh.UNKNOWN (S)-- at - 13:38:41 12/30/2011---- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)---- hds header_endLIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all;
ENTITY ROM_8_2 IS-- Declarations PORT (addr: IN STD_Logic_Vector (2 downto 0); dout: OUT STD_Logic_Vector (1 downto 0); clk: IN STD_Logic);END ROM_8_2 ;
-- hds interface_endARCHITECTURE rtl OF ROM_8_2 IStype rom_type is array (0 to 7) of STD_Logic_Vector(1 downto 0);constant rom: rom_type:= ("00","01","10","11","00","01","10","11");BEGINProcess (clk)Begin if (rising_edge(clk)) then dout <= rom(conv_integer(unsigned(addr))); End if;End Process;END rtl;
Page: 1
ROM 8.2 Simulatin Codeforce -freeze sim:/rom_8_2/clk 1 0, 0 {50 ns} -r 100force -freeze sim:/rom_8_2/addr 000 0force -freeze sim:/rom_8_2/addr 001 200force -freeze sim:/rom_8_2/addr 010 300force -freeze sim:/rom_8_2/addr 011 400force -freeze sim:/rom_8_2/addr 100 500force -freeze sim:/rom_8_2/addr 101 600force -freeze sim:/rom_8_2/addr 110 700force -freeze sim:/rom_8_2/addr 111 800add wave sim:/rom_8_2/*runrunrunrunrunrunrunrunrunrunrun
Page 1
000 001 010 011 100 101 110 111
UU 00 01 10 11 00 01 10 11
0 500 1 us 1500 2 us
/rom_8_2/addr 000 001 010 011 100 101 110 111
/rom_8_2/dout UU 00 01 10 11 00 01 10 11
/rom_8_2/clk
Entity:rom_8_2 Architecture:rtl Date: Fri Dec 30 13:41:54 HDS 2011 Row: 1 Page: 1
1. TLC
2. Sequence Detector
3. Vending Machine
4. EDL
5. Smart Door
6. Suez Canal
2
Contents
TLC
Edited:
Yellow
Title:
Path:
clk
rst
RedRed
Package List
LIBRARY ieee;
USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all;
DeclarationsPorts:
Diagram Signals:
Green : std_logicrst : std_logic
Start : std_logicclk : std_logic
SIGNAL finish_y : std_logicSIGNAL finish_r : std_logic
Red : std_logicYellow : std_logic
<enter project name here><company name> Project:
<enter diagram title here> <enter comments here>
S_TLC/TLC/struct
by Pharaoh on 16 Dec 2011
rst S_TLC
TLC_FSM
I2
Green
Start
clk
Yellow
Greenrst
finish_y
Start
clk
Yellow
S_TLC
Counter_2bit
I0
clk
en
q
rst
S_TLC
Counter_4bit
I1
clk
en
q
rst
finish_r
finish_r
Red
clk
rst
finish_y
S_TLC\TLC\struct
Page 1 of 1Printed by Pharaoh on 12/29/2011 at 05:12:47 PM
Green <= '1';Yellow <= '0';Red <= '0';
Green <= '0';Yellow <= '1';Red <= '0';
Signals StatusSIGNAL SCOPE DEFAULT RESET STATUS Green OUT '0' COMB Red OUT '0' COMB Yellow OUT '0' COMB
Package List
LIBRARY ieee;USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
Architecture DeclarationsGlobal Actions Concurrent Statements Process DeclarationsState Register Statements
<enter project name here><company name> Project:
<enter diagram title here>Title: <enter comments here>
by Pharaoh on 16 Dec 2011
Path: S_TLC/TLC_FSM/fsm
Edited:
s0
s1s2
Green <= '0';Yellow <= '0';Red <= '1';
Start = '1'
finish_y = '1'
finish_r = '1'
S_TLC\TLC_FSM\fsm ['machine0']
Page 1 of 1Printed by Pharaoh on 12/29/2011 at 05:13:23 PM
Simulationview signals# .signalsforce -freeze sim:/tlc/clk 1 0, 0 {50 ns} -r 100force -freeze sim:/tlc/rst 1 0force -freeze sim:/tlc/rst 0 200force -freeze sim:/tlc/start 0 0force -freeze sim:/tlc/start 1 300force -freeze sim:/tlc/start 0 400add wave sim:/tlc/*runrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrun
Page 1
Simulationrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrun
Page 2
Simulationrunrunrunrunrunrunrun
Page 3
0 1 us 2 us 3 us 4 us 5 us 6 us 7 us 8 us 9 us
/tlc/start
/tlc/clk
/tlc/rst
/tlc/green
/tlc/red
/tlc/yellow
/tlc/finish_r
/tlc/finish_y
/tlc/yellow_internal
/tlc/red_internal
Entity:tlc Architecture:struct Date: Fri Dec 16 20:17:15 HDS 2011 Row: 1 Page: 1
C:\FPGAdv52\Libraries\S_TLC\src\@counter_2bit\rtl.vhd 12/16/11 18:20:57
-- hds header_start---- VHDL Architecture S_TLC.Counter_2bit.rtl---- Created:-- by - Pharaoh.UNKNOWN (S)-- at - 18:12:46 12/16/2011---- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)---- hds header_endLIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all;
ENTITY Counter_2bit IS-- Declarations PORT (rst, en, clk: IN Std_Logic; q : OUT Std_Logic);END Counter_2bit ;
-- hds interface_endARCHITECTURE rtl OF Counter_2bit ISSignal count_sig: unsigned (1 downto 0);BEGINProcess(rst,clk)Beginif (rst ='1') then count_sig <= (Others => '0');elsif (rising_edge(clk)) thenif (en = '1') thencount_sig <= count_sig +1;end if;end if;end process;q <= count_sig(0) and count_sig(1);END rtl;
Page: 1
Simulation 2bitview signals# .signalsforce -freeze sim:/counter_2bit/rst 1 0force -freeze sim:/counter_2bit/rst 0 200force -freeze sim:/counter_2bit/en 0 0force -freeze sim:/counter_2bit/en 1 400force -freeze sim:/counter_2bit/clk 1 0, 0 {50 ns} -r 100add wave sim:/counter_2bit/*runrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrun
Page 1
00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10
0 500 1 us 1500 2 us
/counter_2bit/rst
/counter_2bit/en
/counter_2bit/clk
/counter_2bit/q
/counter_2bit/count_sig 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10
Entity:counter_2bit Architecture:rtl Date: Fri Dec 16 18:25:50 HDS 2011 Row: 1 Page: 1
C:\FPGAdv52\Libraries\S_TLC\src\@counter_4bit\rtl.vhd 12/16/11 18:28:19
-- hds header_start---- VHDL Architecture S_TLC.Counter_4bit.rtl---- Created:-- by - Pharaoh.UNKNOWN (S)-- at - 18:27:22 12/16/2011---- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)---- hds header_endLIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all;
ENTITY Counter_4bit IS-- Declarationsport(clk,en,rst:IN Std_Logic; q:OUT Std_Logic);END Counter_4bit ;
-- hds interface_endARCHITECTURE rtl OF Counter_4bit ISsignal count_sig:unsigned(3 downto 0);BEGINprocess(rst,clk)beginif(rst='1') thencount_sig<=(others=>'0');elsif(rising_edge(clk)) thenif (en='1') thencount_sig<=count_sig+1;end if;end if;end process;q<=count_sig(0) and count_sig(1) and count_sig(2) and count_sig(3);END rtl;
Page: 1
Simulation 4bitview signals# .signals# .signalsforce -freeze sim:/counter_4bit/rst 1 0force -freeze sim:/counter_4bit/rst 0 200force -freeze sim:/counter_4bit/en 0 0force -freeze sim:/counter_4bit/en 1 400force -freeze sim:/counter_4bit/clk 1 0, 0 {50 ns} -r 100add wave sim:/counter_4bit/*runrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrun
Page 1
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101
0 500 1 us 1500 2 us
/counter_4bit/clk
/counter_4bit/en
/counter_4bit/rst
/counter_4bit/q
/counter_4bit/count_sig 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101
Entity:counter_4bit Architecture:rtl Date: Fri Dec 16 18:30:05 HDS 2011 Row: 1 Page: 1
Sequence Detector
Non-Overlapping
<enter project name here>
Package List
LIBRARY ieee;USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
Declarations
Ports:
Diagram Signals:
<company name>
by Pharaoh on 17 Dec 2011
Project:
<enter diagram title here>Title:
Path:
<enter comments here>
<<-- more -->>
Edited:
Rst : std_logicdin : std_logicSeq_Ok : std_logic
Clk : std_logic
din
Rst
Clk
S_Sequence_Detector
Seq_Det_FSM_10010
I2
Seq_OkRst
din
Seq_Ok
Clk
S_Sequence_Detector\Seq_Det_10010\struct
Page 1 of 1Printed by Pharaoh on 12/19/2011 at 12:35:28 PM
din = '1'
Signals StatusSIGNAL SCOPE DEFAULT RESET STATUS Seq_Ok OUT '0' COMB
s4
din = '0'
2
Package List
LIBRARY ieee;
USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all;
Architecture DeclarationsGlobal Actions Concurrent Statements Process DeclarationsState Register Statements
<enter project name here><company name>
by Pharaoh on 17 Dec 2011
Project:
<enter diagram title here>Title:
Path:
<enter comments here>
<<-- more -->>
Edited:
s0
Seq_Ok <= '1'; s5 s1
s2
din = '1'
din = '0'din = '0'
din = '1'
1
din = '0'
1
din = '1'2
1
s3
1
din = '1'
2
din = '0'
2
S_Sequence_Detector\Seq_Det_FSM_10010\fsm ['machine0']
Page 1 of 1Printed by Pharaoh on 12/19/2011 at 12:35:56 PM
s0 s1 s2 s3 s4 s5 s1 s2 s3 s4 s5 s0 s1 s2 s1
s0 s1 s2 s3 s4 s5 s1 s2 s3 s4 s5 s0 s1 s2 s1
0 500 1 us 1500 2 us
/seq_det_fsm_10010/clk
/seq_det_fsm_10010/rst
/seq_det_fsm_10010/din
/seq_det_fsm_10010/seq_ok
/seq_det_fsm_10010/current_state s0 s1 s2 s3 s4 s5 s1 s2 s3 s4 s5 s0 s1 s2 s1
/seq_det_fsm_10010/next_state s0 s1 s2 s3 s4 s5 s1 s2 s3 s4 s5 s0 s1 s2 s1
Entity:seq_det_fsm_10010 Architecture:fsm Date: Mon Dec 19 12:49:10 HDS 2011 Row: 1 Page: 1
Sequence Detector
Overlapping
<enter project name here>
Package List
LIBRARY ieee;USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
Declarations
Ports:
Diagram Signals:
<company name>
by Pharaoh on 17 Dec 2011
Project:
<enter diagram title here>Title:
Path:
<enter comments here>
<<-- more -->>
Edited:
Seq_Ok : std_logic
Rst : std_logicClk : std_logic
din : std_logic
Clk
Rst
din
S_Sequence_Detector
Seq_Det_FSM_10010_O
I3
Seq_OkSeq_OkRst
Clk
din
S_Sequence_Detector\Seq_Det_10010_O\struct
Page 1 of 1Printed by Pharaoh on 12/19/2011 at 12:36:22 PM
din = '1'
1
Signals StatusSIGNAL SCOPE DEFAULT RESET STATUS Seq_Ok OUT '0' COMB
s4
s5
din = '0'
Package List
LIBRARY ieee;USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
Architecture DeclarationsGlobal Actions Concurrent Statements Process DeclarationsState Register Statements
<enter project name here><company name>
by Pharaoh on 17 Dec 2011
Project:
<enter diagram title here>Title:
Path:
<enter comments here>
<<-- more -->>
Edited:
s0
Seq_Ok <= '1';
2
s1
s2
din = '1'
1
din = '0'
din = '0'
1
din = '0'
din = '1'
din = '1'2
s3
1
din = '1'
2
din = '0'
2
S_Sequence_Detector\Seq_Det_FSM_10010_O\fsm ['machine0']
Page 1 of 1Printed by Pharaoh on 12/19/2011 at 12:36:39 PM
s0 s1 s2 s3 s4 s5 s1 s2 s3 s4 s5 s3 s4 s5 s1
s0 s1 s2 s3 s4 s5 s1 s2 s3 s4 s5 s3 s4 s5 s1
0 500 1 us 1500 2 us
/seq_det_fsm_10010_o/clk
/seq_det_fsm_10010_o/rst
/seq_det_fsm_10010_o/din
/seq_det_fsm_10010_o/seq_ok
/seq_det_fsm_10010_o/current_state s0 s1 s2 s3 s4 s5 s1 s2 s3 s4 s5 s3 s4 s5 s1
/seq_det_fsm_10010_o/next_state s0 s1 s2 s3 s4 s5 s1 s2 s3 s4 s5 s3 s4 s5 s1
Entity:seq_det_fsm_10010_o Architecture:fsm Date: Mon Dec 19 12:40:35 HDS 2011 Row: 1 Page: 1
Vending Machine
Return_Request
<enter project name here>
<enter comments here>
SIGNAL Clk : std_logicSIGNAL Dollar : std_logicSIGNAL Quarter_Dollar : std_logicSIGNAL Return_Request : std_logicSIGNAL Rst : std_logicSIGNAL Soda : std_logicSIGNAL Soda_Request : std_logicSIGNAL The_Return : std_logic
The_Return
Package List
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
DeclarationsPorts:Diagram Signals:
<company name>
by Pharaoh on 21 Dec 2011
Project:
<enter diagram title here>Title:
Path:
Edited:
S_VM/VM/struct
S_VM
VM_FSM
I0Dollar
Quarter_Dollar
Soda_Request
Clk
Rst
Soda
S_VM\VM\struct
Page 1 of 1Printed by Pharaoh on 12/21/2011 at 11:36:14 AM
Signals Status
SIGNAL SCOPE DEFAULT RESET STATUS Soda OUT '0' COMB The_Return OUT '0' COMB
Package List
LIBRARY ieee;
USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all;
Architecture DeclarationsGlobal Actions Concurrent Statements Process DeclarationsState Register Statements
<enter project name here><company name>
by Pharaoh on 21 Dec 2011
Project:
<enter diagram title here>Title:
Path:
<enter comments here>
S_VM/VM_FSM/fsm
Edited:
s0
s1
Quarter_Dollar = '1'
1
Quarter_Dollar = '1' s2
s5
s3
Quarter_Dollar = '1'
1
Quarter_Dollar = '1'
Soda_Request = '1'
2
Soda <= '1';
Dollar = '1'
s8
The_Return <= '1';
2
Return_Request = '1'
s4
Soda_Request = '1'
s7
Soda <= '0';
s6
Soda <= '1';
S_VM\VM_FSM\fsm ['machine0']
Page 1 of 1Printed by Pharaoh on 12/21/2011 at 11:41:17 AM
VM Simulation Code - 3 Quartersforce -freeze sim:/vm_fsm/clk 1 0, 0 {50 ns} -r 100force -freeze sim:/vm_fsm/rst 1 0force -freeze sim:/vm_fsm/rst 0 50force -freeze sim:/vm_fsm/dollar 0 0force -freeze sim:/vm_fsm/quarter_dollar 0 0force -freeze sim:/vm_fsm/soda_request 0 0force -freeze sim:/vm_fsm/return_request 0 0force -freeze sim:/vm_fsm/quarter_dollar 1 200force -freeze sim:/vm_fsm/quarter_dollar 0 500force -freeze sim:/vm_fsm/soda_request 1 1200add wave sim:/vm_fsm/*runrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrun
Page 1
s0 s1 s2 s3 s5 s0
s0 s1 s2 s3 s3 s5 s0
0 500 1 us 1500 2 us
/vm_fsm/clk
/vm_fsm/rst
/vm_fsm/dollar
/vm_fsm/quarter_dollar
/vm_fsm/return_request
/vm_fsm/soda_request
/vm_fsm/soda
/vm_fsm/the_return
/vm_fsm/current_state s0 s1 s2 s3 s5 s0
/vm_fsm/next_state s0 s1 s2 s3 s3 s5 s0
Entity:vm_fsm Architecture:fsm Date: Wed Dec 21 12:09:48 HDS 2011 Row: 1 Page: 1
VM Simulation Code - 4 Quartersforce -freeze sim:/vm_fsm/clk 1 0, 0 {50 ns} -r 100force -freeze sim:/vm_fsm/rst 1 0force -freeze sim:/vm_fsm/rst 0 50force -freeze sim:/vm_fsm/dollar 0 0force -freeze sim:/vm_fsm/quarter_dollar 0 0force -freeze sim:/vm_fsm/soda_request 0 0force -freeze sim:/vm_fsm/return_request 0 0force -freeze sim:/vm_fsm/quarter_dollar 1 200force -freeze sim:/vm_fsm/quarter_dollar 0 600force -freeze sim:/vm_fsm/soda_request 1 1200force -freeze sim:/vm_fsm/return_request 1 2000add wave sim:/vm_fsm/*runrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrun
Page 1
s0 s1 s2 s3 s4 s6 s7 s8 s0
s0 s1 s2 s3 s4 s4 s6 s7 s8 s0
0 500 1 us 1500 2 us
/vm_fsm/clk
/vm_fsm/rst
/vm_fsm/dollar
/vm_fsm/quarter_dollar
/vm_fsm/return_request
/vm_fsm/soda_request
/vm_fsm/soda
/vm_fsm/the_return
/vm_fsm/current_state s0 s1 s2 s3 s4 s6 s7 s8 s0
/vm_fsm/next_state s0 s1 s2 s3 s4 s4 s6 s7 s8 s0
Entity:vm_fsm Architecture:fsm Date: Wed Dec 21 11:52:56 HDS 2011 Row: 1 Page: 1
VM Simulation Code - Dollarforce -freeze sim:/vm_fsm/clk 1 0, 0 {50 ns} -r 100force -freeze sim:/vm_fsm/rst 1 0force -freeze sim:/vm_fsm/rst 0 50force -freeze sim:/vm_fsm/dollar 0 0force -freeze sim:/vm_fsm/quarter_dollar 0 0force -freeze sim:/vm_fsm/soda_request 0 0force -freeze sim:/vm_fsm/return_request 0 0force -freeze sim:/vm_fsm/dollar 1 200force -freeze sim:/vm_fsm/dollar 0 300force -freeze sim:/vm_fsm/soda_request 1 800force -freeze sim:/vm_fsm/return_request 1 1600add wave sim:/vm_fsm/*runrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrun
Page 1
s0 s4 s6 s7 s8 s0
s0 s4 s4 s6 s7 s8 s0
0 500 1 us 1500 2 us
/vm_fsm/clk
/vm_fsm/rst
/vm_fsm/dollar
/vm_fsm/quarter_dollar
/vm_fsm/return_request
/vm_fsm/soda_request
/vm_fsm/soda
/vm_fsm/the_return
/vm_fsm/current_state s0 s4 s6 s7 s8 s0
/vm_fsm/next_state s0 s4 s4 s6 s7 s8 s0
Entity:vm_fsm Architecture:fsm Date: Wed Dec 21 12:03:18 HDS 2011 Row: 1 Page: 1
Electronic Door Lock
No Interrupt
Declarations
Diagram Signals:
SIGNAL Key : std_logic_vector(3 DOWNTO 0)
SIGNAL Rst : std_logic
SIGNAL Clk : std_logic
SIGNAL Open_Door : std_logic
SIGNAL Click : std_logic
Package List
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
Ports:
<company name>
by Pharaoh on 24 Dec 2011
<enter diagram title here>Title:
Path: Exp/EDL/struct
Edited:
<enter project name here>Project:
<enter comments here>
Exp
EDL_FSM
I0
Clk
Rst
Key : (3:0)
Open_Door
Click
Exp\EDL\struct
Page 1 of 1Printed by Pharaoh on 12/31/2011 at 04:06:55 PM
Signals Status
SIGNAL SCOPE DEFAULT RESET STATUS Click OUT '0' COMB Open_Door OUT '0' COMB
Package List
LIBRARY ieee;
USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all;
Architecture DeclarationsGlobal Actions Concurrent Statements Process DeclarationsState Register Statements
<enter project name here><company name> Project:
<enter diagram title here>Title: <enter comments here>
s0
by Pharaoh on 29 Dec 2011
Path: Exp/EDL_FSM/fsm
Edited:
s1
Click <= '1';
s5
Click <= '1';
Key = "0011"
1
Key = "1010"
1
2
2
Click <= '1';
s2
Click <= '1';
s3
s6
Click <= '1';
s7
Key = "0101"
1
2
Click <= '1';
s4
Open_Door <= '1';
Click <= '1';
Key = "1011"
Exp\EDL_FSM\fsm ['machine0']
Page 1 of 1Printed by Pharaoh on 12/29/2011 at 05:35:08 PM
0011 1010 0101 1011
s0 s1 s2 s3 s4 s0 s5 s6 s7 s0 s5 s6 s7 s0 s5 s6 s7 s0
s1 s2 s3 s4 s0 s5 s6 s7 s0 s5 s6 s7 s0 s5 s6 s7 s0 s5
0 500 1 us 1500 2 us
/edl_fsm/clk
/edl_fsm/key 0011 1010 0101 1011
/edl_fsm/rst
/edl_fsm/click
/edl_fsm/open_door
/edl_fsm/current_state s0 s1 s2 s3 s4 s0 s5 s6 s7 s0 s5 s6 s7 s0 s5 s6 s7 s0
/edl_fsm/next_state s1 s2 s3 s4 s0 s5 s6 s7 s0 s5 s6 s7 s0 s5 s6 s7 s0 s5
Entity:edl_fsm Architecture:fsm Date: Thu Dec 29 17:30:47 HDS 2011 Row: 1 Page: 1
Simulation Codeforce -freeze sim:/edl_fsm/clk 1 0, 0 {50 ns} -r 100force -freeze sim:/edl_fsm/rst 1 0force -freeze sim:/edl_fsm/rst 0 50force -freeze sim:/edl_fsm/key 0011 0force -freeze sim:/edl_fsm/key 1010 100force -freeze sim:/edl_fsm/key 0101 200force -freeze sim:/edl_fsm/key 1011 300add wave sim:/edl_fsm/*runrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrun
Page 1
Electronic Door Lock
With Interrupt
Key : std_logic_vector(3 DOWNTO 0)
Rst
Key(3:0)
DeclarationsPorts:
Diagram Signals:
EDL_FSM
Package List
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
<company name>
by Pharaoh on 24 Dec 2011
<enter diagram title here>Title:
Path: S_EDL/EDL/struct
Edited:
<enter project name here>Project:
<enter comments here>
Rst : std_logic
Clk : std_logic
door_open : std_logicrdy_bsy : std_logic
intr : std_logic
S_EDL
I0
intr
Clk
intr
Key : (3:0)
Clk
Rst
door_open
rdy_bsy
door_open
rdy_bsy
S_EDL\EDL\struct
Page 1 of 1Printed by Pharaoh on 12/29/2011 at 05:03:50 PM
door_open <= '0';rdy_bsy <= '0';
Signals Status
SIGNAL SCOPE DEFAULT RESET STATUS door_open OUT '0' COMB rdy_bsy OUT '0' COMB
Path: S_EDL/EDL_FSM/fsm
Package List
LIBRARY ieee;
USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all;
Architecture DeclarationsGlobal Actions Concurrent Statements Process DeclarationsState Register Statements
<enter project name here><company name> Project:
<enter diagram title here>Title: <enter comments here>
s0
by Pharaoh on 24 Dec 2011Edited:
s1
door_open <= '0';rdy_bsy <= '1';
s5door_open <= '0';
rdy_bsy <= '1';
intr = '1' AND Key = "1101"
1
1
intr = '1'
2
intr = '1'
intr = '1'
2
intr = '1'
intr = '1'
s2
door_open <= '0';rdy_bsy <= '1';
s3door_open <= '0';
rdy_bsy <= '1';
s6door_open <= '0';rdy_bsy <= '1';
s7door_open <= '0';
rdy_bsy <= '1';
intr = '1' AND Key = "0011"
intr = '1' AND Key = "0111"
1
intr = '1' AND Key = "1001"
1
intr = '1'
2intr = '1'
2
s4
door_open <= '1';rdy_bsy <= '1';
S_EDL\EDL_FSM\fsm ['machine0']
Page 1 of 1Printed by Pharaoh on 12/29/2011 at 05:04:16 PM
0000 1101 0011 0111 1001
s0 s1 s2 s3 s4 s0
s0 s1 s1 s2 s2 s3 s3 s4 s0
0 500 1 us 1500 2 us
/edl_fsm/clk
/edl_fsm/rst
/edl_fsm/key 0000 1101 0011 0111 1001
/edl_fsm/intr
/edl_fsm/door_open
/edl_fsm/rdy_bsy
/edl_fsm/current_state s0 s1 s2 s3 s4 s0
/edl_fsm/next_state s0 s1 s1 s2 s2 s3 s3 s4 s0
Entity:edl_fsm Architecture:fsm Date: Thu Dec 29 17:42:03 HDS 2011 Row: 1 Page: 1
Simulation Codeforce -freeze sim:/edl_fsm/clk 1 0, 0 {50 ns} -r 100force -freeze sim:/edl_fsm/rst 1 0force -freeze sim:/edl_fsm/rst 0 50force -freeze sim:/edl_fsm/key 0000 0force -freeze sim:/edl_fsm/intr 0 0force -freeze sim:/edl_fsm/intr 1 200force -freeze sim:/edl_fsm/intr 1 500force -freeze sim:/edl_fsm/intr 1 800force -freeze sim:/edl_fsm/intr 1 1100force -freeze sim:/edl_fsm/intr 0 300force -freeze sim:/edl_fsm/intr 0 600force -freeze sim:/edl_fsm/intr 0 900force -freeze sim:/edl_fsm/intr 0 1200force -freeze sim:/edl_fsm/key 1101 200force -freeze sim:/edl_fsm/key 0011 500force -freeze sim:/edl_fsm/key 0111 800force -freeze sim:/edl_fsm/key 1001 1100add wave sim:/edl_fsm/*runrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrun
Page 1
Simulation Coderunrunrunrun
Page 2
Smart Door
Sensor_1
<enter project name here>
<enter comments here>
SIGNAL Clk : std_logicSIGNAL Open_Door : std_logicSIGNAL Rst : std_logicSIGNAL Sensor_1 : std_logicSIGNAL Sensor_2 : std_logicSIGNAL close : std_logicSIGNAL en : std_logic
Package List
LIBRARY ieee;
USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all;
DeclarationsPorts:Diagram Signals:
<company name>
by Pharaoh on 21 Dec 2011
Project:
<enter diagram title here>Title:
Path: S_SD/SD/struct
Edited:
Clk
Rst
Open_Door
S_SD
Counter_20sec
I1
clk
rst
close
en
S_SD
SD_FSM
I0 enClk
Rst
Sensor_2
close
S_SD\SD\struct
Page 1 of 1Printed by Pharaoh on 12/21/2011 at 02:59:21 PM
<enter project name here>
State Register Statements
SIGNAL SCOPE DEFAULT RESET STATUS
Open_Door OUT '0' COMB en OUT '0' COMB
Package List
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
Architecture Declarations
Concurrent StatementsGlobal Actions
Process Declarations
Signals Status
<company name>
by Pharaoh on 21 Dec 2011
Project:
Title:
Path:
<enter comments here>
S_SD/SD_FSM/fsm
Edited:
Smart Door
s0
Sensor_1 = '1' OR Sensor_2 = '1'
2
s1
Open_Door <= '1';
en <= '1';
s2
en <= '0';
Sensor_1 = '1' OR Sensor_2 = '1' 1
close = '1'
S_SD\SD_FSM\fsm ['machine0']
Page 1 of 1Printed by Pharaoh on 12/21/2011 at 03:05:29 PM
Smart Door - Simulation Codeadd wave sim:/sd/*force -freeze sim:/sd/clk 1 0, 0 {50 ns} -r 100force -freeze sim:/sd/rst 1 0force -freeze sim:/sd/rst 0 50force -freeze sim:/sd/sensor_2 0 0force -freeze sim:/sd/sensor_1 0 0force -freeze sim:/sd/sensor_1 1 900force -freeze sim:/sd/sensor_1 0 1000force -freeze sim:/sd/sensor_2 1 3900force -freeze sim:/sd/sensor_2 0 4000force -freeze sim:/sd/sensor_2 1 6900force -freeze sim:/sd/sensor_2 0 7000
runrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrun
Page 1
Smart Door - Simulation Coderunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrun
Page 2
Smart Door - Simulation Coderunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrun
Page 3
C:\FPGAdv52\Libraries\S_SD\src\@counter_20sec\rtl.vhd 12/21/11 14:58:23
-- hds header_start---- VHDL Architecture S_SD.Counter_20sec.rtl---- Created:-- by - Pharaoh.UNKNOWN (S)-- at - 12:40:51 12/21/2011---- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)---- hds header_endLIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all;
ENTITY Counter_20sec IS-- Declarations port(rst,clk,en: in std_logic; close: out std_logic); END Counter_20sec ;
-- hds interface_endARCHITECTURE rtl OF Counter_20sec ISsignal count: unsigned(4 downto 0); BEGIN process(rst,clk) begin if(rst = '1')then count <= "00010"; close <= '0'; elsif (rising_edge(clk)) then if(en = '1') then if( count < 20 ) then count <= count + 1; close <= '0'; else count <= "00001"; close <= '1'; end if; end if; end if; end process; END rtl;
Page: 1
Suez Canal
Start_4
Clk
Rst
SIGNAL sensor_B : std_logic
<enter project name here>
DeclarationsPorts:Diagram Signals:
SIGNAL Start_8 : Std_Logic
Package List
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;SIGNAL Clk : Std_LogicSIGNAL Rst : Std_LogicSIGNAL Start_4 : Std_Logic
SIGNAL alarm : Std_LogicSIGNAL finish_4 : Std_LogicSIGNAL finish_8 : Std_LogicSIGNAL gate_closed : Std_LogicSIGNAL green : Std_LogicSIGNAL red : Std_LogicSIGNAL sensor_A : std_logic
SIGNAL sensor_C : std_logicSIGNAL yellow : Std_Logic
<company name>
by Pharaoh on 29 Dec 2011
Project:
<enter diagram title here>Title:
Path:
<enter comments here>
Basma/Suez/struct
Edited:
Basma
suez_fsm
I0
red
alarm
gate_closed
green
Start_8
yellow
Start_4
finish_8
finish_4
sensor_C
sensor_B
sensor_A
Rst
Clk
Basma
counter_3bits
I2
clk
en
q
rst
Basma
counter_2bits
I1
clk
enq
rst
Start_8
finish_4
Clk
Rst
finish_8
Basma\Suez\struct
Page 1 of 1Printed by Pharaoh on 12/29/2011 at 04:42:42 PM
gate_closed <= '1';
green <= '0';
yellow <= '0';
red <= '1';
green <= '1';
yellow <= '0';
red <= '0';
green <= '0';
yellow <= '1';
red <= '0';
Start_4 <= '1';
s5
finish_4 = '1'
Signals Status
SIGNAL SCOPE DEFAULT RESET STATUS Start_4 OUT '0' COMB Start_8 OUT '0' COMB alarm OUT '0' COMB
gate_closed OUT '0' COMB green OUT '0' COMB red OUT '0' COMB yellow OUT '0' COMB
by Pharaoh on 29 Dec 2011Edited:
sensor_A = '0' AND sensor_B = '0' AND sensor_C = '0'
Package List
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
Architecture DeclarationsGlobal Actions Concurrent Statements Process DeclarationsState Register Statements
<enter project name here><company name> Project:
<enter diagram title here>Title:
Path:
<enter comments here>
Basma/suez_fsm/fsm
s0 s1sensor_A = '1'
s2s3s4
alarm <= '1';
gate_closed <= '1';
green <= '0';
yellow <= '0';
red <= '1';
green <= '0';
yellow <= '0';
red <= '1';
finish_8 = '1'sensor_B = '1'
sensor_C = '1'
green <= '0';
yellow <= '0';
red <= '1';
Start_8 <= '1';
Basma\suez_fsm\fsm ['machine0']
Page 1 of 1Printed by Pharaoh on 12/29/2011 at 04:43:10 PM
Simulation Forcesforce -freeze sim:/suez/clk 1 0, 0 {50 ns} -r 100force -freeze sim:/suez/rst 1 0force -freeze sim:/suez/rst 0 50force -freeze sim:/suez/sensor_a 0 0force -freeze sim:/suez/sensor_b 0 0force -freeze sim:/suez/sensor_c 0 0force -freeze sim:/suez/sensor_a 1 200force -freeze sim:/suez/sensor_a 0 300force -freeze sim:/suez/sensor_b 1 1600force -freeze sim:/suez/sensor_b 0 1700force -freeze sim:/suez/sensor_c 1 4000force -freeze sim:/suez/sensor_c 0 4100add wave sim:/suez/*runrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrun
Page 1
Simulation Forcesrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrunrun
Page 2
0 500 1 us 1500 2 us 2500 3 us 3500 4 us 4500
/suez/clk
/suez/rst
/suez/green
/suez/yellow
/suez/red
/suez/sensor_a
/suez/sensor_b
/suez/sensor_c
/suez/start_4
/suez/finish_4
/suez/start_8
/suez/finish_8
/suez/gate_closed
/suez/alarm
Entity:suez Architecture:struct Date: Thu Dec 29 16:44:34 HDS 2011 Row: 1 Page: 1
C:\FPGAdv52\Libraries\Basma\src\counter_2bits\untitled.vhd 12/29/11 14:06:48
-- hds header_start---- VHDL Architecture Basma.counter_2bits.untitled---- Created:-- by - Pharaoh.UNKNOWN (S)-- at - 13:55:37 12/29/2011---- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)---- hds header_endLIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all;
ENTITY counter_2bits IS-- Declarations PORT (rst, en, clk: IN Std_Logic; q : OUT Std_Logic);END counter_2bits ;
-- hds interface_endARCHITECTURE untitled OF counter_2bits ISSignal count_sig: unsigned (1 downto 0);BEGINProcess(rst,clk)Beginif (rst ='1') then count_sig <= (Others => '0');elsif (rising_edge(clk)) thenif (en = '1') thencount_sig <= count_sig +1;end if;end if;end process;q <= count_sig(0) and count_sig(1);END untitled;
Page: 1
C:\FPGAdv52\Libraries\Basma\src\counter_3bits\untitled.vhd 12/29/11 14:08:12
-- hds header_start---- VHDL Architecture Basma.counter_3bits.untitled---- Created:-- by - Pharaoh.UNKNOWN (S)-- at - 14:06:22 12/29/2011---- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)---- hds header_endLIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all;
ENTITY counter_3bits IS-- Declarations PORT (rst, en, clk: IN Std_Logic; q : OUT Std_Logic);END counter_3bits ;
-- hds interface_endARCHITECTURE untitled OF counter_3bits ISSignal count_sig: unsigned (2 downto 0);BEGINProcess(rst,clk)Beginif (rst ='1') then count_sig <= (Others => '0');elsif (rising_edge(clk)) thenif (en = '1') thencount_sig <= count_sig +1;end if;end if;end process;q <= count_sig(0) and count_sig(1) and count_sig(2);END untitled;
Page: 1
