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1-Bit Adder & 4-Bit Adder

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Design a 1-bit adder using VHDL.

Design a 4-bit adder with 4x(1-bit adders)using VHDL.

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File New Project Enter the Project name and location.

Select the preferred language (VHDL)

Sources New Source VHDL Module

Test Bench Waveform

VHDL Test Bench

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How to test your VHDL code?

Test bench Waveform

VHDL Test Bench

On the FPGA itself.

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Inputs: A (1 bit)

B (1 bit)

Cin (1 bit)

Outputs Sum = A xor B xor Cin

Cout = AB + BC + AC

BA

SUM

CinCout

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VHDL Code (1-Bit Adder)

entity isPort( );

end ;

architecture of is

begin{Code implementation}

end;

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Notes Libraries of the IEEE are analogous to the Libraries Import in JAVA.

Entity: defines the Input (in) & Output (out) ports.

Architecture: Comprises the Body of the code (Analogous to the Main

Method in JAVA) STD_LOGICmeans the value of this port will be 0 or 1

STD_LOGIC_VECTORmeans the value of this port will be a Vector

(array) of Zeros and Ones.

SUM

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Unit 1

1-BitAdder

B0A0

SUM 0

Cin= 01-BitAdder

B1A1

SUM 1

1-BitAdder

B2A2

SUM 2

1-BitAdder

B3A3

SUM 3

Cout

InputsA (4 bits)

B (4 bits)

OutputsSum (4 bits)

Cout (1 bit)

Unit 2Unit 3Unit 4

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Unit 1

1-BitAdder

Cin=0

1-BitAdder

1-BitAdder

1-BitAdder

InputsA (4 bits)

B (4 bits)

OutputsSum (4 bits)

Cout (1 bit)

Unit 2Unit 3Unit 4

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Unit 1

1-BitAdder

Cin= 01-BitAdder

1-BitAdder

1-BitAdder

: 3 2 1 0A (4 bits) : 0 1 1 0B (4 bits) : 1 0 1 1

---------------------------------

Sum (4 bits) : 1 1 1 1

Cout (1 bit) : 0 0 1 0

Unit 2Unit 3Unit 4

Cout, w3, w2, w1

Sum(3), Sum(2), Sum(1), Sum(0)

B(3), B(2), B(1), B(0)

A(3), A(2), A(1), A(0)

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Entity Declaration Specifying the circuits input & output ports.

Input ports : A represents : A(0), A(1), A(2), A(3). B represents : B(0), B(1), B(2), B(3).

Output ports: SUM represents : SUM(0), SUM(1), SUM(2), SUM(3) Cout

entity adder4 is

Port ( A : in STD_LOGIC_VECTOR (3 downto 0);B : in STD_LOGIC_VECTOR (3 downto 0);

sum : out STD_LOGIC_VECTOR (3 downto 0);cout : out STD_LOGIC);

end adder4;

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Architecture

Component and Signalare placed above theBegin and End of the

Architecture

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Architecture Component

Object of the (1-bitadder)

Analogous to the

Constructor headings inJava, however its

initializations(architecture) are in the

bitadder file

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Architecture

Signalw1, w2, w3 represents the

Carry outs of the 1-Bit

adder UNITs (1,2,3) -Inside the (4 Bit Adder)

w1, w2, w3Temporary values

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1. In the Main Method / 4-Bit adder architecture

Student A = new Student (Name, ID); Student B = new Student (Name, ID);

2. Calls the Constructor / Component

(VHDL) The Component

represents the JAVAConstructor heading ONLY

Public Student( N , ID )

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1. In the Main Method / 4-Bit adder architecture

Student A = new Student (Name, ID); Student B = new Student (Name, ID);

2. Calls the Constructor / Component

(VHDL) The Component

represents the JAVAConstructor heading ONLY

Public Student( N , ID )

Mapping

with the

Port

JAVA : The Constructor has

Inputs Only !!

Label

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3. The Constructor Body / 1-Bit adder file

.

* VHDL (Output/Returned values) are returned in the brackets.

* Java (Output/ Returned values) are stored to a NEW variable.

The Sum and Coutvalues will be returned

back to the units in

the Main 4-Bit AdderArchitecture.

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Unit 1

1-Bit

Adder

Cin= 01-Bit

Adder

1-Bit

Adder

1-Bit

Adder

Unit 2Unit 3Unit 4

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Feel Free to ask any question and help inimproving these slides by your highly

appreciated feedback.