VHDL Tutorial 1 Using Qucs
Author: David Schlaak © 2015
This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License.
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Objective
• To begin our investigation of VHDL using Qucs (Quite Universal Circuit Simulator)
Preamble
Qucs is an open source circuit simulator; that, while not as polished or user friendly as some commercial products, rivals many in capability and features.
The image at right shows the simulation types that Qucs can perform at the time of this writing. This series of tutorials is concerned with its ability to simulate digital VHDL code.
It is assumed that you are working in the Windows OS and have downloaded and installed Qucs. Also install all ancillary software indicated as necessary during the installation. It is available from http://qucs.sourceforge.net/download.html. The most recent version as of this writing is 0.0.18.
Procedure
1. Start Qucs by clicking on its icon from the Start button.
2. The main screen’s appearance will vary from that shown here depending upon how the program was last used. To obtain the clean slate shown here, select the Projects tab; then click of each revealed project followed by clicking the Delete button.
3. To create a new project, click the New button in the Projects tab. Name the new project something meaningful - andGate in this case. Ensure the open new project box is checked.
4. The project will now be created and the Content tab will be automatically opened to show which of the listed content types comprise the project. Since the project is currently empty, none of the types are populated.
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5. Click the New Text button shown here. You could also have selected File > New Text from the menu to create a new text file.
6. A new blank text window opens ready to receive your VHDL code. The previous window is still available on the top tab immediately to the left of the new untitled text window tab. The first window was a schematic drawing window. We will use it later.
7. Click the Save button (or File > Save as…). While we could write our code first and save later, saving now will enable editor syntax color highlighting which is very useful.
8. Pick a meaningful name - like andGate. The VHDL extension will be added automatically. Click the Save button.
9. The text file tab now contains the name of our file and chevrons have been added to the project’s content list in the left window. Clicking on the chevrons (if they point to the right) will expand them to show that the VHDL file has been added to the project.
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10. Type the code shown here. While Qucs doesn’t necessarily need it, every VHDL program should begin with these lines since their inclusion meets current VHDL coding standards.
11. While you could add the entity and architecture manually, Qucs can do some of the work for you. Click the Insert menu item, then select VHDL entity.
12. An empty entity/architecture pair is added for you to complete. Every VHDL program requires at least one entity/architecture pair. In specific instances, either the entity or architecture may be left empty. More on this in a later tutorial.
13. Modify your entity and architecture code to match that shown here. While indentation is not critical, it makes reading the code much easier. Get in the habit of following good coding practices. While Qucs will accept this code as shown, future tutorials will present better coding practices.
14. In VHDL, the entity declares the inputs and outputs (and their types) of a “black box”. The architecture declares the internal “circuitry” which gives the correct outputs in response to the inputs.
15. Save your work at this point (and do so often.)
16. Select the top untitled schematic tab.
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17. Select the Components tab of the left window.
18. From the drop down list at the top of the left window, select digital components.
19. Scroll through the digital components list to the VHDL file component. Left click on this component.
20. Move the mouse cursor into the schematic window and left click to place the VHDL file component. You could also click on the component and drag it into the schematic if you prefer.
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21. Right click on the VHDL file component you just placed to open a context menu. Select Edit Properties.
22. In the Edit Component Properties dialog, click the Browse button.
23. Select your saved VHDL file and click the Open button.
24. Change the Name of the component to andGate as shown here (or something else that is meaningful.) Ensure the display in schematic box is checked. Click the OK button.
25. Save your schematic giving it a meaningful name - like andGate. The proper schematic extension will be added automatically.
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26. The schematic now shows a graphical representation of your VHDL entity.
27. Click the Insert Port tool button shown here.
28. Left click to place a port at each of the andGate’s I/O pins.
29. To terminate this (or any) active command, either click the Select tool shown here, or press the Escape key.
30. Right click on the first port to open the context menu. Then select Edit Properties.
31. Change the port Name to a and ensure its display in schematic box is checked.
32. With the Properties > Name > Num field selected, ensure its display in schematic box is unchecked as shown here.
33. With the Properties > Name > Type field selected, change its type to in from the drop down list as shown here.
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34. Ensure its accompanying display in schematic box is unchecked as shown here.
35. Click the OK button.
36. Observe that the port symbol has changed shape to indicate it serves as input.
37. Repeat the preceding steps making the port for b type in; and the port for x type out.
38. Right click on the b port symbol and select Mirror about Y axis .
39. Left click on the Wire tool in the top tool bar.
40. Using the Wire tool, connect the ports to their respective I/O pins as shown here.
41. Right click in an empty area of the schematic to open a different context menu. Select Edit Circuit Symbol as shown here.
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42. This opens the sub-circuit component which was actually created by our VHDL code. Since convention dictates inputs should be on the left and outputs should be on the right, we need to relocate the b input and the x output.
43. Left click on the b input to select it as shown here. Be careful not to click on the line representing the pin.
44. You can now left click and drag the b input port toward the pin where it should be located as shown here.
45. Repeat these steps to move the x output port toward the pin where it should be located as shown here.
46. Right click on the x port to open the context menu, then select Mirror about Y axis.
47. Both the b port and the x port are now oriented properly for final placement in the sub-circuit.
48. Just as you previously moved the ports, now move them so their respective circles are positioned over the ends of the lines representing the pins.
49. Select the Components tab in the left window. In the paintings option of the top drop-down box, drag a Text component into your sub-circuit schematic.
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50. In the Edit Text Properties dialog, type an a. You can experiment with the Text color and Text size attributes.
51. Click the OK button.
52. Repeat these steps creating a b and an x.
53. Left click and drag these text entries next to their respective I/O pins as shown here. If you wish more precise placement, you can change Grid settings through File > Document Settings… Always restore the default Grid settings after moving text.
54. Now is a good time to save your work again. Try using the Save All tool.
55. Right click in an empty area of the symbol schematic to open a context menu, then select Edit Schematic.
56. Do not be alarmed if the schematic symbol hasn’t changed.
57. Everything up to this point has been to create a sub-circuit, from our VHDL code, that can be simulated in a digital circuit. We can now assemble this digital circuit.
58. Left click the New schematic tool.
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59. Select the Components tab in the left window. Select file components in the top drop-down box. Drag a Subcircuit component into your new schematic window.
60. Right click on the sub-circuit component, then select Edit Properties.
61. In the Edit Component Properties dialog, change the Name of the sub-circuit to something meaningful – like andGate. Ensure the display in schematic box is checked.
62. Click the Browse button. Navigate to (and select) the only schematic we have saved in our project thus far – our sub-circuit schematic.
63. This sub-circuit is the embodiment of our VHDL code.
64. In the Components tab of the left window, select digital components from the top drop-down box.
65. Select the digital source component at the top of the resulting list of available components.
66. Place a digital source component next to each of our sub-circuit inputs as shown here.
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67. Right click on the first digital source to open a context menu. Select Edit Properties.
68. In the resulting Edit Component Properties dialog, change the digital source > Name to a and ensure the display in schematic box is checked.
69. In the Properties section, ensure the display in schematic box is unchecked for each of the listed fields.
70. Ensure the Properties > times field is set to 1ns; 1ns.
71. Click the OK button.
72. Repeat the previous steps changing the second digital source > Name to b with display in schematic boxes checked/unchecked as done for source a.
73. Ensure the Properties > times field for source b is set to 2ns; 2ns as shown here.
74. Use the Wire tool to connect the digital sources to their respective input pins. Add a short wire to the output as shown here.
75. Left click on the Wire Label tool.
76. Left click on the open end of the output wire to place a Wire Label on it.
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77. In the Insert Nodename dialog, enter x as the output label. Then click the Ok button.
78. Save your work giving this schematic a meaningful name such as andGateCircuit. Do not use the same name as your sub-circuit. The proper extension will be added automatically.
79. Under the Components tab in the left window, select simulations from the drop-down box.
80. Drag a digital simulation component into your circuit.
81. Save your work at this point. If you don’t save prior to simulation, your circuit will fail.
82. Left click on the Simulate tool (or select (Simulation > Simulate from the menu bar.)
83. The Qucs Simulation Messages dialog will open briefly and close automatically if the simulation is successful. It will stay open if errors are encountered.
84. If errors occurred, you must correct them and re-simulate. If the simulation is successful, a new blank window will open. This window will be used to display our simulation results.
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85. With the Components tab selected in the left window, and diagrams selected from the top drop-down box, all of Qucs’ simulation output displays are visible. The proper display to select is governed by the type of circuit simulated. For digital circuits, both Truth Table and Timing Diagram are appropriate choices.
86. Drag a Truth Table component from the left window into the new right window.
87. The truth table’s Edit Diagram Properties dialog should automatically open. Scroll through the Dataset list in the left window. The last item will likely be the circuit output – x.X. Double click on this item to place it into the Graph window on the right.
88. Click the OK button.
89. The truth table should immediately populate with the simulation results. The a and b inputs are not specifically listed by default, while their state combinations are listed. You can specifically add them to the Graph window of the Edit Diagram Properties dialog; however, doing so will likely clutter the truth table unnecessarily. Knowing that the left-most columns of the truth table are the circuit inputs should suffice.
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90. Drag a Timing Diagram component from the left window into the .dpl window on the right. Its Edit Diagram Properties dialog should open automatically.
91. Resize the dialog and its various windows as necessary to see adequate information in its Dataset window to make proper choices.
92. Double click on inputs a.X and b.X near the top of the Dataset. Then scroll down and double click of the output x.X. These actions place the inputs and output into the Graph window.
93. The timing diagram requires that all inputs and outputs be selected by double clicking on each to copy them to the Graph window as shown above.
94. Shown here beneath the truth table is the timing diagram. The small red mark at its lower right corner indicates that all of its content is not visible. Click on the timing diagram to select it. If it is not selectable, press the Escape key and select the timing diagram again.
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95. Drag handles becomes visible in each of the corners of the timing diagram.
96. Drag the bottom right handle to resize the timing diagram so all of its data is visible.
97. Examination of the resulting truth table and diagram reveal that our VHDL code produces the correct output for all combinations of input.
98. From the menu, select Simulation > Show Last Netlist.
99. Qucs opens a text file (shown here in two parts) which it created to perform the simulation of our VHDL code. At the top of the file, Qucs repeated our code as shown here.
100. The rest of the file contains the code Qucs constructed from our VHDL code, the sub-circuit symbol we created, and from our test circuit. It is essentially what is called a Test Bench in VHDL simulation terms. Test Benches are the standard and preferred simulation technique used by engineering professionals. As we learn more VHDL, we will also learn how to write our own Test Benches because it is a necessary skill for all VHDL professionals.
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The rest of the file is shown below and will be examined/explained in tutorials to follow.
101. Show the instructor your final truth table and timing diagram.
Instructor Demo _____________________
