VHDL LAB MANUAL Starting With XILINX Tool for Chip Designing and simulation Design requirements: Design of ANDGate. The pin definitions and numbers are shown in the functional logic diagram as shown in below figure. Functional Logic Diagram a (in) c (out) b(in) b(in) Using the Design Software Starting the ISE7.1 Project Navigator Look for the Xilinx Icon and double click on it. Using the Xilinx ISE7.1 Project Navigator. The Xilinx Design System is the tool we will use to write our VHDL code and/or to draw our schematics and simulate them Department of Electronics & Communication 1 AND Gate
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VHDL LAB MANUAL Starting With XILINX Tool for Chip Designing and simulation
Design requirements: Design of ANDGate. The pin definitions and numbers are shown in the functional logic diagram as shown in below figure.
Functional Logic Diagram
a (in) c (out) b(in) b(in)
Using the Design Software
Starting the ISE7.1 Project Navigator
Look for the Xilinx Icon and double click on it.
Using the Xilinx ISE7.1 Project Navigator.
The Xilinx Design System is the tool we will use to write our VHDL code and/or to draw our schematics and simulate them electronically. If we draw a schematic, the schematic program will generate a VHDL program that includes all the information in our schematic. In order to use our Xilinx software and Xilinx FPGA chip, all of our designs must be made with parts that Xilinx Design Manager recognizes. These parts are the parts which are included in the Xilinx library.
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AND Gate
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Click on OK.
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Write and Compile VHDL program
To define your design using VHDL you will have to create a new VHDL source. To do this, select Project→New Source… and select VHDL Module.
A VHDL source file is created and opened in the edit/view window on the right-hand side of the project navigator. You can now write your VHDL program for the design. Once completed, save the program.
Once the VHDL program is completed, select Synthesize from the Processes window. Repair any syntax errors and repeat until the program compiles without errors or warnings.
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Building a Circuit
To build a schematic in Xilinx:
Open a new project by selecting New Project... from the File menu.
This will pop up the window shown in Figure: New Project
Give your project a name and location, the Device Family, the Device, the Package, and the Speed Grade. Make sure the Design Flow is XST VHDL… as shown in the subsequent screen shots. Then click FINISH.
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The above steps will create a .ise folder which can be used as a skeleton for
any program to be written using VHDL\Verilog for chip designing, as shown in
the screen shot below.
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Follow the steps as shown below, to create a New source for appropriate
design method to be used, i.e VHDL module\ Verilog module \ Test bench
etc… Also specify the file name for the same, and click NEXT.
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Specify the Entity and Architecture Name used for design then click NEXT
and FINISH.
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Space for writing code will be created, with some architecture and library
level coded lines generated automatically.
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Declare the variables for input, output or inout ports as required for the
functional block within entity using PORT declaration syntax.
Write necessary code within Architecture declaration.
Points to remember:
A design will have only one entity declaration and more than one
architecture body for an entity.
Entity Declaration includes : Port names and indicates whether they are
input, output or in-out ports and also specifies data-type for example:
BIT, STD_LOGIC, Integer etc.
Exa: Entity (
I1: IN std_logic;
O1: OUT std_logic
);
I1, O1: port names
In, Out: Mode
std_logic: data-type
Architecture declaration : There are three ways of declaring an
architecture, they are a) Structural (Component instantiation) b) Data
flow and c) Behavioral.
Signals and component instantiation are declared inside the
architecture (before Keyword Begin of Architecture).
Variables are declared inside the Process statements (don’t declare
signals inside the process).
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To ensure the code is syntactically correct click on Synthesize-XST or
Check syntax in Process View Window as shown below...
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Save the file or else pop-up as shown below will be displayed. If so click on
YES to save it.
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If syntactically correct all the options will be checked in GREEN as shown
below.
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SimulationModelSim is used to simulate the schematics made in Xilinx. This makes it
possible to simulate your design in Xilinx to verify its operation. You may do
so once your circuit is constructed by the following steps:
1.In Project Navigator highlight the schematic you want to simulate.
2. Double click on Launch ModelSim Simulator from the Xilinx Project
Navigator Window as seen in Figure
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The following window will be displayed in MODELSIM simulator with
corresponding I/O Ports as declared within Entity
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Follow the steps as shown to provide values for the input ports in order to
simulate the design.
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Check the waveforms created.
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OR
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Starting the MODELSIM XE
Look for the ModelSim Icon and double click on it.
The following window will be displayed..
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First make a do file.
Right click File Menu and open the existing AndGate source where you saved.
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Corresponding .vhd file will be opened.
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Compile the code using Compile in Menu bar.
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Click Compile then Done to close the compilation window.
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To simulate the design, select work\ filename.vhd in the library window and select simulate option by right clicking on the filename.
Following window will be displayed..
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#Kill old simulation if runningquit -sim#Start a new oneAndGate/Simulate#Bring up the waves window using viewwave option in Menu bar#Put signals of interest in waves windowadd wave InputAadd wave InputBadd wave OutputC#set the data input signals#force is to make sure that what you put over-rides anything else#0, 1 10ns -r 20ns means force to 0 for 10ns then force to 1, repeat every 20nsforce InputA 0, 1 10ns -r 20nsforce InputB 0, 1 20ns -r 40nsforce InputC 0, 1 10ns -r 20nsforce InputD 0, 1 20ns -r 40nsrun 160ns
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There are various options on running a simulation. The Run toolbar is shown below.
Restart-This resets the simulation and reassigns all of the inputs and outputs to U.Run-Run will cause the simulation to run for the designated about of picoseconds as shown above.Continue Run-This is used to restart simulation after breaking or stopping a simulation.Run All- This will cause the simulation to go on forever. You must click the break button to stop it at some point.Break- Used to stop a simulation from running.
Here are some keyboard shortcuts that may be useful while in the Wave window:
Zoom In- i I or +Zoom Out- o O or -Zoom Full- f or FZoom Last- l or LZoom Range- r or RNext Transition- tab
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For generating program file select Generate Programming File option in
Process View Window.
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Create Constraints File and Define Pin Assignments . Select the Assign Package Pins and assign the pins as follows:
Signal Pins XSA Function NAmea 48 DIPSW4(DIPSWID)b 51 DIPSW3(DIPSWIC)c 2 LED – S1
To assign the pins, enter the pin number (with a preceding p) in the Design Object List – I/O Pins window. Once the pins are assigned the window should look like the following figure:
Pin Assignment Image
Design Object List – I/O PinsI/O Name I/O
DirectionsLOC Function
BlockMacroloc
c Output P2a Input P48b Input P51It is very important to save and close the pin assignment window before proceeding to the next step. Otherwise your pin assignments may not be assigned correctly.
Select Assign Pin Package option in Process View window to do pin assignment as discussed above.
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To view RTL schematic of the functional block Run RTL Schematic in
Process View window.
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The corresponding RTL level block will be displayed as shown which indicates
input and output of the block.
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To view internal description of the block click on the RTL block then following
structure will be displayed.
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To view the process technology Run View Technology Schematic in
