ECE385DIGITAL SYSTEMS LABORATORYDIGITAL SYSTEMS LABORATORY
LectureIntroduction to VHDL
© Janak H Patel© Janak H. PatelDepartment of Electrical and Computer Engineering
University of Illinois at Urbana-Champaigny p g
TopicspProgrammable Logic
PLAs PLDs FPGAsPLAs, PLDs, FPGAsDesign Description LanguagesI t d ti t VHDLIntroduction to VHDL
Logic Value System of VHDLE titEntityArchitectureC SConcurrent Statements
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Programmable Logicg gProgrammable Logic Arrays (PLAs) and PALs
Two-level AND-OR array with True andTwo-level AND-OR array with True and Complemented inputs
Primarily used in large chip designsProgrammable Logic Devices (PLDs)
A variety of proprietary designs consisting of l PLA lik bl k d blseveral PLA like blocks and programmable
switches to interconnect themField Programmable Gate Arrays (FPGAs)Field Programmable Gate Arrays (FPGAs)
Thousands of identical macro-cells that can be interconnected by programmable switchesy p gEach macro-cell is a Programmable Logic Gate
Truth Table is stored in a RAM, called the Look-up T bl (LUT)
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Table (LUT)
PLDs and FPGAsSpeed
PLDs give predictable timing and give higherPLDs give predictable timing, and give higher system clock frequencyFPGA clock frequency is design dependent and q y g pusually much slower than PLDs
SizePLDs can accommodate up to 10,000 gatesFPGAs can accommodate up to 25 million gates
D i fl ibilitDesign flexibilityFPGAs often come with large memory and predefined function unitspredefined function units
ManufacturersXilinx, Altera, Lucent, Cypress, Lattice
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Xilinx, Altera, Lucent, Cypress, Lattice
Hardware Description Languagesp g gTwo Widely Used Languages
Verilog HDLVerilog HDLC-language like syntax, easy to learn
VHDLVHSIC Hardware Description LanguageVHSIC - Very High Speed Integrated CircuitsFollows the structure of ADA programming LanguageOriginally intended as a Simulation Language forOriginally intended as a Simulation Language for very large systemsVery Strongly Typed Language, for example, bit
t “0011” d i t ‘3’ t ilvector “0011” and integer ‘3’ are not easily interchangeable
Verilog and VHDL each have about 50% share of
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Verilog and VHDL each have about 50% share of the commercial user base
VHDLUses 9 Signal Values (IEEE standard)
A Signal Val e m st be enclosed in single q otesA Signal Value must be enclosed in single quotes‘0’ -- Forcing 0‘1’ Forcing 11 -- Forcing 1‘X’ -- Forcing Unknown‘-’ -- Don’t Care- Don t Care‘Z’ -- High Impedance‘U’ -- UninitializedU Uninitialized‘L’ -- Weak 0‘H’ -- Weak 1
Bit Vectors are enclosed in double quotesAn example of VHDL assignment statement
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p gY <=‘1’ when STATE =“0101” else ‘0’;
Entities and ArchitecturesEntity
External View: Pin-Out description, InterfaceExternal View: Pin Out description, Interface description, Input-Output Port definition etc.
ArchitectureInternal View
Structural Description - e.g. Gates and wiresB h i l D i ti f ti dBehavioral Description - e.g. functions and processes, RTL description, if-then-else, Add, Subtract
ENTITY muxDin
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ARCHITECTUREselDout2
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4-to-1 Multiplexer (behavioral)p ( )library IEEE; -- libraries needed foruse IEEE.std_logic_1164.all; -- simple logic functionsentity mux isport (sel: in std_logic_vector(1 downto 0);
Din: in std logic vector (3 downto 0);Din: in std_logic_vector (3 downto 0);Dout: out std_logic);
end entity mux;architecture my_mux_behavior of mux isbegin -- all comments are preceded by two dashesDout <= Din(3) when sel=“11” else -- first evaluate thisDout < Din(3) when sel 11 else first evaluate this
Din(2) when sel=“10” else -- next evaluate thisDin(1) when sel=“01” else -- then evaluate this
h l hDin(0) when sel=“00” else -- then evaluate this‘X’; -- if all fails then X
end architecture my mux behavior;
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y_ _ ;
(“when <condition> else” construct forces a priority structure in hardware synthesis)
4-to-1 Multiplexer (better behavioral)library IEEE;use IEEE.std_logic_1164.all;entity mux isport (sel: in std_logic_vector(1 downto 0);
Din: in std logic vector (3 downto 0);Din: in std_logic_vector (3 downto 0);Dout: out std_logic);
end entity mux;
architecture behavior of mux isbeginwith sel selectwith sel selectDout <= Din(3) when “11”, -- there is no specific order under
Din(2) when “10”, -- which conditions are evaluatedi (1) h “01”Din(1) when “01”,Din(0) when “00”,
‘X’ when others; --“default case” must be included
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end architecture behavior;
(“with <signal> select” construct results in better optimized hardware in synthesis)
4-to-1 Multiplexer using gatesp g gDin(3)
s0bars1bar
Din(2)
Di (1)Dout =
Din(1)
Din(0)
Din(3)●sel(1)●sel(0) +Din(2)●sel(1)●s0bar +Din(1)●s1bar●sel(0) +( ) ( )Din(0)●s1bar●s0bar
sel(1) sel(0)
architecture structure of mux issignal s0bar, s1bar; std_logic; -- internal signalsb ibegin
s0bar <= not(sel(0));s1bar <= not(sel(1));Dout <= (Din(3) and sel(1) and sel(0)) or
(Din(2) and sel(1) and s0bar) or
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(Din(2) and sel(1) and s0bar) or(Din(1) and s1bar and sel(0)) or(Din(0) and s1bar and s0bar);
end architecture structure;
4-to-1 Multiplexer (Structural)p ( )library IEEE;use IEEE.std_logic_1164.all;entity mux isport (sel: in std_logic_vector(1 downto 0);
Din: in std logic vector (3 downto 0);Din: in std_logic_vector (3 downto 0);Dout: out std_logic);
end entity mux;architecture structure of mux issignal s0bar, s1bar; std_logic; -- internal signalsbegin -- following three are concurrent signal assignments (CSAs)g f g g g ( )s0bar <= not(sel(0)); -- these are not executed sequentiallys1bar <= not(sel(1)); -- order of these CSAs is unimportant!Dout <= (Din(3) and sel(1) and sel(0))orDout < (Din(3) and sel(1) and sel(0))or
(Din(2) and sel(1) and s0bar) or(Din(1) and s1bar and sel(0)) or(Din(0) and s1bar and s0bar);
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(Din(0) and s1bar and s0bar);end architecture structure;
A Note about LibrariesIn almost all designs from now on, we will use the following Librariesfollowing Libraries
library IEEE;use IEEE STD LOGIC 1164 ALL;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE STD LOGIC UNSIGNED ALLuse IEEE.STD_LOGIC_UNSIGNED.ALL
These libraries permit use of predefined logic values logic operations like AND OR andvalues, logic operations like AND, OR, and arithmetic operations like + (add) etc.
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A Bit-Serial Logic UnitgF2-F0
A inA_out
One-bit wideLogic Unit“compute”
A_in
B_inF_A_B
computeB_out
entity compute isPort ( F : in std logic vector(2 downto 0);Port ( F : in std_logic_vector(2 downto 0);
A_In, B_In : in std_logic;A_Out, B_Out : out std_logic;F A B o t std logic)F_A_B : out std_logic);
end entity compute;
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Behavioral of Logic Processorgarchitecture Behavioral of compute isbeginwith F selectF_A_B <= A_In and B_In when "000",
A In or B In when "001",_ _ ,A_In xor B_In when "010",'1' when "011",A In nand B In when "100",A_In nand B_In when 100 ,A_In nor B_In when "101",A_In xnor B_In when "110",'0' when others; must be included'0' when others; -- must be included
A_Out <= A_In;B_Out <= B_In;
end architecture Behavioral;
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Concurrency in VHDLyConcurrent Signal Assignments (CSA)
All statements in a VHDL description are e ec tedAll statements in a VHDL description are executed concurrently unless specified within a processConcurrency is useful in describing combinationalConcurrency is useful in describing combinational logic circuitsA concurrent statement is evaluated when any ofA concurrent statement is evaluated when any of its arguments change its value
A process executes only on specified triggersA process executes only on specified triggersA process declaration includes a sensitivity listA process executes only when one of theA process executes only when one of the arguments in the sensitivity list changesProcesses are useful in describing sequential
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g qcircuits and state transition diagrams
Sequential Circuit Exampleq pentity up_down_counter is
t ( lk bl d i td l iport (clk, enable, up_down : in std_logic;asynch_clr: in std_logic;Q: out std logic vector(7 downto 0);Q: out std_logic_vector(7 downto 0);
end entity;
8 bit U D C t
enableup down
8-bit Up-Down Counterasynch_clr
clk
p_
Q(7) Q(6) . . . . . Q(1)Q(0)
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Counter Behaviorarchitecture counter_behavior of up_dn_counter issignal count: std_logic_vector(7 downto 0);Begin count is an internal signal to this processBegin -- count is an internal signal to this processprocess(clk, asynch_reset) -- sensitivity listbeginif (asynch reset=‘1’) then count <= “00000000”;if (asynch_reset= 1 ) then count <= 00000000 ;elsif (rising_edge(clk)) then – synchronous state transitionsif (enable=‘1’) thenif (up down=‘1’) then count <= count+”00000001”;if (up_down 1 ) then count < count+ 00000001 ;
else count <= count-”00000001”;end if;end if;;-- ‘end if’ is not permitted here to match ‘elsif’end if;end process;pQ <= count;end architecture counter_behavior;
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Note: We cannot use “Q <= Q + 1” since Q is defined as output only
Sequential Circuit Example-2q pentity up_down_counter is
t ( lk bl d i td l iport (clk, enable, up_down : in std_logic;synch_clr: in std_logic;Q: buf std logic vector(7 downto 0);Q: buf std_logic_vector(7 downto 0);
-- ‘buf’ is same as ‘out’ but can be read inside the processend entity;
8 bit U D C t
enableup down
8-bit Up-Down Countersynch_clr
clk
p_
Q(7) Q(6) . . . . . Q(1)Q(0)
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Counter Behavior-2architecture counter_behavior of up_dn_counter isbeginprocess(clk, synch_reset) -- sensitivity listbeginif (rising_edge(clk) then_if(synch_reset=‘1’) then Q <= “00000000”;elsif (enable=‘1’) then --notice no ‘e’ in ‘elsif’if (up down=‘1’) then Q <= Q + ’1’( p_ ) Q Q
else Q <= Q - ’1’;end if;
-- “end if” is not permitted here to match the “elsif”end if is not permitted here to match the elsifend if;end if; -- notice it is ‘end if’ not ‘endif’end process;end process;end architecture counter_behavior;
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4-Bit Shift Registerg
entity reg_4 isPort (Shift_In, Load, Shift_En, Clk : in std_logic;
D : in std_logic_vector(3 downto 0);Shift Out : out std logic;_ _ gData_Out : out std_logic_vector(3 downto 0);
end entity reg_4;
D 44
4-Bit Register“reg 4”
Shift_In
Load Shift Out
Data_Out4
reg_4LoadShift_En
Clk
Shift_Out
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Shift-Register Behaviorgarchitecture Behavioral of reg_4 is signal reg_value: std_logic_vector(3 downto 0); b ibegin operate_reg: process (Load, Shift_En, Clk, Shift_In) begin
if (rising_edge(Clk)) then if (Shift_En = '1') then reg value <= Shift In & reg value(3 downto 1);g_ _ g_ ( )
-- operator “&” concatenates two bit-fieldselsif (Load = '1') then reg value <= D; -- parallel load (lower priority than shift)reg_value < D; parallel load (lower priority than shift)
else reg_value <= reg_value; --keep data unchanged
end if;end if; end if;
end process;D t O t < l
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Data_Out <= reg_value; Shift_Out <= reg_value(0);end architecture Behavioral;
Control Unitentity control isPort ( Reset, LoadA, LoadB, Execute : in std_logic;
Clk : in std_logic;Shift_En, Ld_A, Ld_B : out std_logic);_ _ _ _
end entity control;
Input switches C l Bi
Control
ResetLoadA
Shift_En
Input switches Control Bits
Control(state machine)LoadB
ExecuteLd_A
Clk Ld_B
0 1 d d d d 10
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A FEDCB0 1 d d d d 1
Shift ShiftShift Shift HaltReset
Controller State Machinearchitecture Behavioral of control istype cntrl state is (A, B, C, D, E, F);type cntrl_state is (A, B, C, D, E, F);-- User defined type “cntrl_state” has 6 symbolic valuessignal state, next_state : cntrl_state; beginbegin
control_reg: process (Reset, Clk, LoadA, LoadB)begin
if (Reset = '1') thenstate <= A;
elsif (rising_edge(Clk)) then_state <= next_state;
end if;end process; p ;
-- Behavioral continued on next two slides for Next State and Output Functions
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See Sequence Recognizer Example in Mano and Kime (ECE 290 Text Book)
State Transitionsget_next_state: process (Execute, state)begin
case state iswhen A =>
if (Execute = '1') thennext_state <= B;
elsenext_state <= A;
end if;when B => next_state <= C;when C => next state <= D;_when D => next_state <= E;when E => next_state <= F;
--wait at state F until 'Execute' = 0when F =>when F =>
if (Execute = '0') thennext_state <= A;
elsenext state <= F;next_state <= F;
end if;-- “when others =>” default case is not needed here since there are -- only six values for “state” and we have exhausted them all.
end case;
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end case;end process;
Outputs (Moore machine)p ( )get_cntrl_out: process (LoadA, LoadB, state)begin
case state iscase state iswhen A =>-- Enable Register-Loads only when in state A
Ld A <= LoadA;_Ld_B <= LoadB;Shift_En <= '0’;
h F Ld A '0' Ld B '0'when F => Ld_A <= '0'; Ld_B <= '0';Shift_En <= '0';
when others => -- “others” are states B C D and Ewhen others => -- others are states B,C,D and ELd_A <= '0'; Ld_B <= '0';Shift_En <= ‘1';
end case;end process;
d
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end architecture Behavioral; -- started on page 23
State Machine EncodinggState Machine Encoding and Synthesis
S nthesis a tomaticall picks the “best” encodingSynthesis automatically picks the “best” encodingOr, you can specify the encoding for your state machine explicitlymachine explicitlyExamples of State Encodings (for 5 States)
Arbitrary Binary Encoding: 011 101 000 111 010Arbitrary Binary Encoding: 011, 101, 000, 111, 010Enumerated Binary: 000, 001, 010, 011, 100One-Hot: 00001 00010 00100 01000 10000One Hot: 00001, 00010, 00100, 01000,10000
See VHDL example code from Xilinxhttp://toolbox.xilinx.com/docsan/xilinx4/data/docs/sim/vtex9.htmlp
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Using “Components”g pentity full_adder isport (x, y, z : in std logic); x y zp y _ g
s, c : out std_logic);end entity;-- we will use the component full_adder to
x y z
c sfull_adder
sumcarry-- build a 4-bit ripple carry adder
entity ADDER4 isport (A B : in std logic vector (3 down to 0);
sumcarry
port (A,B : in std_logic_vector (3 down to 0);S : out std_logic_vector (3 down to 0);c_in : in std_logic;
t t td l i )c_out : out std_logic);end entity;
A0 B0A1 B1A2 B2A3 B3
S0S1S2S3ADDER4 c_inc_out
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S0S1S2S3
Connecting Componentsg parchitecture structural of ADDER4 iscomponent full_adder is
t( i td l i t td l i ) d h dport(x,y,z: in std_logic; s,c: out std_logic); -- reproduce the entity descriptionend component full_adder; -- omit name “full_adder” for older simulatorssignal c0,c1,c2: std_logic; -- internal wires needed to connect full addersbegin -- this illustrates how to instantiate and connect componentsFA0: full_adder port map(x =>A(0), y =>B(0), z =>c_in, s =>S(0), c =>c0);FA1: full adder port map(x =>A(1), y =>B(1), z =>c0, s =>S(1), c =>c1);_ p p( ( ), y ( ), , ( ), );FA2: full_adder port map(x =>A(2), y =>B(2), z =>c1, s =>S(2), c =>c2);FA3: full_adder port map(x =>A(3), y =>B(3), z =>c2, s =>S(3), c =>c_out);end architecture structural ADDER4end architecture structural ADDER4
A1 B1 A0 B0A3 B3 A2 B2
x y
sc zFA1c1 x y
sc zFA0c0x y
sc zFA3c_out x y
sc zFA2c2 c_in
28S1 S0S3 S2
Putting it all togetherg g
entity my_system6
D6
3 A6
RegisterUnit
ComputeUnit
F3
2 B6
R ti C t lLoadAR
2
RoutingUnit
ControlUnitLoadB
Execute
Reset
Clock
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Architecture of my_systemy_ yarchitecture structural of my_system iscomponent compute is -- entity description reproducedport(A in B in: in std logic; F2-F0port(A_in, B_in: in std_logic;
A_out, B_out, F_A_B: out std_logic;F: in std_logic_vector(2 downto 0));
end component compute;
entitycompute
A_in
B in
F_A_B
A_out
B out
F2-F0
end component compute; component register_unit is... -- reproduce entity description herecomponent router is
B_in B_out
component router is... -- reproduce entity description herecomponent control is... -- reproduce entity description herep y pend component control;signal ...; –- declare all signals needed to interconnect componentsbegin... -- instantiate and connect all components in main bodycomputation_unit: computeport map(F=>F, A_in=> ..., B_in=>..., F_A_B=>...);
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...end architecture structural my_system;
SummaryyVHDL is a design description language – not a language that automatically designs for you!language that automatically designs for you!
The design process is very similar to the designing with TTL chips and wires, but with much more fl ibili d f i liflexibility and functionalityIn VHDL you create your own “chips” (entities) and connect the “pins” (ports) with “wires” (signals)connect the pins (ports) with wires (signals)You cannot make bigger TTL chips out of smaller chips, but with VHDL you can make bigger and p , y ggmore complex entities out of smaller entities (e.g. a 16-bit ALU out of 16 one-bit ALU slices)
Y t fi t d i i bl kYou must first design on paper using block diagrams and interconnections, before you can describe it in VHDL!
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