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Introduction to VHDL

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Introduction to VHDL

HDL is short for Hardware DescriptionLanguage

VHDL VHSIC Hardware Description Language

(VHSIC: Very High Speed Integrated Circuits)

VHDL is a standard developed by IEEE(Institute of Electrical and ElectronicsEngineers)

We will use DirectVHDL program for writingand simulating VHDL codes.

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DirectVHDL

An interactive VHDL simulator

Allows editing and simulating VHDL designwithout complicated setup or compilationprocedures

DirectVHDL includes the following:

- VHDL Workspace

- VHDL Editor

- VHDL Simulator- VHDL Tutorial

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Using DirectVHDL

Double click the symbol to open the

VHDL Workspace.

VHDL Workspace is a manager that serves as a

starting point to launch the VHDL editor andsimulator.

It is the main workstation of DirectVHDL

program.

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VHDL Workspace

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VHDL Workspace

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Opening a new file in VHDL Workspace

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Opening a new file in VHDL Workspace

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VHDL Editor

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Simulation of a .vhd file

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Simulation of a .vhd file

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Simulation of a .vhd file

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Changing Time Step

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Changing View Interval

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Simulation of a .vhd file

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Simulation of a .vhd file

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Adding Trace/Watch

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Opening the waveform report

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Programming in VHDL

There are three programming strategies in VHDL:

- Dataflow

- Structural

- Behavioral

Most of time a mixture of these three methods

are used.

Each statement in VHDL ends with ;

The comment lines begin with --

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Dataflow programming in VHDL

In data-flow approach, circuits are described

by indicating how the inputs and outputs of

built-in primitive components are connected.

In other words, we describe how signals (data)flow through the circuit.

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Dataflow programming example in

VHDL

entity sample_gate is

port(a,b: in bit;

c: out bit);

end sample_gate;

architecture dataflow of sample_gate is

begin

c

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Dataflow programming example in

VHDL

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Structural programming in VHDL

In this strategy, every portion of a VHDL

design is considered as a block and they are

named as entity.

The entity describes the interface to that blockand a seperate part associated with the entity

describes how that block operates.

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Structural programming example

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Structural programming example:

Code Part-1

entity and_gate isport(a1,b1: in bit;

c1: out bit);

end and_gate;

entity nor_gate is

port(a2,b2: in bit;

c2: out bit);

end nor_gate;

entity or_gate is

port(a3,b3: in bit;

c3: out bit);

end or_gate;

entity simple isport(a4,b4,c4,d4: in bit;

g4: out bit);

end simple;

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Structural programming example:

Code Part-2

architecture dataflow of and_gate is

begin

c1

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Structural programming example:

Code Part-3architecture structure of simple is

signal e4:bit;

signal f4:bit;

component and_gate

port(a1,b1: in bit;

c1: out bit);

end component;

component nor_gateport (a2,b2: in bit;

c2: out bit);

end component;

component or_gate

port (a3,b3: in bit;

c3: out bit);

end component;

begin

n1:and_gate

port map (a4,b4,e4);

n2:nor_gate

port map (c4,d4,f4);

n3:or_gate

port map (e4,f4,g4);

end structure;

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Structural programming example:

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Same circuit but programmed with dataflow

strategy

entity sample_gate_dataflow is

port (a,b,c,d: in bit;

o3: out bit);

end sample_gate_dataflow;

architecture dataflow of sample_gate_dataflow is

signal o1: bit;

signal o2: bit;

begin

o1

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Same circuit but programmed with dataflow

strategy

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SR Latch using dataflow strategy

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SR Latch using dataflow strategy:

Code

entity latch is

port(s,r: in bit;

q,nq: out bit);

end latch;

architecture dataflow of latch issignal q: bit := '1';

signal nq: bit := '0';

begin

q

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SR Latch using dataflow strategy:

Simulation

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Behavioral Programming

Blackbox approach to modeling.

Used to model complex components thatwould be tedious to model using the othermethods.

Behavioral descriptions are supported byprocess statement

The statements in the process are used to

compute the outputs of the process from itsinputs.

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A behavioral & structural programming example:

4-bit Binary Counter Design using D-Flip Flops

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4-bit Binary Counter Design using D-Flip Flops

Code: Part-1

entity Dflipflop is

Port(resetn,D,clock :in bit;

Q1,Q2 : out bit);

end Dflipflop;

--

architecture behavior of Dflipflop is

begin

p1: process (resetn,D,clock)

begin

if resetn = '1' then

Q1

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4-bit Binary Counter Design using D-Flip Flops

Code: Part-2entity binary_counter is

port(resetn,D,clk:in bit;

Qb1,Qb1n,Qb2,Qb2n,Qb3,Qb3n,Qb4,Qb4n: out bit);end binary_counter;

architecture structure of binary_counter is

component Dflipflop

Port(resetn,D,clock :in bit;

Q1,Q2 : out bit);

end component;

n1: Dflipflop

port map (resetn,Qb1n,clk,Qb1,Qb1n);

n2: Dflipflop

port map (resetn,Qb2n,Qb1n,Qb2,Qb2n);

n3: Dflipflop

port map (resetn,Qb3n,Qb2n,Qb3,Qb3n);

n4: Dflipflop

port map (resetn,Qb4n,Qb3n,Qb4,Qb4n);

end structure;

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4-bit Binary Counter Design using D-Flip Flops

-Simulation-

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4-bit Binary Counter Design using D-Flip Flops

-Simulation-

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References

DirectVHDL Help Content