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VHDLTutorial 1Digital Systems CE00057-6Signal Processing, CE00039-2Signal Processing, CE00039-2Shortly About the VHDLVHDL is an acronym of VHSIC Hardware Description Language

VHSIC is an acronym of Very High Speed Integrated Circuits

A Formal Language for Specifying the Behavior and Structure of a Digital Circuit

Digital Systems CE00057-6Signal Processing, CE00039-2Signal Processing, CE00039-2Introduction Two major HDLs:VHDL standardized by IEEE in 1987,1993, 2002, 2006 object-oriented, very widely used Has Verbose syntax like AdaVerilog standardized by IEEE in 1995, 2001, 2005 has concise syntax like CDigital Systems CE00057-6Signal Processing, CE00039-2Signal Processing, CE00039-2ModelSim XE II 5.7gDigital Systems CE00057-6

Signal Processing, CE00039-2Signal Processing, CE00039-2ModelSim XE II 5.7gDigital Systems CE00057-6

Signal Processing, CE00039-2Signal Processing, CE00039-2ModelSim XE II 5.7gDigital Systems CE00057-6

Signal Processing, CE00039-2Signal Processing, CE00039-2ModelSim XE II 5.7gDigital Systems CE00057-6

Signal Processing, CE00039-2Signal Processing, CE00039-2ModelSim XE II 5.7gDigital Systems CE00057-6

Signal Processing, CE00039-2Signal Processing, CE00039-2ModelSim XE II 5.7gDigital Systems CE00057-6

Signal Processing, CE00039-2Signal Processing, CE00039-2ModelSim XE II 5.7gDigital Systems CE00057-6

Signal Processing, CE00039-2Signal Processing, CE00039-2ModelSim XE II 5.7gDigital Systems CE00057-6

Signal Processing, CE00039-2Signal Processing, CE00039-2ModelSim XE II 5.7gDigital Systems CE00057-6

Signal Processing, CE00039-2Signal Processing, CE00039-2VHDLTutorial 2Digital Systems CE00057-6Signal Processing, CE00039-2Signal Processing, CE00039-2Hardware abstraction

Signal Processing, CE00039-2Signal Processing, CE00039-2External view specifies the interface of the device through which it communicates with other models in its environment.Internal view specifies the functionality/structure of the device.The hardware abstraction of any digital system is called Entity.

Signal Processing, CE00039-2Signal Processing, CE00039-2Primary design unitsTo describe an entity, there are 5 primary design units;Entity declarationArchitecture bodyConfiguration declarationPackage declarationPackage body Plus library declarationSignal Processing, CE00039-2Signal Processing, CE00039-2Entity & its model

Signal Processing, CE00039-2Signal Processing, CE00039-2Library declaration: syntax

Library library_name; Use library_name.package name.package parts;

librarypackagesieee libraryStd_logic_1164Std_logic_arithStd_logic_signedStd_logic_unsigned

Signal Processing, CE00039-2Signal Processing, CE00039-2Entity declaration: syntax Entity entity_name is Port( port_name:signal mode signal type; . . ); End entity_name;

Signal Processing, CE00039-2Signal Processing, CE00039-2Architecture body:syntax

architecture architecture_name of entity_name is {declaration}; Begin {code}; end architecture_name;

Signal Processing, CE00039-2Signal Processing, CE00039-2AND gatelibrary ieee;use ieee.std_logic_1164.all;entity and2 isport(x,y:in std_logic;z:out std_logic);end and2;architecture data flow of and2 isbeginz