Virtual Logic Netlist: Enabling efficient RTL

analysisSpandana Rachamalla, Arun Joseph, Rahul Rao, Diwesh Pandey

IBM Systems GroupE-mail: arujosep@in.ibm.com

Session 6B. EDA for Design Exploration & Analysis Beyond Moore’s Law

Overview Why do we need a Virtual Logic Netlist (VLN) ? What is a VLN ? VLN based RTL clock gating analysis framework. Evaluation on IBM POWER8 microprocessor.

Slide 2VIRTUAL LOGIC NETLIST: ENABLING EFFICIENT RTL ANALYSIS

Why VLN Early design analysis & related challenges. Quick synthesis based prior approaches. Formal, Probability based prior approaches. VLN-based RTL analysis.

Slide 3VIRTUAL LOGIC NETLIST: ENABLING EFFICIENT RTL ANALYSIS

VLN based RTL analysis Enable Reuse, Continuity & Turn around time reduction Backend tool engines for RTL analysis

without the need for a synthesis operation.

VLN: Key Aspects Representation of logic structure and

hierarchy, without capturing actual logic. Modeled using the same data structures

used to model physical design netlist.RTL Contained Analysis

Netlist-Based Backend

Tool Engines

Virtual Logic Netlist

RTLRTL

Analysis

Collateral RTL Information

RTL Contained Analysis

Netlist-Based Backend

Tool Engines

Virtual Logic Netlist

RTLRTL

Analysis

Collateral RTL Information

Slide 4VIRTUAL LOGIC NETLIST: ENABLING EFFICIENT RTL ANALYSIS

VLN based analysis: Application Analysis of criteria that has greater dependency on the micro-architecture and logical implementation. Independent of physical parameters. Available earlier in the design cycle. Partial designs. Example - workload-dependent clock gating analysis & rollup.

Not applicable for all kind of analysis. Cannot perform accurate power or reliability analysis.

Slide 5VIRTUAL LOGIC NETLIST: ENABLING EFFICIENT RTL ANALYSIS

VLN creation

Logic Information (RTL)

Logic HierarchyStructure

Extraction Engine

Logic HierarchyStructure

Information

User Defined Constraints:

Logic Pruning Identifiers

A

F

E

B

D

C

Virtual Logic Netlist

Virtual Logic Netlist Creation Engine

Logic Information (RTL)

Logic HierarchyStructure

Extraction Engine

Logic HierarchyStructure

Information

User Defined Constraints:

Logic Pruning Identifiers

A

F

E

B

D

C

Virtual Logic Netlist

Virtual Logic Netlist Creation Engine

Virtual Logic Netlist Creation Engine

1. Load data structure definitions used to model the design contents of a hierarchical Physical Design netlist.

2. Process the Logic hierarchy structure information.

3. Using 1 and 2 create in-memory hierarchical data structures, which is representative of the Logic Hierarchy Structure, without capturing the logic content.

Slide 6VIRTUAL LOGIC NETLIST: ENABLING EFFICIENT RTL ANALYSIS

VLN-based RTL clock gating analysis

The concept was applied to develop a new framework, EinsCG, for early RTL contained clock gating analysis.

RTL Contained Clock Gating Analysis

Virtual Logic Netlist

RTLRTL Clock

GatingAnalysis

Micro-benchmark driven Logic Simulation based Switching Activity Information

Netlist-Based Backend Tool Engines for

Activity Extraction and Clock Gating Analysis

RTL Contained Clock Gating Analysis

Virtual Logic Netlist

RTLRTL Clock

GatingAnalysis

Micro-benchmark driven Logic Simulation based Switching Activity Information

Netlist-Based Backend Tool Engines for

Activity Extraction and Clock Gating Analysis Virtual Logic

Netlist (VLN)

VLN2IDM

IDM: Integrated Data Model

Netlist-BasedBackend Tools

and Engines

RTL C

lock Gating Analysis

Framew

ork TCL Interface

Virtual LogicNetlist (VLN)

VLN2IDM

IDM: Integrated Data Model

Netlist-BasedBackend Tools

and Engines

RTL C

lock Gating Analysis

Framew

ork TCL Interface

Slide 7VIRTUAL LOGIC NETLIST: ENABLING EFFICIENT RTL ANALYSIS

VLN evaluation on IBM POWER8

The different core and nest units of the POWER8 processor were evaluated for clock gating, under different micro-benchmark conditions.

VLN FlowLogic Synthesis

LCW-based Unit Clock Gating Rollup on PD Netlist Hierarchies

LCW-based Unit Clock Gating Rollup on VLN Hierarchies

Compare

Logic Simulation based Switching Activities

POWER8Processor Unit RTL

MicroBenchmark

PD-CG VLN-CG

Netlist Based Clock Gating Analysis

Netlist BasedClock Gating Analysis

VLN FlowLogic Synthesis

LCW-based Unit Clock Gating Rollup on PD Netlist Hierarchies

LCW-based Unit Clock Gating Rollup on VLN Hierarchies

Compare

Logic Simulation based Switching Activities

POWER8Processor Unit RTL

MicroBenchmark

PD-CG VLN-CG

Netlist Based Clock Gating Analysis

Netlist BasedClock Gating Analysis

Slide 8VIRTUAL LOGIC NETLIST: ENABLING EFFICIENT RTL ANALYSIS

Evaluation results Error of less than 2% across the POWER8 core and nest units, and across workloads.

TAT improvement of ~250X (when compared with synthesis) on the POWER8 IFU.

Continuity across the design flow for clock gating analysis & rollup.

Experiment 1: Accuracy across POWER8 core units

0

20

40

60

80

100

DFU FXU ISU VSU IFU LSU

Core design unit

Acc

urac

y (%

)

Accuracy (%)

Experiment 1: Accuracy across POWER8 uncore units

0

20

40

60

80

100

EH EN ES MCU L2 L3 PBH_PBIEX

Uncore design unitA

ccur

acy

(%)

Accuracy (%)

Slide 9VIRTUAL LOGIC NETLIST: ENABLING EFFICIENT RTL ANALYSIS

Summary Introduced the concept of virtual logic netlist to enable early & efficient RTL analysis using backend tools and algorithms. The construction of VLN and its application to develop a new framework for RTL contained clock gating analysis is presented. Experimental evaluation on a server-class microprocessor chip was performed. The concept of VLN can be further explored for more RTL-like analysis which is dependent on the logical graph, but independent of the physical properties of the design.

Slide 10VIRTUAL LOGIC NETLIST: ENABLING EFFICIENT RTL ANALYSIS