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Virtual Prototyping in SpaceFibre System-on-Chip Design Ilya Korobkov, Junior Researcher, Saint-Petersburg State University of Aerospace Instrumentation © Accellera Systems Initiative 1
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Page 1: Virtual Prototyping in SpaceFibre System-on-Chip Design...Virtual Prototyping in SpaceFibre System-on-Chip Design Ilya Korobkov, Junior Researcher, ... running em b ed d ed so f t

Virtual Prototyping in SpaceFibre System-on-Chip Design

Ilya Korobkov, Junior Researcher,

Saint-Petersburg State University of Aerospace Instrumentation

© Accellera Systems Initiative 1

Page 2: Virtual Prototyping in SpaceFibre System-on-Chip Design...Virtual Prototyping in SpaceFibre System-on-Chip Design Ilya Korobkov, Junior Researcher, ... running em b ed d ed so f t

Network Memory Controller

© Accellera Systems Initiative 2

MIPS 324KEp RAM

DMARegisters Routing table

SpFi controller 1

Cro

ssb

ar

Broadcast controller

Interrupt/Acknowledge controller

Configuration port

AXI BUS

SpFi controller 2

SpFi controller 3

SpFi controller N

SpaceFibre port 3

SpaceFibre port N

SpaceFibre port 1

SpaceFibre port 2

...

OVP

SystemC/TLM 2.0

*SpaceFibre – abridgement SpFi

Page 3: Virtual Prototyping in SpaceFibre System-on-Chip Design...Virtual Prototyping in SpaceFibre System-on-Chip Design Ilya Korobkov, Junior Researcher, ... running em b ed d ed so f t

VSP: Cadence Virtual System Platform

© Accellera Systems Initiative 3

Virtual prototype

Create new IP blocks (tlmgen)

Provide access to processor models

(ARM Fast Models, Imperas)

Assemble the IP blocks into a

virtual prototype

Work with virtual prototype

(configuration, simulation,

debugging)

Software

Using virtual prototype for

running embedded software

Testing embedded software

inside the prototype

Analyze performance of

architecture and embedded

software

Page 4: Virtual Prototyping in SpaceFibre System-on-Chip Design...Virtual Prototyping in SpaceFibre System-on-Chip Design Ilya Korobkov, Junior Researcher, ... running em b ed d ed so f t

tlmgen tool• Generates TLM module templates with memory mapped

registers

• Helps to avoid common errors as naming inconsistencies, register overlapping, and illegal register accesses by the software

• Speeds up development time

There are two forms of input data:

simple register definition language (simpleRDL)

IP-XACT XML

© Accellera Systems Initiative 4

Page 5: Virtual Prototyping in SpaceFibre System-on-Chip Design...Virtual Prototyping in SpaceFibre System-on-Chip Design Ilya Korobkov, Junior Researcher, ... running em b ed d ed so f t

RDFfile – Register Description FileIt is input data for tlmgen on simpleRDL language

It consists of:

• description of registers: fields and register banks

• ports specification

• parameter specification

© Accellera Systems Initiative 5

Page 6: Virtual Prototyping in SpaceFibre System-on-Chip Design...Virtual Prototyping in SpaceFibre System-on-Chip Design Ilya Korobkov, Junior Researcher, ... running em b ed d ed so f t

Result of tlmgen using

TLM-2.0 module template was generated for “DMA”

© Accellera Systems Initiative 6

dma

doc test

dma_hwtest

systemc

src inc cfg build

dma_test.cpp

dma_test.h

dma_test_tlm2.cxx

dma_test_tlm2.hxx

tlm2_test_build.sh

dma_bank.cxx

dma_base_tlm2.cxx

dma_tlm2.cxx

dma.cpp

dma.h

dma_bank.hxx

dma_base_tlm2.hxx

dma_reg_defs.h

dma_reg_defs_const.hxx

dma_reg_desc_macro.hxx

dma_register_class.hxx

dma_standard_headers.hxx

dma_tlm2.hxx

platform_type_defs.hxx

dma.conf

dma_model.conf.internaldma_build.sh

dma.tex

Page 7: Virtual Prototyping in SpaceFibre System-on-Chip Design...Virtual Prototyping in SpaceFibre System-on-Chip Design Ilya Korobkov, Junior Researcher, ... running em b ed d ed so f t

Benefits of tlmgen

• Input data format is simple and clear

• You can add new sockets, classes, threads and processes to template

• It provides classes for register description

• It decreases time for IP block development

• It helps to avoid common errors as naming inconsistencies, register overlapping

© Accellera Systems Initiative 7

Page 8: Virtual Prototyping in SpaceFibre System-on-Chip Design...Virtual Prototyping in SpaceFibre System-on-Chip Design Ilya Korobkov, Junior Researcher, ... running em b ed d ed so f t

SimVision for debugging code• Breakpoints can be created in objects, functions, processes• Step-by-step simulation and debugging• Waveforms• Viewer of the variables, data members, call stack, processes• ...

© Accellera Systems Initiative 8

Page 9: Virtual Prototyping in SpaceFibre System-on-Chip Design...Virtual Prototyping in SpaceFibre System-on-Chip Design Ilya Korobkov, Junior Researcher, ... running em b ed d ed so f t

Performance Analyzing (1/3)• Static information about your SystemC design• Simulation run-time information (dynamic)• More than 10 performance metrics: throughput,

TLM response status, read/write accesses, bytes transferred …

It is useful for finding performance bottlenecks!

© Accellera Systems Initiative 9

Page 10: Virtual Prototyping in SpaceFibre System-on-Chip Design...Virtual Prototyping in SpaceFibre System-on-Chip Design Ilya Korobkov, Junior Researcher, ... running em b ed d ed so f t

Performance Analyzing(2/3)

© Accellera Systems Initiative 10

Resource usage

CPU and Memory

Run-time distribution of resources between processes

Page 11: Virtual Prototyping in SpaceFibre System-on-Chip Design...Virtual Prototyping in SpaceFibre System-on-Chip Design Ilya Korobkov, Junior Researcher, ... running em b ed d ed so f t

Performance Analyzing(3/3)

© Accellera Systems Initiative 11

Set chart options to show simulation results

Plots with required parameters

Page 12: Virtual Prototyping in SpaceFibre System-on-Chip Design...Virtual Prototyping in SpaceFibre System-on-Chip Design Ilya Korobkov, Junior Researcher, ... running em b ed d ed so f t

Network Memory Controller

© Accellera Systems Initiative 12

MIPS 324KEp RAM

DMARegisters Routing table

SpFi controller 1

Cro

ssb

ar

Broadcast controller

Interrupt/Acknowledge controller

Configuration port

AXI BUS

SpFi controller 2

SpFi controller 3

SpFi controller N

SpaceFibre port 3

SpaceFibre port N

SpaceFibre port 1

SpaceFibre port 2

...

OVP

SystemC/TLM 2.0

Page 13: Virtual Prototyping in SpaceFibre System-on-Chip Design...Virtual Prototyping in SpaceFibre System-on-Chip Design Ilya Korobkov, Junior Researcher, ... running em b ed d ed so f t

First results:

Performance Testing of SpaceFibre ports for Streaming Data

© Accellera Systems Initiative 13

Page 14: Virtual Prototyping in SpaceFibre System-on-Chip Design...Virtual Prototyping in SpaceFibre System-on-Chip Design Ilya Korobkov, Junior Researcher, ... running em b ed d ed so f t

Streaming via SpaceFibre port

© Accellera Systems Initiative 14

Output SpFi port #2

Network Memory Controller #1Sensor data

Background dataControl data

VideoAudio

Network Memory Controller #2

Tx Traffic generator #1

Output SpFi port #1

Tx Traffic generator #2

Rx Unit #1

Rx Unit #2Input SpFi

port #2

Input SpFi port #1

1.25 Gbit/s

1.25 Gbit/s

To test performance of SpFi ports for streaming we used traffics:• Video: SVGA RGB 60Hz, 1.42Mbytes, accepted latency < 16 ms

• Audio: Kodec G.711, 160 bytes, 0.05 packet/ms, accepted latency < 100 ms

• Sensor data: 1Kbytes, 50 packet/ms, accepted latency < 5 ms

• Control data: 260 bytes, 0.02 packet/ms, accepted latency < 0.1 ms

• Background: 1Kbytes, 25 packet/ms, accepted latency – not defined

Page 15: Virtual Prototyping in SpaceFibre System-on-Chip Design...Virtual Prototyping in SpaceFibre System-on-Chip Design Ilya Korobkov, Junior Researcher, ... running em b ed d ed so f t

SpaceFibre port model

© Accellera Systems Initiative 15

Port consists of input and output interfaces

Port includes:• Virtual Channels (VC) with 1Kbytes buffers for data storage• Medium Access Controller multiplexes output data and provides QoS• VC de-multiplexer distributes input data between VCs

INPUT SpFi portOUTPUT SpFi port

Rx UnitVC2 buffer

VC1 buffer

VC3 bufferLinkTx Traffic

generator

Sensor data

Control data

BackgroundVC2 buffer

VC1 buffer

VC3 buffer

Me

diu

m A

cce

ss

Co

ntr

ole

r

VC

de

-mu

litp

lexe

r

1.25 Gbit/s

VC4 bufferAudio

VC5 bufferVideo

VC4 buffer

VC5 buffer

INPUT SpFi port #1OUTPUT SpFi port #1

Rx UnitVC2 buffer

VC1 buffer

VC3 buffer

LinkTx Traffic generator

Sensor data

Control data

BackgroundVC2 buffer

VC1 buffer

VC3 buffer

Me

diu

m A

cce

ss

Co

ntr

olle

r

VC

de

-m

ulit

ple

xer

1.25 Gbit/s

Page 16: Virtual Prototyping in SpaceFibre System-on-Chip Design...Virtual Prototyping in SpaceFibre System-on-Chip Design Ilya Korobkov, Junior Researcher, ... running em b ed d ed so f t

What is SpaceFibre QoS?

© Accellera Systems Initiative 16

Medium Access Controller provides QoS:Sheduled: time is separated into max 256 time-slots during which VC can be

scheduled to send data

The current time-slot is indicated by broadcast time values

Priority: 16 priorities. VC with high priority will be entitled to send data first

Bandwidth Reserved: determines the limitations of the link utilization by VC

Video frame 1 Video frame 2

16 ms

TimeSlots for VC5

Slots forother VCs

...... ...

Problem: SpaceFibre limits amount of priorities and time-slots

Page 17: Virtual Prototyping in SpaceFibre System-on-Chip Design...Virtual Prototyping in SpaceFibre System-on-Chip Design Ilya Korobkov, Junior Researcher, ... running em b ed d ed so f t

Schedule Compaction: Priority + Scheduled QoS

© Accellera Systems Initiative 17

If VC scheduled in the time-slotdoes not have data to send,other VCs are permitted to usethe wasted bandwidth

Streaming video

Slot 187Slot 185 Slot 186

Time

Slot 188 Slot 189Slot 184Slot 182 Slot 183...

two traffics are assignedto one time-slot

VC4, priority = 15 (low)VC5, priority = 14 (high)

...Slot 190

Schedule Compaction –

Audio1Audio2

The Rule: VC5 must have higher priority than VC4 to guarantee that VC5 will

be entitled to finish sending video frames. Then VC4 can send audio data

In general case, VC shall compete with others for sending data based on the priority

Size of video frame

TimeSlots for sending

video frame

Wasted

bandwidth

Streaming video

Slot 187Slot 185 Slot 186 Slot 190Slot 188 Slot 189Slot 184Slot 182 Slot 183...

Audio1

...

Audio2

Page 18: Virtual Prototyping in SpaceFibre System-on-Chip Design...Virtual Prototyping in SpaceFibre System-on-Chip Design Ilya Korobkov, Junior Researcher, ... running em b ed d ed so f t

SpFi port performance testing (1/4)

© Accellera Systems Initiative 18

Situation: port #2 was disabled. All data was passed through the port #1

Result:

Output SpFi port #2

Network Memory Controller #1

Sensor dataBackground data

Control data

VideoAudio

Network Memory Controller #2

Tx Traffic generator #1

Output SpFi port #1

Tx Traffic generator #2

Rx Unit #1

Rx Unit #2Input SpFi

port #2

Input SpFi port #1

Overload!

Latency, ms

packets

Max acceptable latency = 5 ms

sensor data were delayed for too much time, because the link was occupied by a video traffic. Sensor latency – unacceptable

Page 19: Virtual Prototyping in SpaceFibre System-on-Chip Design...Virtual Prototyping in SpaceFibre System-on-Chip Design Ilya Korobkov, Junior Researcher, ... running em b ed d ed so f t

SpFi port performance testing (2/4)

© Accellera Systems Initiative 19

SpaceFibre Solution: use Schedule Compaction to get delivery latency determinism

TimeSlots for sending

video frame via VC 5

Idle time

Streaming video

Slot 187Slot 185 Slot 186 Slot 190Slot 188 Slot 189Slot 184Slot 182 Slot 183...

Sensordata 1

...

Sensordata 2

VC1, priority = 1VC5, priority = 1Reason: video VC priority is not higher than sensor VC priority –>schedule compaction doesn‘t work –> idle time

Max acceptable latency = 5 msLatency, ms

packets

Result:

But there is problem – idle virtual channel:not transferred max possible amount ofsensor data

all data were delivered withacceptable latencies

Page 20: Virtual Prototyping in SpaceFibre System-on-Chip Design...Virtual Prototyping in SpaceFibre System-on-Chip Design Ilya Korobkov, Junior Researcher, ... running em b ed d ed so f t

SpFi port performance testing (3/4)

© Accellera Systems Initiative 20

Our solution: use Schedule Compaction with Adaptive Data Streaming Service

ADSS can dynamically change VC priorities and time value that defines the current time-slot. It removes the limitations of priorities and time-slots.

The increment of transmitted sensor data is up to 2.7%

256 time-slots

Result: 1) no idle virtual channel 2) more time-slots for scheduling: from 256 to 512

Page 21: Virtual Prototyping in SpaceFibre System-on-Chip Design...Virtual Prototyping in SpaceFibre System-on-Chip Design Ilya Korobkov, Junior Researcher, ... running em b ed d ed so f t

SpFi port performance testing(4/4)

© Accellera Systems Initiative 21

The increment by 2.7%: is it a small result?

It’s good result for spacecraft, because the reliability was improved!

The increment of transmitted sensor

data is up to 10.5%

Packet size: 1.33 packet/ms

Packet rate: 260 bytes

256 time-slots

Result depends on traffic and schedule:

Page 22: Virtual Prototyping in SpaceFibre System-on-Chip Design...Virtual Prototyping in SpaceFibre System-on-Chip Design Ilya Korobkov, Junior Researcher, ... running em b ed d ed so f t

Conclusion

© Accellera Systems Initiative 22

SystemC/TLM 2.0 languages

They allowed to perform simulation of the Network Memory Controller project

and to analyze performance of SpaceFibre ports

OVP technology andCadence VSP Software

Page 23: Virtual Prototyping in SpaceFibre System-on-Chip Design...Virtual Prototyping in SpaceFibre System-on-Chip Design Ilya Korobkov, Junior Researcher, ... running em b ed d ed so f t

Thank you for attention!

Questions?

Feel free to contact with me

e-mail: [email protected]

© Accellera Systems Initiative 23


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